Searched refs:CSR2 (Results 1 - 14 of 14) sorted by relevance

/drivers/net/ethernet/amd/
H A Ddepca.h27 #define CSR2 2 macro
H A Dariadne.h64 #define CSR2 0x0200 /* - IADR[23:16] */ macro
H A Datarilance.c305 #define CSR2 2 /* init block addr (high) */ macro
656 REGA( CSR2 ) = 0;
H A Dsun3lance.c204 #define CSR2 2 /* init block addr (high) */ macro
503 REGA(CSR2) = dvma_vtob(&(MEM->init)) >> 16;
H A Dni65.c152 #define CSR2 0x02 macro
591 writereg(pib >> 16,CSR2);
H A Ddepca.c1200 outw(CSR2, DEPCA_ADDR); /* initialisation block address MSW */
1895 outw(CSR2, DEPCA_ADDR);
1896 printk("CSR2&1: 0x%4.4x", inw(DEPCA_DATA));
/drivers/staging/media/dt3155v4l/
H A Ddt3155v4l.h59 #define CSR2 0x10 macro
113 /* CSR2 bit masks */
H A Ddt3155v4l.c213 write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD);
369 write_i2c_reg_nowait(ipd->regs, CSR2, ipd->csr2);
783 write_i2c_reg(pd->regs, CSR2, pd->csr2 | SYNC_SNTL);
786 write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | SYNC_SNTL);
788 read_i2c_reg(pd->regs, CSR2, &tmp);
791 write_i2c_reg(pd->regs, CSR2, pd->csr2);
/drivers/net/ethernet/dec/tulip/
H A Dtulip.h108 CSR2 = 0x10, enumerator in enum:tulip_offsets
352 0x02000000 means use the ring start address in CSR2/3.
H A Dxircom_cb.c49 #define CSR2 0x10 macro
527 This is accomplished by writing to the CSR2 port. The documentation
536 outl(val, card->io_port + CSR2);
H A Dinterrupt.c91 iowrite32(0x01, tp->base_addr + CSR2);
H A Dtulip_core.c495 iowrite32(0, ioaddr + CSR2); /* Rx poll demand */
/drivers/net/wireless/rt2x00/
H A Drt2400pci.h82 * CSR2: System admin status register (invalid).
84 #define CSR2 0x0008 macro
H A Drt2500pci.h93 * CSR2: System admin status register (invalid).
95 #define CSR2 0x0008 macro

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