Searched refs:CSR5 (Results 1 - 12 of 12) sorted by relevance
/drivers/net/ethernet/dec/tulip/ |
H A D | interrupt.c | 87 if(((ioread32(tp->base_addr + CSR5)>>17)&0x07) == 4) { 129 if (ioread32(tp->base_addr + CSR5) == 0xffffffff) { 134 iowrite32((RxIntr | RxNoBuf), tp->base_addr + CSR5); 270 } while ((ioread32(tp->base_addr + CSR5) & RxIntr)); 531 csr5 = ioread32(ioaddr + CSR5); 558 iowrite32(csr5 & 0x0001ff3f, ioaddr + CSR5); 562 iowrite32(csr5 & 0x0001ffff, ioaddr + CSR5); 574 csr5, ioread32(ioaddr + CSR5)); 653 "The transmitter stopped. CSR5 is %x, CSR6 %x, new CSR6 %x\n", 712 iowrite32(0x0800f7ba, ioaddr + CSR5); [all...] |
H A D | pnic.c | 59 netdev_dbg(dev, "PNIC link changed state %08x, CSR5 %08x\n", 61 if (ioread32(ioaddr + CSR5) & TPLnkFail) { 75 } else if (ioread32(ioaddr + CSR5) & TPLnkPass) { 112 int csr5 = ioread32(ioaddr + CSR5); 115 netdev_dbg(dev, "PNIC timer PHY status %08x, %s CSR5 %08x\n", 126 netdev_dbg(dev, "%s link beat failed, CSR12 %04x, CSR5 %08x, PHY %03x\n", 129 ioread32(ioaddr + CSR5),
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H A D | tulip.h | 111 CSR5 = 0x28, enumerator in enum:tulip_offsets 138 /* The bits in the CSR5 status registers, mostly interrupt sources. */ 158 /* bit mask for CSR5 TX/RX process state */ 543 while (--i && (ioread32(ioaddr + CSR5) & (CSR5_TS|CSR5_RS))) 547 netdev_dbg(tp->dev, "tulip_stop_rxtx() failed (CSR5 0x%x CSR6 0x%x)\n", 548 ioread32(ioaddr + CSR5),
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H A D | xircom_cb.c | 52 #define CSR5 0x28 macro 318 status = inl(card->io_port+CSR5); 348 outl(status,card->io_port+CSR5); 625 val = inl(card->io_port + CSR5); /* Status register */ 633 outl(val, card->io_port + CSR5); 647 val = inl(card->io_port + CSR5); /* Status register */ 663 val = inl(card->io_port + CSR5); /* Status register */
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H A D | timer.c | 30 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR6),
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H A D | tulip_core.c | 446 iowrite32(ioread32(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5); local 454 } else if (ioread32(ioaddr + CSR5) & TPLnkPass) 492 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5); 498 netdev_dbg(dev, "Done tulip_up(), CSR0 %08x, CSR5 %08x CSR6 %08x\n", 500 ioread32(ioaddr + CSR5), 556 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12), 565 (int)ioread32(ioaddr + CSR5), 572 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12)); 842 ioread32 (ioaddr + CSR5)); [all...] |
H A D | 21142.c | 151 "21143 link status interrupt %08x, CSR5 %x, %08x\n", 206 netdev_dbg(dev, " Restarting Tx and Rx, CSR5 is %08x\n", 207 ioread32(ioaddr + CSR5));
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/drivers/net/ethernet/amd/ |
H A D | pcnet32.c | 208 #define CSR5 5 macro 1080 /* set SUSPEND (SPND) - CSR5 bit 0 */ 1081 csr5 = a->read_csr(ioaddr, CSR5); 1082 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND); 1086 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) { 1417 /* clear SUSPEND (SPND) - CSR5 bit 0 */ 1418 csr5 = a->read_csr(ioaddr, CSR5); 1419 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND)); 2629 /* clear SUSPEND (SPND) - CSR5 bit 0 */ 2630 csr5 = lp->a->read_csr(ioaddr, CSR5); [all...] |
/drivers/net/wireless/rt2x00/ |
H A D | rt2400pci.h | 103 * CSR5: BSSID register 0. 105 #define CSR5 0x0014 macro
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H A D | rt2500pci.h | 114 * CSR5: BSSID register 0. 116 #define CSR5 0x0014 macro
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H A D | rt2400pci.c | 317 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
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H A D | rt2500pci.c | 323 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
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