Searched refs:CSR8 (Results 1 - 12 of 12) sorted by relevance
| /drivers/net/wireless/rt2x00/ |
| H A D | rt2400pci.c | 988 rt2x00pci_register_read(rt2x00dev, CSR8, ®);
994 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1318 rt2x00pci_register_read(rt2x00dev, CSR8, ®);
1320 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1343 rt2x00pci_register_read(rt2x00dev, CSR8, ®);
1347 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1417 rt2x00pci_register_read(rt2x00dev, CSR8, ®);
1419 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
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| H A D | rt2500pci.c | 1143 rt2x00pci_register_read(rt2x00dev, CSR8, ®);
1149 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1450 rt2x00pci_register_read(rt2x00dev, CSR8, ®);
1452 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1475 rt2x00pci_register_read(rt2x00dev, CSR8, ®);
1479 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1549 rt2x00pci_register_read(rt2x00dev, CSR8, ®);
1551 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
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| H A D | rt2400pci.h | 139 * CSR8: Interrupt mask register.
149 #define CSR8 0x0020 macro
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| H A D | rt2500pci.h | 177 * CSR8: Interrupt mask register.
200 #define CSR8 0x0020 macro
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| /drivers/net/ethernet/amd/ |
| H A D | ariadne.h | 68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */ macro
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| H A D | ariadne.c | 433 lance->RAP = CSR8; /* Logical Address Filter, LADRF[15:0] */
670 lance->RAP = CSR8 + (i << 8);
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| H A D | atarilance.c | 307 #define CSR8 8 /* address filter */ macro
1105 REGA( CSR8+i ) = multicast_table[i];
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| H A D | sun3lance.c | 206 #define CSR8 8 /* address filter */ macro
924 REGA( CSR8+i ) = multicast_table[i];
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| /drivers/net/ethernet/dec/tulip/ |
| H A D | interrupt.c | 683 dev->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
799 if ((missed = ioread32(ioaddr + CSR8) & 0x1ffff)) {
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| H A D | tulip.h | 114 CSR8 = 0x40, enumerator in enum:tulip_offsets
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| H A D | tulip_core.c | 780 dev->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
861 dev->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
1522 ioread32(ioaddr + CSR8);
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| H A D | xircom_cb.c | 55 #define CSR8 0x40 macro
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