| /drivers/gpu/drm/i2c/ |
| H A D | ch7006_mode.c | 135 #define MODE(f, hd, vd, ht, vt, hsynp, vsynp, \ macro
146 MODE(21000, 512, 384, 840, 500, N, N, 181.797557582, 5_4, 0x6, PAL_LIKE),
147 MODE(26250, 512, 384, 840, 625, N, N, 145.438046066, 1_1, 0x1, PAL_LIKE),
148 MODE(20140, 512, 384, 800, 420, N, N, 213.257083791, 5_4, 0x4, NTSC_LIKE),
149 MODE(24671, 512, 384, 784, 525, N, N, 174.0874153, 1_1, 0x3, NTSC_LIKE),
150 MODE(28125, 720, 400, 1125, 500, N, N, 135.742176298, 5_4, 0x6, PAL_LIKE),
151 MODE(34875, 720, 400, 1116, 625, N, N, 109.469496898, 1_1, 0x1, PAL_LIKE),
152 MODE(23790, 720, 400, 945, 420, N, N, 160.475642016, 5_4, 0x4, NTSC_LIKE),
153 MODE(29455, 720, 400, 936, 525, N, N, 129.614941843, 1_1, 0x3, NTSC_LIKE),
154 MODE(2500
[all...] |
| /drivers/media/video/ |
| H A D | omap1_camera.c | 80 /* MODE bit shifts */
440 u32 mode = CAM_READ_CACHE(pcdev, MODE) & ~EN_V_DOWN;
455 CAM_WRITE(pcdev, MODE, mode | RAZ_FIFO);
471 CAM_WRITE(pcdev, MODE, mode);
484 u32 mode = CAM_READ_CACHE(pcdev, MODE);
486 CAM_WRITE(pcdev, MODE, mode & ~(IRQ_MASK | DMA));
524 mode = CAM_READ_CACHE(pcdev, MODE) & ~THRESHOLD_MASK;
526 CAM_WRITE(pcdev, MODE, mode | EN_FIFO_FULL | DMA);
749 CAM_WRITE(pcdev, MODE,
750 CAM_READ_CACHE(pcdev, MODE)
[all...] |
| H A D | tw9910.c | 88 #define CLMD 0x33 /* CLAMP MODE */
146 #define MODE 0x80 /* 0 : CCIR601 compatible YCrCb 4:2:2 format */ macro
|
| /drivers/staging/comedi/drivers/ |
| H A D | das6402.c | 89 #define MODE 0x10 macro
272 outb_p(MODE, dev->iobase + 11);
273 b = BIP | SEM | MODE | GAIN | FIFOHFULL;
|
| /drivers/net/ethernet/amd/ |
| H A D | am79c961a.h | 84 #define MODE 15 macro
|
| H A D | am79c961a.c | 253 write_ireg (dev->base_addr, 2, 0x0000); /* MODE register selects media */
261 write_rreg (dev->base_addr, MODE, mode);
416 write_rreg(dev->base_addr, MODE, mode);
|
| /drivers/media/dvb/frontends/ |
| H A D | bcm3510.c | 493 cmd.ACQUIRE0.MODE = 0x1;
498 cmd.ACQUIRE0.MODE = 0x2;
504 cmd.ACQUIRE0.MODE = 0x3;
507 cmd.ACQUIRE0.MODE = 0x4;
510 cmd.ACQUIRE0.MODE = 0x5;
513 cmd.ACQUIRE0.MODE = 0x6;
516 cmd.ACQUIRE0.MODE = 0x7;
520 cmd.ACQUIRE0.MODE = 0x8;
525 cmd.ACQUIRE0.MODE = 0x9;
|
| H A D | bcm3510_priv.h | 189 u8 MODE :4; member in struct:bcm3510_hab_cmd_ext_acquire::__anon1498
214 u8 MODE :4; member in struct:bcm3510_hab_cmd_int_acquire::__anon1500
|
| /drivers/char/pcmcia/ |
| H A D | synclink_cs.c | 254 #define MODE 0x22 macro
2917 /* MODE
2934 write_reg(info, CHB + MODE, val);
3018 /* MODE:00 TLP Test Loop, 1=loopback enabled */
3019 val = read_reg(info, CHA + MODE) | BIT0;
3020 write_reg(info, CHA + MODE, val);
3058 /* MODE
3077 write_reg(info, CHA + MODE, val);
3269 /* MODE:03 RAC Receiver Active, 0=inactive */
3270 clear_reg_bits(info, CHA + MODE, BIT
[all...] |
| /drivers/net/ethernet/oki-semi/pch_gbe/ |
| H A D | pch_gbe.h | 52 u32 MODE; member in struct:pch_gbe_regs
|
| H A D | pch_gbe_main.c | 399 iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
1093 iowrite32(mode, &hw->reg->MODE);
|
| /drivers/net/wan/ |
| H A D | pc300-falc-lh.h | 47 /* MODE (Mode Register)
1127 #define MODE 0x03 /* Mode Reg */ macro
|
| H A D | pc300_drv.c | 1167 cpc_writeb(falcbase + F_REG(MODE, ch), 0);
1169 cpc_writeb(falcbase + F_REG(MODE, ch),
1170 cpc_readb(falcbase + F_REG(MODE, ch)) |
|