1/* 2 * Support for the Broadcom BCM3510 ATSC demodulator (1st generation Air2PC) 3 * 4 * Copyright (C) 2001-5, B2C2 inc. 5 * 6 * GPL/Linux driver written by Patrick Boettcher <patrick.boettcher@desy.de> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22#ifndef __BCM3510_PRIV_H__ 23#define __BCM3510_PRIV_H__ 24 25#define PACKED __attribute__((packed)) 26 27#undef err 28#define err(format, arg...) printk(KERN_ERR "bcm3510: " format "\n" , ## arg) 29#undef info 30#define info(format, arg...) printk(KERN_INFO "bcm3510: " format "\n" , ## arg) 31#undef warn 32#define warn(format, arg...) printk(KERN_WARNING "bcm3510: " format "\n" , ## arg) 33 34 35#define PANASONIC_FIRST_IF_BASE_IN_KHz 1407500 36#define BCM3510_SYMBOL_RATE 5381000 37 38typedef union { 39 u8 raw; 40 41 struct { 42 u8 CTL :8; 43 } TSTCTL_2e; 44 45 u8 LDCERC_4e; 46 u8 LDUERC_4f; 47 u8 LD_BER0_65; 48 u8 LD_BER1_66; 49 u8 LD_BER2_67; 50 u8 LD_BER3_68; 51 52 struct { 53 u8 RESET :1; 54 u8 IDLE :1; 55 u8 STOP :1; 56 u8 HIRQ0 :1; 57 u8 HIRQ1 :1; 58 u8 na0 :1; 59 u8 HABAV :1; 60 u8 na1 :1; 61 } HCTL1_a0; 62 63 struct { 64 u8 na0 :1; 65 u8 IDLMSK :1; 66 u8 STMSK :1; 67 u8 I0MSK :1; 68 u8 I1MSK :1; 69 u8 na1 :1; 70 u8 HABMSK :1; 71 u8 na2 :1; 72 } HCTLMSK_a1; 73 74 struct { 75 u8 RESET :1; 76 u8 IDLE :1; 77 u8 STOP :1; 78 u8 RUN :1; 79 u8 HABAV :1; 80 u8 MEMAV :1; 81 u8 ALDONE :1; 82 u8 REIRQ :1; 83 } APSTAT1_a2; 84 85 struct { 86 u8 RSTMSK :1; 87 u8 IMSK :1; 88 u8 SMSK :1; 89 u8 RMSK :1; 90 u8 HABMSK :1; 91 u8 MAVMSK :1; 92 u8 ALDMSK :1; 93 u8 REMSK :1; 94 } APMSK1_a3; 95 96 u8 APSTAT2_a4; 97 u8 APMSK2_a5; 98 99 struct { 100 u8 HABADR :7; 101 u8 na :1; 102 } HABADR_a6; 103 104 u8 HABDATA_a7; 105 106 struct { 107 u8 HABR :1; 108 u8 LDHABR :1; 109 u8 APMSK :1; 110 u8 HMSK :1; 111 u8 LDMSK :1; 112 u8 na :3; 113 } HABSTAT_a8; 114 115 u8 MADRH_a9; 116 u8 MADRL_aa; 117 u8 MDATA_ab; 118 119 struct { 120#define JDEC_WAIT_AT_RAM 0x7 121#define JDEC_EEPROM_LOAD_WAIT 0x4 122 u8 JDEC :3; 123 u8 na :5; 124 } JDEC_ca; 125 126 struct { 127 u8 REV :4; 128 u8 LAYER :4; 129 } REVID_e0; 130 131 struct { 132 u8 unk0 :1; 133 u8 CNTCTL :1; 134 u8 BITCNT :1; 135 u8 unk1 :1; 136 u8 RESYNC :1; 137 u8 unk2 :3; 138 } BERCTL_fa; 139 140 struct { 141 u8 CSEL0 :1; 142 u8 CLKED0 :1; 143 u8 CSEL1 :1; 144 u8 CLKED1 :1; 145 u8 CLKLEV :1; 146 u8 SPIVAR :1; 147 u8 na :2; 148 } TUNSET_fc; 149 150 struct { 151 u8 CLK :1; 152 u8 DATA :1; 153 u8 CS0 :1; 154 u8 CS1 :1; 155 u8 AGCSEL :1; 156 u8 na0 :1; 157 u8 TUNSEL :1; 158 u8 na1 :1; 159 } TUNCTL_fd; 160 161 u8 TUNSEL0_fe; 162 u8 TUNSEL1_ff; 163 164} bcm3510_register_value; 165 166/* HAB commands */ 167 168/* version */ 169#define CMD_GET_VERSION_INFO 0x3D 170#define MSGID_GET_VERSION_INFO 0x15 171struct bcm3510_hab_cmd_get_version_info { 172 u8 microcode_version; 173 u8 script_version; 174 u8 config_version; 175 u8 demod_version; 176} PACKED; 177 178#define BCM3510_DEF_MICROCODE_VERSION 0x0E 179#define BCM3510_DEF_SCRIPT_VERSION 0x06 180#define BCM3510_DEF_CONFIG_VERSION 0x01 181#define BCM3510_DEF_DEMOD_VERSION 0xB1 182 183/* acquire */ 184#define CMD_ACQUIRE 0x38 185 186#define MSGID_EXT_TUNER_ACQUIRE 0x0A 187struct bcm3510_hab_cmd_ext_acquire { 188 struct { 189 u8 MODE :4; 190 u8 BW :1; 191 u8 FA :1; 192 u8 NTSCSWEEP :1; 193 u8 OFFSET :1; 194 } PACKED ACQUIRE0; /* control_byte */ 195 196 struct { 197 u8 IF_FREQ :3; 198 u8 zero0 :1; 199 u8 SYM_RATE :3; 200 u8 zero1 :1; 201 } PACKED ACQUIRE1; /* sym_if */ 202 203 u8 IF_OFFSET0; /* IF_Offset_10hz */ 204 u8 IF_OFFSET1; 205 u8 SYM_OFFSET0; /* SymbolRateOffset */ 206 u8 SYM_OFFSET1; 207 u8 NTSC_OFFSET0; /* NTSC_Offset_10hz */ 208 u8 NTSC_OFFSET1; 209} PACKED; 210 211#define MSGID_INT_TUNER_ACQUIRE 0x0B 212struct bcm3510_hab_cmd_int_acquire { 213 struct { 214 u8 MODE :4; 215 u8 BW :1; 216 u8 FA :1; 217 u8 NTSCSWEEP :1; 218 u8 OFFSET :1; 219 } PACKED ACQUIRE0; /* control_byte */ 220 221 struct { 222 u8 IF_FREQ :3; 223 u8 zero0 :1; 224 u8 SYM_RATE :3; 225 u8 zero1 :1; 226 } PACKED ACQUIRE1; /* sym_if */ 227 228 u8 TUNER_FREQ0; 229 u8 TUNER_FREQ1; 230 u8 TUNER_FREQ2; 231 u8 TUNER_FREQ3; 232 u8 IF_OFFSET0; /* IF_Offset_10hz */ 233 u8 IF_OFFSET1; 234 u8 SYM_OFFSET0; /* SymbolRateOffset */ 235 u8 SYM_OFFSET1; 236 u8 NTSC_OFFSET0; /* NTSC_Offset_10hz */ 237 u8 NTSC_OFFSET1; 238} PACKED; 239 240/* modes */ 241#define BCM3510_QAM16 = 0x01 242#define BCM3510_QAM32 = 0x02 243#define BCM3510_QAM64 = 0x03 244#define BCM3510_QAM128 = 0x04 245#define BCM3510_QAM256 = 0x05 246#define BCM3510_8VSB = 0x0B 247#define BCM3510_16VSB = 0x0D 248 249/* IF_FREQS */ 250#define BCM3510_IF_TERRESTRIAL 0x0 251#define BCM3510_IF_CABLE 0x1 252#define BCM3510_IF_USE_CMD 0x7 253 254/* SYM_RATE */ 255#define BCM3510_SR_8VSB 0x0 /* 5381119 s/sec */ 256#define BCM3510_SR_256QAM 0x1 /* 5360537 s/sec */ 257#define BCM3510_SR_16QAM 0x2 /* 5056971 s/sec */ 258#define BCM3510_SR_MISC 0x3 /* 5000000 s/sec */ 259#define BCM3510_SR_USE_CMD 0x7 260 261/* special symbol rate */ 262#define CMD_SET_VALUE_NOT_LISTED 0x2d 263#define MSGID_SET_SYMBOL_RATE_NOT_LISTED 0x0c 264struct bcm3510_hab_cmd_set_sr_not_listed { 265 u8 HOST_SYM_RATE0; 266 u8 HOST_SYM_RATE1; 267 u8 HOST_SYM_RATE2; 268 u8 HOST_SYM_RATE3; 269} PACKED; 270 271/* special IF */ 272#define MSGID_SET_IF_FREQ_NOT_LISTED 0x0d 273struct bcm3510_hab_cmd_set_if_freq_not_listed { 274 u8 HOST_IF_FREQ0; 275 u8 HOST_IF_FREQ1; 276 u8 HOST_IF_FREQ2; 277 u8 HOST_IF_FREQ3; 278} PACKED; 279 280/* auto reacquire */ 281#define CMD_AUTO_PARAM 0x2a 282#define MSGID_AUTO_REACQUIRE 0x0e 283struct bcm3510_hab_cmd_auto_reacquire { 284 u8 ACQ :1; /* on/off*/ 285 u8 unused :7; 286} PACKED; 287 288#define MSGID_SET_RF_AGC_SEL 0x12 289struct bcm3510_hab_cmd_set_agc { 290 u8 LVL :1; 291 u8 unused :6; 292 u8 SEL :1; 293} PACKED; 294 295#define MSGID_SET_AUTO_INVERSION 0x14 296struct bcm3510_hab_cmd_auto_inversion { 297 u8 AI :1; 298 u8 unused :7; 299} PACKED; 300 301 302/* bert control */ 303#define CMD_STATE_CONTROL 0x12 304#define MSGID_BERT_CONTROL 0x0e 305#define MSGID_BERT_SET 0xfa 306struct bcm3510_hab_cmd_bert_control { 307 u8 BE :1; 308 u8 unused :7; 309} PACKED; 310 311#define MSGID_TRI_STATE 0x2e 312struct bcm3510_hab_cmd_tri_state { 313 u8 RE :1; /* a/d ram port pins */ 314 u8 PE :1; /* baud clock pin */ 315 u8 AC :1; /* a/d clock pin */ 316 u8 BE :1; /* baud clock pin */ 317 u8 unused :4; 318} PACKED; 319 320 321/* tune */ 322#define CMD_TUNE 0x38 323#define MSGID_TUNE 0x16 324struct bcm3510_hab_cmd_tune_ctrl_data_pair { 325 struct { 326#define BITS_8 0x07 327#define BITS_7 0x06 328#define BITS_6 0x05 329#define BITS_5 0x04 330#define BITS_4 0x03 331#define BITS_3 0x02 332#define BITS_2 0x01 333#define BITS_1 0x00 334 u8 size :3; 335 u8 unk :2; 336 u8 clk_off :1; 337 u8 cs0 :1; 338 u8 cs1 :1; 339 340 } PACKED ctrl; 341 342 u8 data; 343} PACKED; 344 345struct bcm3510_hab_cmd_tune { 346 u8 length; 347 u8 clock_width; 348 u8 misc; 349 u8 TUNCTL_state; 350 351 struct bcm3510_hab_cmd_tune_ctrl_data_pair ctl_dat[16]; 352} PACKED; 353 354#define CMD_STATUS 0x38 355#define MSGID_STATUS1 0x08 356struct bcm3510_hab_cmd_status1 { 357 struct { 358 u8 EQ_MODE :4; 359 u8 reserved :2; 360 u8 QRE :1; /* if QSE and the spectrum is inversed */ 361 u8 QSE :1; /* automatic spectral inversion */ 362 } PACKED STATUS0; 363 364 struct { 365 u8 RECEIVER_LOCK :1; 366 u8 FEC_LOCK :1; 367 u8 OUT_PLL_LOCK :1; 368 u8 reserved :5; 369 } PACKED STATUS1; 370 371 struct { 372 u8 reserved :2; 373 u8 BW :1; 374 u8 NTE :1; /* NTSC filter sweep enabled */ 375 u8 AQI :1; /* currently acquiring */ 376 u8 FA :1; /* fast acquisition */ 377 u8 ARI :1; /* auto reacquire */ 378 u8 TI :1; /* programming the tuner */ 379 } PACKED STATUS2; 380 u8 STATUS3; 381 u8 SNR_EST0; 382 u8 SNR_EST1; 383 u8 TUNER_FREQ0; 384 u8 TUNER_FREQ1; 385 u8 TUNER_FREQ2; 386 u8 TUNER_FREQ3; 387 u8 SYM_RATE0; 388 u8 SYM_RATE1; 389 u8 SYM_RATE2; 390 u8 SYM_RATE3; 391 u8 SYM_OFFSET0; 392 u8 SYM_OFFSET1; 393 u8 SYM_ERROR0; 394 u8 SYM_ERROR1; 395 u8 IF_FREQ0; 396 u8 IF_FREQ1; 397 u8 IF_FREQ2; 398 u8 IF_FREQ3; 399 u8 IF_OFFSET0; 400 u8 IF_OFFSET1; 401 u8 IF_ERROR0; 402 u8 IF_ERROR1; 403 u8 NTSC_FILTER0; 404 u8 NTSC_FILTER1; 405 u8 NTSC_FILTER2; 406 u8 NTSC_FILTER3; 407 u8 NTSC_OFFSET0; 408 u8 NTSC_OFFSET1; 409 u8 NTSC_ERROR0; 410 u8 NTSC_ERROR1; 411 u8 INT_AGC_LEVEL0; 412 u8 INT_AGC_LEVEL1; 413 u8 EXT_AGC_LEVEL0; 414 u8 EXT_AGC_LEVEL1; 415} PACKED; 416 417#define MSGID_STATUS2 0x14 418struct bcm3510_hab_cmd_status2 { 419 struct { 420 u8 EQ_MODE :4; 421 u8 reserved :2; 422 u8 QRE :1; 423 u8 QSR :1; 424 } PACKED STATUS0; 425 struct { 426 u8 RL :1; 427 u8 FL :1; 428 u8 OL :1; 429 u8 reserved :5; 430 } PACKED STATUS1; 431 u8 SYMBOL_RATE0; 432 u8 SYMBOL_RATE1; 433 u8 SYMBOL_RATE2; 434 u8 SYMBOL_RATE3; 435 u8 LDCERC0; 436 u8 LDCERC1; 437 u8 LDCERC2; 438 u8 LDCERC3; 439 u8 LDUERC0; 440 u8 LDUERC1; 441 u8 LDUERC2; 442 u8 LDUERC3; 443 u8 LDBER0; 444 u8 LDBER1; 445 u8 LDBER2; 446 u8 LDBER3; 447 struct { 448 u8 MODE_TYPE :4; /* acquire mode 0 */ 449 u8 reservd :4; 450 } MODE_TYPE; 451 u8 SNR_EST0; 452 u8 SNR_EST1; 453 u8 SIGNAL; 454} PACKED; 455 456#define CMD_SET_RF_BW_NOT_LISTED 0x3f 457#define MSGID_SET_RF_BW_NOT_LISTED 0x11 458/* TODO */ 459 460#endif 461