Searched refs:VAL (Results 1 - 20 of 20) sorted by relevance

/drivers/watchdog/
H A Dit8712f_wdt.c63 #define VAL 0x2f /* The value to read/write */ macro
101 return inb(VAL);
107 outb(val, VAL);
114 val = inb(VAL) << 8;
116 val |= inb(VAL);
123 outb(ldn, VAL);
144 outb(0x02, VAL);
H A Dit87_wdt.c63 #define VAL 0x2f macro
183 outb(0x02, VAL);
190 outb(ldn, VAL);
196 return inb(VAL);
202 outb(val, VAL);
209 val = inb(VAL) << 8;
211 val |= inb(VAL);
218 outb(val >> 8, VAL);
220 outb(val, VAL);
/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_hdr.h711 #define QLC_DEV_CHECK_ACTIVE(VAL, FN) ((VAL) & (1 << (FN * 4)))
712 #define QLC_DEV_SET_REF_CNT(VAL, FN) ((VAL) |= (1 << (FN * 4)))
713 #define QLC_DEV_CLR_REF_CNT(VAL, FN) ((VAL) &= ~(1 << (FN * 4)))
714 #define QLC_DEV_SET_RST_RDY(VAL, FN) ((VAL) |= (1 << (FN * 4)))
715 #define QLC_DEV_SET_QSCNT_RDY(VAL, FN) ((VAL) |
[all...]
H A Dqlcnic.h794 #define QLCNIC_IS_LB_CONFIGURED(VAL) \
795 (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE))
/drivers/rtc/
H A Drtc-at32ap700x.c75 now = rtc_readl(rtc, VAL);
89 rtc_writel(rtc, VAL, now);
114 rtc_unix_time = rtc_readl(rtc, VAL);
145 if (rtc_readl(rtc, VAL) > rtc->alarm_time) {
179 rtc_writel(rtc, VAL, rtc->alarm_time);
237 * Do not reset VAL register, as it can hold an old time
/drivers/staging/comedi/drivers/
H A Ds626.h464 #define I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24))
465 #define I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16))
466 #define I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8))
H A Ds626.c534 #define I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24))
535 #define I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16))
536 #define I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8))
/drivers/scsi/
H A Dsun3x_esp.c44 #define dma_write32(VAL, REG) \
45 writel((VAL), esp->dma_regs + (REG))
49 #define dma_write32(VAL, REG) \
50 do { *(volatile u32 *)(esp->dma_regs + (REG)) = (VAL); } while (0)
H A Daha152x.h288 #define SETPORT(PORT, VAL) outb( (VAL), (PORT) )
H A Dmac_esp.c49 #define esp_write8(VAL, REG) mac_esp_write8(esp, VAL, REG)
H A Dsun_esp.c32 #define dma_write32(VAL, REG) \
33 sbus_writel((VAL), esp->dma_regs + (REG))
H A Desp_scsi.c104 #define esp_write8(VAL,REG) esp->ops->esp_write8(esp, VAL, REG)
/drivers/hwmon/
H A Dsmsc47b397.c55 #define VAL 0x2f /* The value to read/write */ macro
60 outb(val, VAL);
66 return inb(VAL);
H A Dsmsc47m1.c57 #define VAL 0x2f /* The value to read/write */ macro
63 outb(val, VAL);
70 return inb(VAL);
H A Dit87.c72 #define VAL 0x2f /* The value to read/write */ macro
84 return inb(VAL);
90 outb(val, VAL);
97 val = inb(VAL) << 8;
99 val |= inb(VAL);
106 outb(ldn, VAL);
127 outb(0x02, VAL);
/drivers/net/ethernet/freescale/fs_enet/
H A Dmii-fec.c47 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
H A Dmac-fcc.c73 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
/drivers/scsi/qla4xxx/
H A Dql4_nx.h719 #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0)
720 #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
/drivers/scsi/qla2xxx/
H A Dqla_nx.h704 #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0)
705 #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
/drivers/net/ethernet/qlogic/netxen/
H A Dnetxen_nic_hdr.h979 #define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)

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