1/* 2 * QLogic qlcnic NIC Driver 3 * Copyright (c) 2009-2010 QLogic Corporation 4 * 5 * See LICENSE.qlcnic for copyright and licensing details. 6 */ 7 8#ifndef _QLCNIC_H_ 9#define _QLCNIC_H_ 10 11#include <linux/module.h> 12#include <linux/kernel.h> 13#include <linux/types.h> 14#include <linux/ioport.h> 15#include <linux/pci.h> 16#include <linux/netdevice.h> 17#include <linux/etherdevice.h> 18#include <linux/ip.h> 19#include <linux/in.h> 20#include <linux/tcp.h> 21#include <linux/skbuff.h> 22#include <linux/firmware.h> 23 24#include <linux/ethtool.h> 25#include <linux/mii.h> 26#include <linux/timer.h> 27 28#include <linux/vmalloc.h> 29 30#include <linux/io.h> 31#include <asm/byteorder.h> 32#include <linux/bitops.h> 33#include <linux/if_vlan.h> 34 35#include "qlcnic_hdr.h" 36 37#define _QLCNIC_LINUX_MAJOR 5 38#define _QLCNIC_LINUX_MINOR 0 39#define _QLCNIC_LINUX_SUBVERSION 27 40#define QLCNIC_LINUX_VERSIONID "5.0.27" 41#define QLCNIC_DRV_IDC_VER 0x01 42#define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\ 43 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION)) 44 45#define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c)) 46#define _major(v) (((v) >> 24) & 0xff) 47#define _minor(v) (((v) >> 16) & 0xff) 48#define _build(v) ((v) & 0xffff) 49 50/* version in image has weird encoding: 51 * 7:0 - major 52 * 15:8 - minor 53 * 31:16 - build (little endian) 54 */ 55#define QLCNIC_DECODE_VERSION(v) \ 56 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16)) 57 58#define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2) 59#define QLCNIC_NUM_FLASH_SECTORS (64) 60#define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024) 61#define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \ 62 * QLCNIC_FLASH_SECTOR_SIZE) 63 64#define RCV_DESC_RINGSIZE(rds_ring) \ 65 (sizeof(struct rcv_desc) * (rds_ring)->num_desc) 66#define RCV_BUFF_RINGSIZE(rds_ring) \ 67 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc) 68#define STATUS_DESC_RINGSIZE(sds_ring) \ 69 (sizeof(struct status_desc) * (sds_ring)->num_desc) 70#define TX_BUFF_RINGSIZE(tx_ring) \ 71 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc) 72#define TX_DESC_RINGSIZE(tx_ring) \ 73 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc) 74 75#define QLCNIC_P3P_A0 0x50 76#define QLCNIC_P3P_C0 0x58 77 78#define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0) 79 80#define FIRST_PAGE_GROUP_START 0 81#define FIRST_PAGE_GROUP_END 0x100000 82 83#define P3P_MAX_MTU (9600) 84#define P3P_MIN_MTU (68) 85#define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */ 86 87#define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN) 88#define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU) 89#define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048 90#define QLCNIC_LRO_BUFFER_EXTRA 2048 91 92/* Opcodes to be used with the commands */ 93#define TX_ETHER_PKT 0x01 94#define TX_TCP_PKT 0x02 95#define TX_UDP_PKT 0x03 96#define TX_IP_PKT 0x04 97#define TX_TCP_LSO 0x05 98#define TX_TCP_LSO6 0x06 99#define TX_TCPV6_PKT 0x0b 100#define TX_UDPV6_PKT 0x0c 101 102/* Tx defines */ 103#define QLCNIC_MAX_FRAGS_PER_TX 14 104#define MAX_TSO_HEADER_DESC 2 105#define MGMT_CMD_DESC_RESV 4 106#define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \ 107 + MGMT_CMD_DESC_RESV) 108#define QLCNIC_MAX_TX_TIMEOUTS 2 109 110/* 111 * Following are the states of the Phantom. Phantom will set them and 112 * Host will read to check if the fields are correct. 113 */ 114#define PHAN_INITIALIZE_FAILED 0xffff 115#define PHAN_INITIALIZE_COMPLETE 0xff01 116 117/* Host writes the following to notify that it has done the init-handshake */ 118#define PHAN_INITIALIZE_ACK 0xf00f 119#define PHAN_PEG_RCV_INITIALIZED 0xff01 120 121#define NUM_RCV_DESC_RINGS 3 122 123#define RCV_RING_NORMAL 0 124#define RCV_RING_JUMBO 1 125 126#define MIN_CMD_DESCRIPTORS 64 127#define MIN_RCV_DESCRIPTORS 64 128#define MIN_JUMBO_DESCRIPTORS 32 129 130#define MAX_CMD_DESCRIPTORS 1024 131#define MAX_RCV_DESCRIPTORS_1G 4096 132#define MAX_RCV_DESCRIPTORS_10G 8192 133#define MAX_RCV_DESCRIPTORS_VF 2048 134#define MAX_JUMBO_RCV_DESCRIPTORS_1G 512 135#define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024 136 137#define DEFAULT_RCV_DESCRIPTORS_1G 2048 138#define DEFAULT_RCV_DESCRIPTORS_10G 4096 139#define DEFAULT_RCV_DESCRIPTORS_VF 1024 140#define MAX_RDS_RINGS 2 141 142#define get_next_index(index, length) \ 143 (((index) + 1) & ((length) - 1)) 144 145/* 146 * Following data structures describe the descriptors that will be used. 147 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when 148 * we are doing LSO (above the 1500 size packet) only. 149 */ 150 151#define FLAGS_VLAN_TAGGED 0x10 152#define FLAGS_VLAN_OOB 0x40 153 154#define qlcnic_set_tx_vlan_tci(cmd_desc, v) \ 155 (cmd_desc)->vlan_TCI = cpu_to_le16(v); 156#define qlcnic_set_cmd_desc_port(cmd_desc, var) \ 157 ((cmd_desc)->port_ctxid |= ((var) & 0x0F)) 158#define qlcnic_set_cmd_desc_ctxid(cmd_desc, var) \ 159 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0)) 160 161#define qlcnic_set_tx_port(_desc, _port) \ 162 ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)) 163 164#define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \ 165 ((_desc)->flags_opcode |= \ 166 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))) 167 168#define qlcnic_set_tx_frags_len(_desc, _frags, _len) \ 169 ((_desc)->nfrags__length = \ 170 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))) 171 172struct cmd_desc_type0 { 173 u8 tcp_hdr_offset; /* For LSO only */ 174 u8 ip_hdr_offset; /* For LSO only */ 175 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */ 176 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */ 177 178 __le64 addr_buffer2; 179 180 __le16 reference_handle; 181 __le16 mss; 182 u8 port_ctxid; /* 7:4 ctxid 3:0 port */ 183 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ 184 __le16 conn_id; /* IPSec offoad only */ 185 186 __le64 addr_buffer3; 187 __le64 addr_buffer1; 188 189 __le16 buffer_length[4]; 190 191 __le64 addr_buffer4; 192 193 u8 eth_addr[ETH_ALEN]; 194 __le16 vlan_TCI; 195 196} __attribute__ ((aligned(64))); 197 198/* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ 199struct rcv_desc { 200 __le16 reference_handle; 201 __le16 reserved; 202 __le32 buffer_length; /* allocated buffer length (usually 2K) */ 203 __le64 addr_buffer; 204} __packed; 205 206/* opcode field in status_desc */ 207#define QLCNIC_SYN_OFFLOAD 0x03 208#define QLCNIC_RXPKT_DESC 0x04 209#define QLCNIC_OLD_RXPKT_DESC 0x3f 210#define QLCNIC_RESPONSE_DESC 0x05 211#define QLCNIC_LRO_DESC 0x12 212 213/* for status field in status_desc */ 214#define STATUS_CKSUM_LOOP 0 215#define STATUS_CKSUM_OK 2 216 217/* owner bits of status_desc */ 218#define STATUS_OWNER_HOST (0x1ULL << 56) 219#define STATUS_OWNER_PHANTOM (0x2ULL << 56) 220 221/* Status descriptor: 222 0-3 port, 4-7 status, 8-11 type, 12-27 total_length 223 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset 224 53-55 desc_cnt, 56-57 owner, 58-63 opcode 225 */ 226#define qlcnic_get_sts_port(sts_data) \ 227 ((sts_data) & 0x0F) 228#define qlcnic_get_sts_status(sts_data) \ 229 (((sts_data) >> 4) & 0x0F) 230#define qlcnic_get_sts_type(sts_data) \ 231 (((sts_data) >> 8) & 0x0F) 232#define qlcnic_get_sts_totallength(sts_data) \ 233 (((sts_data) >> 12) & 0xFFFF) 234#define qlcnic_get_sts_refhandle(sts_data) \ 235 (((sts_data) >> 28) & 0xFFFF) 236#define qlcnic_get_sts_prot(sts_data) \ 237 (((sts_data) >> 44) & 0x0F) 238#define qlcnic_get_sts_pkt_offset(sts_data) \ 239 (((sts_data) >> 48) & 0x1F) 240#define qlcnic_get_sts_desc_cnt(sts_data) \ 241 (((sts_data) >> 53) & 0x7) 242#define qlcnic_get_sts_opcode(sts_data) \ 243 (((sts_data) >> 58) & 0x03F) 244 245#define qlcnic_get_lro_sts_refhandle(sts_data) \ 246 ((sts_data) & 0x0FFFF) 247#define qlcnic_get_lro_sts_length(sts_data) \ 248 (((sts_data) >> 16) & 0x0FFFF) 249#define qlcnic_get_lro_sts_l2_hdr_offset(sts_data) \ 250 (((sts_data) >> 32) & 0x0FF) 251#define qlcnic_get_lro_sts_l4_hdr_offset(sts_data) \ 252 (((sts_data) >> 40) & 0x0FF) 253#define qlcnic_get_lro_sts_timestamp(sts_data) \ 254 (((sts_data) >> 48) & 0x1) 255#define qlcnic_get_lro_sts_type(sts_data) \ 256 (((sts_data) >> 49) & 0x7) 257#define qlcnic_get_lro_sts_push_flag(sts_data) \ 258 (((sts_data) >> 52) & 0x1) 259#define qlcnic_get_lro_sts_seq_number(sts_data) \ 260 ((sts_data) & 0x0FFFFFFFF) 261 262 263struct status_desc { 264 __le64 status_desc_data[2]; 265} __attribute__ ((aligned(16))); 266 267/* UNIFIED ROMIMAGE */ 268#define QLCNIC_UNI_FW_MIN_SIZE 0xc8000 269#define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0 270#define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6 271#define QLCNIC_UNI_DIR_SECT_FW 0x7 272 273/*Offsets */ 274#define QLCNIC_UNI_CHIP_REV_OFF 10 275#define QLCNIC_UNI_FLAGS_OFF 11 276#define QLCNIC_UNI_BIOS_VERSION_OFF 12 277#define QLCNIC_UNI_BOOTLD_IDX_OFF 27 278#define QLCNIC_UNI_FIRMWARE_IDX_OFF 29 279 280struct uni_table_desc{ 281 u32 findex; 282 u32 num_entries; 283 u32 entry_size; 284 u32 reserved[5]; 285}; 286 287struct uni_data_desc{ 288 u32 findex; 289 u32 size; 290 u32 reserved[5]; 291}; 292 293/* Flash Defines and Structures */ 294#define QLCNIC_FLT_LOCATION 0x3F1000 295#define QLCNIC_B0_FW_IMAGE_REGION 0x74 296#define QLCNIC_C0_FW_IMAGE_REGION 0x97 297#define QLCNIC_BOOTLD_REGION 0X72 298struct qlcnic_flt_header { 299 u16 version; 300 u16 len; 301 u16 checksum; 302 u16 reserved; 303}; 304 305struct qlcnic_flt_entry { 306 u8 region; 307 u8 reserved0; 308 u8 attrib; 309 u8 reserved1; 310 u32 size; 311 u32 start_addr; 312 u32 end_addr; 313}; 314 315/* Magic number to let user know flash is programmed */ 316#define QLCNIC_BDINFO_MAGIC 0x12345678 317 318#define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021 319#define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022 320#define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023 321#define QLCNIC_BRDTYPE_P3P_4_GB 0x0024 322#define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025 323#define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026 324#define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027 325#define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028 326#define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029 327#define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a 328#define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b 329#define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031 330#define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032 331#define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080 332 333#define QLCNIC_MSIX_TABLE_OFFSET 0x44 334 335/* Flash memory map */ 336#define QLCNIC_BRDCFG_START 0x4000 /* board config */ 337#define QLCNIC_BOOTLD_START 0x10000 /* bootld */ 338#define QLCNIC_IMAGE_START 0x43000 /* compressed image */ 339#define QLCNIC_USER_START 0x3E8000 /* Firmare info */ 340 341#define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408) 342#define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c) 343#define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c) 344#define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c) 345 346#define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8) 347#define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128) 348 349#define QLCNIC_FW_MIN_SIZE (0x3fffff) 350#define QLCNIC_UNIFIED_ROMIMAGE 0 351#define QLCNIC_FLASH_ROMIMAGE 1 352#define QLCNIC_UNKNOWN_ROMIMAGE 0xff 353 354#define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin" 355#define QLCNIC_FLASH_ROMIMAGE_NAME "flash" 356 357extern char qlcnic_driver_name[]; 358 359/* Number of status descriptors to handle per interrupt */ 360#define MAX_STATUS_HANDLE (64) 361 362/* 363 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This 364 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}. 365 */ 366struct qlcnic_skb_frag { 367 u64 dma; 368 u64 length; 369}; 370 371/* Following defines are for the state of the buffers */ 372#define QLCNIC_BUFFER_FREE 0 373#define QLCNIC_BUFFER_BUSY 1 374 375/* 376 * There will be one qlcnic_buffer per skb packet. These will be 377 * used to save the dma info for pci_unmap_page() 378 */ 379struct qlcnic_cmd_buffer { 380 struct sk_buff *skb; 381 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1]; 382 u32 frag_count; 383}; 384 385/* In rx_buffer, we do not need multiple fragments as is a single buffer */ 386struct qlcnic_rx_buffer { 387 u16 ref_handle; 388 struct sk_buff *skb; 389 struct list_head list; 390 u64 dma; 391}; 392 393/* Board types */ 394#define QLCNIC_GBE 0x01 395#define QLCNIC_XGBE 0x02 396 397/* 398 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is 399 * adjusted based on configured MTU. 400 */ 401#define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3 402#define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256 403 404#define QLCNIC_INTR_DEFAULT 0x04 405#define QLCNIC_CONFIG_INTR_COALESCE 3 406 407struct qlcnic_nic_intr_coalesce { 408 u8 type; 409 u8 sts_ring_mask; 410 u16 rx_packets; 411 u16 rx_time_us; 412 u16 flag; 413 u32 timer_out; 414}; 415 416struct qlcnic_dump_template_hdr { 417 __le32 type; 418 __le32 offset; 419 __le32 size; 420 __le32 cap_mask; 421 __le32 num_entries; 422 __le32 version; 423 __le32 timestamp; 424 __le32 checksum; 425 __le32 drv_cap_mask; 426 __le32 sys_info[3]; 427 __le32 saved_state[16]; 428 __le32 cap_sizes[8]; 429 __le32 rsvd[0]; 430}; 431 432struct qlcnic_fw_dump { 433 u8 clr; /* flag to indicate if dump is cleared */ 434 u8 enable; /* enable/disable dump */ 435 u32 size; /* total size of the dump */ 436 void *data; /* dump data area */ 437 struct qlcnic_dump_template_hdr *tmpl_hdr; 438}; 439 440/* 441 * One hardware_context{} per adapter 442 * contains interrupt info as well shared hardware info. 443 */ 444struct qlcnic_hardware_context { 445 void __iomem *pci_base0; 446 void __iomem *ocm_win_crb; 447 448 unsigned long pci_len0; 449 450 rwlock_t crb_lock; 451 struct mutex mem_lock; 452 453 u8 revision_id; 454 u8 pci_func; 455 u8 linkup; 456 u8 loopback_state; 457 u16 port_type; 458 u16 board_type; 459 460 u8 beacon_state; 461 462 struct qlcnic_nic_intr_coalesce coal; 463 struct qlcnic_fw_dump fw_dump; 464}; 465 466struct qlcnic_adapter_stats { 467 u64 xmitcalled; 468 u64 xmitfinished; 469 u64 rxdropped; 470 u64 txdropped; 471 u64 csummed; 472 u64 rx_pkts; 473 u64 lro_pkts; 474 u64 rxbytes; 475 u64 txbytes; 476 u64 lrobytes; 477 u64 lso_frames; 478 u64 xmit_on; 479 u64 xmit_off; 480 u64 skb_alloc_failure; 481 u64 null_rxbuf; 482 u64 rx_dma_map_error; 483 u64 tx_dma_map_error; 484}; 485 486/* 487 * Rcv Descriptor Context. One such per Rcv Descriptor. There may 488 * be one Rcv Descriptor for normal packets, one for jumbo and may be others. 489 */ 490struct qlcnic_host_rds_ring { 491 void __iomem *crb_rcv_producer; 492 struct rcv_desc *desc_head; 493 struct qlcnic_rx_buffer *rx_buf_arr; 494 u32 num_desc; 495 u32 producer; 496 u32 dma_size; 497 u32 skb_size; 498 u32 flags; 499 struct list_head free_list; 500 spinlock_t lock; 501 dma_addr_t phys_addr; 502} ____cacheline_internodealigned_in_smp; 503 504struct qlcnic_host_sds_ring { 505 u32 consumer; 506 u32 num_desc; 507 void __iomem *crb_sts_consumer; 508 509 struct status_desc *desc_head; 510 struct qlcnic_adapter *adapter; 511 struct napi_struct napi; 512 struct list_head free_list[NUM_RCV_DESC_RINGS]; 513 514 void __iomem *crb_intr_mask; 515 int irq; 516 517 dma_addr_t phys_addr; 518 char name[IFNAMSIZ+4]; 519} ____cacheline_internodealigned_in_smp; 520 521struct qlcnic_host_tx_ring { 522 u32 producer; 523 u32 sw_consumer; 524 u32 num_desc; 525 void __iomem *crb_cmd_producer; 526 struct cmd_desc_type0 *desc_head; 527 struct qlcnic_cmd_buffer *cmd_buf_arr; 528 __le32 *hw_consumer; 529 530 dma_addr_t phys_addr; 531 dma_addr_t hw_cons_phys_addr; 532 struct netdev_queue *txq; 533} ____cacheline_internodealigned_in_smp; 534 535/* 536 * Receive context. There is one such structure per instance of the 537 * receive processing. Any state information that is relevant to 538 * the receive, and is must be in this structure. The global data may be 539 * present elsewhere. 540 */ 541struct qlcnic_recv_context { 542 struct qlcnic_host_rds_ring *rds_rings; 543 struct qlcnic_host_sds_ring *sds_rings; 544 u32 state; 545 u16 context_id; 546 u16 virt_port; 547 548}; 549 550/* HW context creation */ 551 552#define QLCNIC_OS_CRB_RETRY_COUNT 4000 553#define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \ 554 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16)) 555 556#define QLCNIC_CDRP_CMD_BIT 0x80000000 557 558/* 559 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared 560 * in the crb QLCNIC_CDRP_CRB_OFFSET. 561 */ 562#define QLCNIC_CDRP_FORM_RSP(rsp) (rsp) 563#define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0) 564 565#define QLCNIC_CDRP_RSP_OK 0x00000001 566#define QLCNIC_CDRP_RSP_FAIL 0x00000002 567#define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003 568 569/* 570 * All commands must have the QLCNIC_CDRP_CMD_BIT set in 571 * the crb QLCNIC_CDRP_CRB_OFFSET. 572 */ 573#define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd)) 574#define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0) 575 576#define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001 577#define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002 578#define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003 579#define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004 580#define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005 581#define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006 582#define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007 583#define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008 584#define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009 585#define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a 586#define QLCNIC_CDRP_CMD_INTRPT_TEST 0x00000011 587#define QLCNIC_CDRP_CMD_SET_MTU 0x00000012 588#define QLCNIC_CDRP_CMD_READ_PHY 0x00000013 589#define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014 590#define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015 591#define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016 592#define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017 593#define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018 594#define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019 595#define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f 596 597#define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020 598#define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021 599#define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022 600#define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024 601#define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025 602#define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026 603#define QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027 604#define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028 605#define QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029 606#define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS 0x0000002a 607#define QLCNIC_CDRP_CMD_CONFIG_PORT 0x0000002E 608#define QLCNIC_CDRP_CMD_TEMP_SIZE 0x0000002f 609#define QLCNIC_CDRP_CMD_GET_TEMP_HDR 0x00000030 610 611#define QLCNIC_RCODE_SUCCESS 0 612#define QLCNIC_RCODE_NOT_SUPPORTED 9 613#define QLCNIC_RCODE_TIMEOUT 17 614#define QLCNIC_DESTROY_CTX_RESET 0 615 616/* 617 * Capabilities Announced 618 */ 619#define QLCNIC_CAP0_LEGACY_CONTEXT (1) 620#define QLCNIC_CAP0_LEGACY_MN (1 << 2) 621#define QLCNIC_CAP0_LSO (1 << 6) 622#define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7) 623#define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8) 624#define QLCNIC_CAP0_VALIDOFF (1 << 11) 625 626/* 627 * Context state 628 */ 629#define QLCNIC_HOST_CTX_STATE_FREED 0 630#define QLCNIC_HOST_CTX_STATE_ACTIVE 2 631 632/* 633 * Rx context 634 */ 635 636struct qlcnic_hostrq_sds_ring { 637 __le64 host_phys_addr; /* Ring base addr */ 638 __le32 ring_size; /* Ring entries */ 639 __le16 msi_index; 640 __le16 rsvd; /* Padding */ 641} __packed; 642 643struct qlcnic_hostrq_rds_ring { 644 __le64 host_phys_addr; /* Ring base addr */ 645 __le64 buff_size; /* Packet buffer size */ 646 __le32 ring_size; /* Ring entries */ 647 __le32 ring_kind; /* Class of ring */ 648} __packed; 649 650struct qlcnic_hostrq_rx_ctx { 651 __le64 host_rsp_dma_addr; /* Response dma'd here */ 652 __le32 capabilities[4]; /* Flag bit vector */ 653 __le32 host_int_crb_mode; /* Interrupt crb usage */ 654 __le32 host_rds_crb_mode; /* RDS crb usage */ 655 /* These ring offsets are relative to data[0] below */ 656 __le32 rds_ring_offset; /* Offset to RDS config */ 657 __le32 sds_ring_offset; /* Offset to SDS config */ 658 __le16 num_rds_rings; /* Count of RDS rings */ 659 __le16 num_sds_rings; /* Count of SDS rings */ 660 __le16 valid_field_offset; 661 u8 txrx_sds_binding; 662 u8 msix_handler; 663 u8 reserved[128]; /* reserve space for future expansion*/ 664 /* MUST BE 64-bit aligned. 665 The following is packed: 666 - N hostrq_rds_rings 667 - N hostrq_sds_rings */ 668 char data[0]; 669} __packed; 670 671struct qlcnic_cardrsp_rds_ring{ 672 __le32 host_producer_crb; /* Crb to use */ 673 __le32 rsvd1; /* Padding */ 674} __packed; 675 676struct qlcnic_cardrsp_sds_ring { 677 __le32 host_consumer_crb; /* Crb to use */ 678 __le32 interrupt_crb; /* Crb to use */ 679} __packed; 680 681struct qlcnic_cardrsp_rx_ctx { 682 /* These ring offsets are relative to data[0] below */ 683 __le32 rds_ring_offset; /* Offset to RDS config */ 684 __le32 sds_ring_offset; /* Offset to SDS config */ 685 __le32 host_ctx_state; /* Starting State */ 686 __le32 num_fn_per_port; /* How many PCI fn share the port */ 687 __le16 num_rds_rings; /* Count of RDS rings */ 688 __le16 num_sds_rings; /* Count of SDS rings */ 689 __le16 context_id; /* Handle for context */ 690 u8 phys_port; /* Physical id of port */ 691 u8 virt_port; /* Virtual/Logical id of port */ 692 u8 reserved[128]; /* save space for future expansion */ 693 /* MUST BE 64-bit aligned. 694 The following is packed: 695 - N cardrsp_rds_rings 696 - N cardrs_sds_rings */ 697 char data[0]; 698} __packed; 699 700#define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \ 701 (sizeof(HOSTRQ_RX) + \ 702 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \ 703 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring))) 704 705#define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \ 706 (sizeof(CARDRSP_RX) + \ 707 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \ 708 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring))) 709 710/* 711 * Tx context 712 */ 713 714struct qlcnic_hostrq_cds_ring { 715 __le64 host_phys_addr; /* Ring base addr */ 716 __le32 ring_size; /* Ring entries */ 717 __le32 rsvd; /* Padding */ 718} __packed; 719 720struct qlcnic_hostrq_tx_ctx { 721 __le64 host_rsp_dma_addr; /* Response dma'd here */ 722 __le64 cmd_cons_dma_addr; /* */ 723 __le64 dummy_dma_addr; /* */ 724 __le32 capabilities[4]; /* Flag bit vector */ 725 __le32 host_int_crb_mode; /* Interrupt crb usage */ 726 __le32 rsvd1; /* Padding */ 727 __le16 rsvd2; /* Padding */ 728 __le16 interrupt_ctl; 729 __le16 msi_index; 730 __le16 rsvd3; /* Padding */ 731 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */ 732 u8 reserved[128]; /* future expansion */ 733} __packed; 734 735struct qlcnic_cardrsp_cds_ring { 736 __le32 host_producer_crb; /* Crb to use */ 737 __le32 interrupt_crb; /* Crb to use */ 738} __packed; 739 740struct qlcnic_cardrsp_tx_ctx { 741 __le32 host_ctx_state; /* Starting state */ 742 __le16 context_id; /* Handle for context */ 743 u8 phys_port; /* Physical id of port */ 744 u8 virt_port; /* Virtual/Logical id of port */ 745 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */ 746 u8 reserved[128]; /* future expansion */ 747} __packed; 748 749#define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX)) 750#define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX)) 751 752/* CRB */ 753 754#define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0 755#define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1 756#define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2 757#define QLCNIC_HOST_RDS_CRB_MODE_MAX 3 758 759#define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0 760#define QLCNIC_HOST_INT_CRB_MODE_SHARED 1 761#define QLCNIC_HOST_INT_CRB_MODE_NORX 2 762#define QLCNIC_HOST_INT_CRB_MODE_NOTX 3 763#define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4 764 765 766/* MAC */ 767 768#define MC_COUNT_P3P 38 769 770#define QLCNIC_MAC_NOOP 0 771#define QLCNIC_MAC_ADD 1 772#define QLCNIC_MAC_DEL 2 773#define QLCNIC_MAC_VLAN_ADD 3 774#define QLCNIC_MAC_VLAN_DEL 4 775 776struct qlcnic_mac_list_s { 777 struct list_head list; 778 uint8_t mac_addr[ETH_ALEN+2]; 779}; 780 781#define QLCNIC_HOST_REQUEST 0x13 782#define QLCNIC_REQUEST 0x14 783 784#define QLCNIC_MAC_EVENT 0x1 785 786#define QLCNIC_IP_UP 2 787#define QLCNIC_IP_DOWN 3 788 789#define QLCNIC_ILB_MODE 0x1 790#define QLCNIC_ELB_MODE 0x2 791 792#define QLCNIC_LINKEVENT 0x1 793#define QLCNIC_LB_RESPONSE 0x2 794#define QLCNIC_IS_LB_CONFIGURED(VAL) \ 795 (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE)) 796 797/* 798 * Driver --> Firmware 799 */ 800#define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1 801#define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3 802#define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4 803#define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7 804#define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc 805#define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12 806 807#define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15 808#define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17 809#define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18 810#define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13 811 812/* 813 * Firmware --> Driver 814 */ 815 816#define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f 817#define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141 818 819#define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ 820#define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ 821#define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ 822 823#define QLCNIC_LRO_REQUEST_CLEANUP 4 824 825/* Capabilites received */ 826#define QLCNIC_FW_CAPABILITY_TSO BIT_1 827#define QLCNIC_FW_CAPABILITY_BDG BIT_8 828#define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9 829#define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10 830#define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27 831 832/* module types */ 833#define LINKEVENT_MODULE_NOT_PRESENT 1 834#define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2 835#define LINKEVENT_MODULE_OPTICAL_SRLR 3 836#define LINKEVENT_MODULE_OPTICAL_LRM 4 837#define LINKEVENT_MODULE_OPTICAL_SFP_1G 5 838#define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6 839#define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7 840#define LINKEVENT_MODULE_TWINAX 8 841 842#define LINKSPEED_10GBPS 10000 843#define LINKSPEED_1GBPS 1000 844#define LINKSPEED_100MBPS 100 845#define LINKSPEED_10MBPS 10 846 847#define LINKSPEED_ENCODED_10MBPS 0 848#define LINKSPEED_ENCODED_100MBPS 1 849#define LINKSPEED_ENCODED_1GBPS 2 850 851#define LINKEVENT_AUTONEG_DISABLED 0 852#define LINKEVENT_AUTONEG_ENABLED 1 853 854#define LINKEVENT_HALF_DUPLEX 0 855#define LINKEVENT_FULL_DUPLEX 1 856 857#define LINKEVENT_LINKSPEED_MBPS 0 858#define LINKEVENT_LINKSPEED_ENCODED 1 859 860/* firmware response header: 861 * 63:58 - message type 862 * 57:56 - owner 863 * 55:53 - desc count 864 * 52:48 - reserved 865 * 47:40 - completion id 866 * 39:32 - opcode 867 * 31:16 - error code 868 * 15:00 - reserved 869 */ 870#define qlcnic_get_nic_msg_opcode(msg_hdr) \ 871 ((msg_hdr >> 32) & 0xFF) 872 873struct qlcnic_fw_msg { 874 union { 875 struct { 876 u64 hdr; 877 u64 body[7]; 878 }; 879 u64 words[8]; 880 }; 881}; 882 883struct qlcnic_nic_req { 884 __le64 qhdr; 885 __le64 req_hdr; 886 __le64 words[6]; 887} __packed; 888 889struct qlcnic_mac_req { 890 u8 op; 891 u8 tag; 892 u8 mac_addr[6]; 893}; 894 895struct qlcnic_vlan_req { 896 __le16 vlan_id; 897 __le16 rsvd[3]; 898} __packed; 899 900struct qlcnic_ipaddr { 901 __be32 ipv4; 902 __be32 ipv6[4]; 903}; 904 905#define QLCNIC_MSI_ENABLED 0x02 906#define QLCNIC_MSIX_ENABLED 0x04 907#define QLCNIC_LRO_ENABLED 0x08 908#define QLCNIC_LRO_DISABLED 0x00 909#define QLCNIC_BRIDGE_ENABLED 0X10 910#define QLCNIC_DIAG_ENABLED 0x20 911#define QLCNIC_ESWITCH_ENABLED 0x40 912#define QLCNIC_ADAPTER_INITIALIZED 0x80 913#define QLCNIC_TAGGING_ENABLED 0x100 914#define QLCNIC_MACSPOOF 0x200 915#define QLCNIC_MAC_OVERRIDE_DISABLED 0x400 916#define QLCNIC_PROMISC_DISABLED 0x800 917#define QLCNIC_NEED_FLR 0x1000 918#define QLCNIC_FW_RESET_OWNER 0x2000 919#define QLCNIC_FW_HANG 0x4000 920#define QLCNIC_IS_MSI_FAMILY(adapter) \ 921 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED)) 922 923#define QLCNIC_DEF_NUM_STS_DESC_RINGS 4 924#define QLCNIC_MSIX_TBL_SPACE 8192 925#define QLCNIC_PCI_REG_MSIX_TBL 0x44 926#define QLCNIC_MSIX_TBL_PGSIZE 4096 927 928#define QLCNIC_NETDEV_WEIGHT 128 929#define QLCNIC_ADAPTER_UP_MAGIC 777 930 931#define __QLCNIC_FW_ATTACHED 0 932#define __QLCNIC_DEV_UP 1 933#define __QLCNIC_RESETTING 2 934#define __QLCNIC_START_FW 4 935#define __QLCNIC_AER 5 936#define __QLCNIC_DIAG_RES_ALLOC 6 937#define __QLCNIC_LED_ENABLE 7 938 939#define QLCNIC_INTERRUPT_TEST 1 940#define QLCNIC_LOOPBACK_TEST 2 941#define QLCNIC_LED_TEST 3 942 943#define QLCNIC_FILTER_AGE 80 944#define QLCNIC_READD_AGE 20 945#define QLCNIC_LB_MAX_FILTERS 64 946 947/* QLCNIC Driver Error Code */ 948#define QLCNIC_FW_NOT_RESPOND 51 949#define QLCNIC_TEST_IN_PROGRESS 52 950#define QLCNIC_UNDEFINED_ERROR 53 951#define QLCNIC_LB_CABLE_NOT_CONN 54 952 953struct qlcnic_filter { 954 struct hlist_node fnode; 955 u8 faddr[ETH_ALEN]; 956 __le16 vlan_id; 957 unsigned long ftime; 958}; 959 960struct qlcnic_filter_hash { 961 struct hlist_head *fhead; 962 u8 fnum; 963 u8 fmax; 964}; 965 966struct qlcnic_adapter { 967 struct qlcnic_hardware_context *ahw; 968 struct qlcnic_recv_context *recv_ctx; 969 struct qlcnic_host_tx_ring *tx_ring; 970 struct net_device *netdev; 971 struct pci_dev *pdev; 972 973 unsigned long state; 974 u32 flags; 975 976 u16 num_txd; 977 u16 num_rxd; 978 u16 num_jumbo_rxd; 979 u16 max_rxd; 980 u16 max_jumbo_rxd; 981 982 u8 max_rds_rings; 983 u8 max_sds_rings; 984 u8 msix_supported; 985 u8 portnum; 986 u8 physical_port; 987 u8 reset_context; 988 989 u8 mc_enabled; 990 u8 max_mc_count; 991 u8 fw_wait_cnt; 992 u8 fw_fail_cnt; 993 u8 tx_timeo_cnt; 994 u8 need_fw_reset; 995 996 u8 has_link_events; 997 u8 fw_type; 998 u16 tx_context_id; 999 u16 is_up; 1000 1001 u16 link_speed; 1002 u16 link_duplex; 1003 u16 link_autoneg; 1004 u16 module_type; 1005 1006 u16 op_mode; 1007 u16 switch_mode; 1008 u16 max_tx_ques; 1009 u16 max_rx_ques; 1010 u16 max_mtu; 1011 u16 pvid; 1012 1013 u32 fw_hal_version; 1014 u32 capabilities; 1015 u32 irq; 1016 u32 temp; 1017 1018 u32 int_vec_bit; 1019 u32 heartbeat; 1020 1021 u8 max_mac_filters; 1022 u8 dev_state; 1023 u8 diag_test; 1024 char diag_cnt; 1025 u8 reset_ack_timeo; 1026 u8 dev_init_timeo; 1027 u16 msg_enable; 1028 1029 u8 mac_addr[ETH_ALEN]; 1030 1031 u64 dev_rst_time; 1032 u8 mac_learn; 1033 unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)]; 1034 1035 struct qlcnic_npar_info *npars; 1036 struct qlcnic_eswitch *eswitch; 1037 struct qlcnic_nic_template *nic_ops; 1038 1039 struct qlcnic_adapter_stats stats; 1040 struct list_head mac_list; 1041 1042 void __iomem *tgt_mask_reg; 1043 void __iomem *tgt_status_reg; 1044 void __iomem *crb_int_state_reg; 1045 void __iomem *isr_int_vec; 1046 1047 struct msix_entry *msix_entries; 1048 1049 struct delayed_work fw_work; 1050 1051 1052 struct qlcnic_filter_hash fhash; 1053 1054 spinlock_t tx_clean_lock; 1055 spinlock_t mac_learn_lock; 1056 __le32 file_prd_off; /*File fw product offset*/ 1057 u32 fw_version; 1058 const struct firmware *fw; 1059}; 1060 1061struct qlcnic_info { 1062 __le16 pci_func; 1063 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */ 1064 __le16 phys_port; 1065 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */ 1066 1067 __le32 capabilities; 1068 u8 max_mac_filters; 1069 u8 reserved1; 1070 __le16 max_mtu; 1071 1072 __le16 max_tx_ques; 1073 __le16 max_rx_ques; 1074 __le16 min_tx_bw; 1075 __le16 max_tx_bw; 1076 u8 reserved2[104]; 1077} __packed; 1078 1079struct qlcnic_pci_info { 1080 __le16 id; /* pci function id */ 1081 __le16 active; /* 1 = Enabled */ 1082 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */ 1083 __le16 default_port; /* default port number */ 1084 1085 __le16 tx_min_bw; /* Multiple of 100mbpc */ 1086 __le16 tx_max_bw; 1087 __le16 reserved1[2]; 1088 1089 u8 mac[ETH_ALEN]; 1090 u8 reserved2[106]; 1091} __packed; 1092 1093struct qlcnic_npar_info { 1094 u16 pvid; 1095 u16 min_bw; 1096 u16 max_bw; 1097 u8 phy_port; 1098 u8 type; 1099 u8 active; 1100 u8 enable_pm; 1101 u8 dest_npar; 1102 u8 discard_tagged; 1103 u8 mac_override; 1104 u8 mac_anti_spoof; 1105 u8 promisc_mode; 1106 u8 offload_flags; 1107}; 1108 1109struct qlcnic_eswitch { 1110 u8 port; 1111 u8 active_vports; 1112 u8 active_vlans; 1113 u8 active_ucast_filters; 1114 u8 max_ucast_filters; 1115 u8 max_active_vlans; 1116 1117 u32 flags; 1118#define QLCNIC_SWITCH_ENABLE BIT_1 1119#define QLCNIC_SWITCH_VLAN_FILTERING BIT_2 1120#define QLCNIC_SWITCH_PROMISC_MODE BIT_3 1121#define QLCNIC_SWITCH_PORT_MIRRORING BIT_4 1122}; 1123 1124 1125/* Return codes for Error handling */ 1126#define QL_STATUS_INVALID_PARAM -1 1127 1128#define MAX_BW 100 /* % of link speed */ 1129#define MAX_VLAN_ID 4095 1130#define MIN_VLAN_ID 2 1131#define DEFAULT_MAC_LEARN 1 1132 1133#define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID) 1134#define IS_VALID_BW(bw) (bw <= MAX_BW) 1135 1136struct qlcnic_pci_func_cfg { 1137 u16 func_type; 1138 u16 min_bw; 1139 u16 max_bw; 1140 u16 port_num; 1141 u8 pci_func; 1142 u8 func_state; 1143 u8 def_mac_addr[6]; 1144}; 1145 1146struct qlcnic_npar_func_cfg { 1147 u32 fw_capab; 1148 u16 port_num; 1149 u16 min_bw; 1150 u16 max_bw; 1151 u16 max_tx_queues; 1152 u16 max_rx_queues; 1153 u8 pci_func; 1154 u8 op_mode; 1155}; 1156 1157struct qlcnic_pm_func_cfg { 1158 u8 pci_func; 1159 u8 action; 1160 u8 dest_npar; 1161 u8 reserved[5]; 1162}; 1163 1164struct qlcnic_esw_func_cfg { 1165 u16 vlan_id; 1166 u8 op_mode; 1167 u8 op_type; 1168 u8 pci_func; 1169 u8 host_vlan_tag; 1170 u8 promisc_mode; 1171 u8 discard_tagged; 1172 u8 mac_override; 1173 u8 mac_anti_spoof; 1174 u8 offload_flags; 1175 u8 reserved[5]; 1176}; 1177 1178#define QLCNIC_STATS_VERSION 1 1179#define QLCNIC_STATS_PORT 1 1180#define QLCNIC_STATS_ESWITCH 2 1181#define QLCNIC_QUERY_RX_COUNTER 0 1182#define QLCNIC_QUERY_TX_COUNTER 1 1183#define QLCNIC_ESW_STATS_NOT_AVAIL 0xffffffffffffffffULL 1184 1185#define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\ 1186do { \ 1187 if (((VAL1) == QLCNIC_ESW_STATS_NOT_AVAIL) && \ 1188 ((VAL2) != QLCNIC_ESW_STATS_NOT_AVAIL)) \ 1189 (VAL1) = (VAL2); \ 1190 else if (((VAL1) != QLCNIC_ESW_STATS_NOT_AVAIL) && \ 1191 ((VAL2) != QLCNIC_ESW_STATS_NOT_AVAIL)) \ 1192 (VAL1) += (VAL2); \ 1193} while (0) 1194 1195struct __qlcnic_esw_statistics { 1196 __le16 context_id; 1197 __le16 version; 1198 __le16 size; 1199 __le16 unused; 1200 __le64 unicast_frames; 1201 __le64 multicast_frames; 1202 __le64 broadcast_frames; 1203 __le64 dropped_frames; 1204 __le64 errors; 1205 __le64 local_frames; 1206 __le64 numbytes; 1207 __le64 rsvd[3]; 1208} __packed; 1209 1210struct qlcnic_esw_statistics { 1211 struct __qlcnic_esw_statistics rx; 1212 struct __qlcnic_esw_statistics tx; 1213}; 1214 1215struct qlcnic_common_entry_hdr { 1216 __le32 type; 1217 __le32 offset; 1218 __le32 cap_size; 1219 u8 mask; 1220 u8 rsvd[2]; 1221 u8 flags; 1222} __packed; 1223 1224struct __crb { 1225 __le32 addr; 1226 u8 stride; 1227 u8 rsvd1[3]; 1228 __le32 data_size; 1229 __le32 no_ops; 1230 __le32 rsvd2[4]; 1231} __packed; 1232 1233struct __ctrl { 1234 __le32 addr; 1235 u8 stride; 1236 u8 index_a; 1237 __le16 timeout; 1238 __le32 data_size; 1239 __le32 no_ops; 1240 u8 opcode; 1241 u8 index_v; 1242 u8 shl_val; 1243 u8 shr_val; 1244 __le32 val1; 1245 __le32 val2; 1246 __le32 val3; 1247} __packed; 1248 1249struct __cache { 1250 __le32 addr; 1251 __le16 stride; 1252 __le16 init_tag_val; 1253 __le32 size; 1254 __le32 no_ops; 1255 __le32 ctrl_addr; 1256 __le32 ctrl_val; 1257 __le32 read_addr; 1258 u8 read_addr_stride; 1259 u8 read_addr_num; 1260 u8 rsvd1[2]; 1261} __packed; 1262 1263struct __ocm { 1264 u8 rsvd[8]; 1265 __le32 size; 1266 __le32 no_ops; 1267 u8 rsvd1[8]; 1268 __le32 read_addr; 1269 __le32 read_addr_stride; 1270} __packed; 1271 1272struct __mem { 1273 u8 rsvd[24]; 1274 __le32 addr; 1275 __le32 size; 1276} __packed; 1277 1278struct __mux { 1279 __le32 addr; 1280 u8 rsvd[4]; 1281 __le32 size; 1282 __le32 no_ops; 1283 __le32 val; 1284 __le32 val_stride; 1285 __le32 read_addr; 1286 u8 rsvd2[4]; 1287} __packed; 1288 1289struct __queue { 1290 __le32 sel_addr; 1291 __le16 stride; 1292 u8 rsvd[2]; 1293 __le32 size; 1294 __le32 no_ops; 1295 u8 rsvd2[8]; 1296 __le32 read_addr; 1297 u8 read_addr_stride; 1298 u8 read_addr_cnt; 1299 u8 rsvd3[2]; 1300} __packed; 1301 1302struct qlcnic_dump_entry { 1303 struct qlcnic_common_entry_hdr hdr; 1304 union { 1305 struct __crb crb; 1306 struct __cache cache; 1307 struct __ocm ocm; 1308 struct __mem mem; 1309 struct __mux mux; 1310 struct __queue que; 1311 struct __ctrl ctrl; 1312 } region; 1313} __packed; 1314 1315enum op_codes { 1316 QLCNIC_DUMP_NOP = 0, 1317 QLCNIC_DUMP_READ_CRB = 1, 1318 QLCNIC_DUMP_READ_MUX = 2, 1319 QLCNIC_DUMP_QUEUE = 3, 1320 QLCNIC_DUMP_BRD_CONFIG = 4, 1321 QLCNIC_DUMP_READ_OCM = 6, 1322 QLCNIC_DUMP_PEG_REG = 7, 1323 QLCNIC_DUMP_L1_DTAG = 8, 1324 QLCNIC_DUMP_L1_ITAG = 9, 1325 QLCNIC_DUMP_L1_DATA = 11, 1326 QLCNIC_DUMP_L1_INST = 12, 1327 QLCNIC_DUMP_L2_DTAG = 21, 1328 QLCNIC_DUMP_L2_ITAG = 22, 1329 QLCNIC_DUMP_L2_DATA = 23, 1330 QLCNIC_DUMP_L2_INST = 24, 1331 QLCNIC_DUMP_READ_ROM = 71, 1332 QLCNIC_DUMP_READ_MEM = 72, 1333 QLCNIC_DUMP_READ_CTRL = 98, 1334 QLCNIC_DUMP_TLHDR = 99, 1335 QLCNIC_DUMP_RDEND = 255 1336}; 1337 1338#define QLCNIC_DUMP_WCRB BIT_0 1339#define QLCNIC_DUMP_RWCRB BIT_1 1340#define QLCNIC_DUMP_ANDCRB BIT_2 1341#define QLCNIC_DUMP_ORCRB BIT_3 1342#define QLCNIC_DUMP_POLLCRB BIT_4 1343#define QLCNIC_DUMP_RD_SAVE BIT_5 1344#define QLCNIC_DUMP_WRT_SAVED BIT_6 1345#define QLCNIC_DUMP_MOD_SAVE_ST BIT_7 1346#define QLCNIC_DUMP_SKIP BIT_7 1347 1348#define QLCNIC_DUMP_MASK_MIN 3 1349#define QLCNIC_DUMP_MASK_DEF 0x1f 1350#define QLCNIC_DUMP_MASK_MAX 0xff 1351#define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed 1352#define QLCNIC_ENABLE_FW_DUMP 0xaddfeed 1353#define QLCNIC_DISABLE_FW_DUMP 0xbadfeed 1354#define QLCNIC_FORCE_FW_RESET 0xdeaddead 1355 1356struct qlcnic_dump_operations { 1357 enum op_codes opcode; 1358 u32 (*handler)(struct qlcnic_adapter *, 1359 struct qlcnic_dump_entry *, u32 *); 1360}; 1361 1362struct _cdrp_cmd { 1363 u32 cmd; 1364 u32 arg1; 1365 u32 arg2; 1366 u32 arg3; 1367}; 1368 1369struct qlcnic_cmd_args { 1370 struct _cdrp_cmd req; 1371 struct _cdrp_cmd rsp; 1372}; 1373 1374int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter); 1375int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config); 1376 1377u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off); 1378int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data); 1379int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data); 1380int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data); 1381void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *); 1382void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64); 1383 1384#define ADDR_IN_RANGE(addr, low, high) \ 1385 (((addr) < (high)) && ((addr) >= (low))) 1386 1387#define QLCRD32(adapter, off) \ 1388 (qlcnic_hw_read_wx_2M(adapter, off)) 1389#define QLCWR32(adapter, off, val) \ 1390 (qlcnic_hw_write_wx_2M(adapter, off, val)) 1391 1392int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32); 1393void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int); 1394 1395#define qlcnic_rom_lock(a) \ 1396 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID) 1397#define qlcnic_rom_unlock(a) \ 1398 qlcnic_pcie_sem_unlock((a), 2) 1399#define qlcnic_phy_lock(a) \ 1400 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID) 1401#define qlcnic_phy_unlock(a) \ 1402 qlcnic_pcie_sem_unlock((a), 3) 1403#define qlcnic_api_lock(a) \ 1404 qlcnic_pcie_sem_lock((a), 5, 0) 1405#define qlcnic_api_unlock(a) \ 1406 qlcnic_pcie_sem_unlock((a), 5) 1407#define qlcnic_sw_lock(a) \ 1408 qlcnic_pcie_sem_lock((a), 6, 0) 1409#define qlcnic_sw_unlock(a) \ 1410 qlcnic_pcie_sem_unlock((a), 6) 1411#define crb_win_lock(a) \ 1412 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID) 1413#define crb_win_unlock(a) \ 1414 qlcnic_pcie_sem_unlock((a), 7) 1415 1416#define __QLCNIC_MAX_LED_RATE 0xf 1417#define __QLCNIC_MAX_LED_STATE 0x2 1418 1419int qlcnic_get_board_info(struct qlcnic_adapter *adapter); 1420int qlcnic_wol_supported(struct qlcnic_adapter *adapter); 1421int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate); 1422void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter); 1423void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter); 1424int qlcnic_dump_fw(struct qlcnic_adapter *); 1425 1426/* Functions from qlcnic_init.c */ 1427int qlcnic_load_firmware(struct qlcnic_adapter *adapter); 1428int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter); 1429void qlcnic_request_firmware(struct qlcnic_adapter *adapter); 1430void qlcnic_release_firmware(struct qlcnic_adapter *adapter); 1431int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter); 1432int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter); 1433int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter); 1434 1435int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp); 1436int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr, 1437 u8 *bytes, size_t size); 1438int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter); 1439void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter); 1440 1441void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32); 1442 1443int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter); 1444void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter); 1445 1446int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter); 1447void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter); 1448 1449void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter); 1450void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter); 1451void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter); 1452 1453int qlcnic_check_fw_status(struct qlcnic_adapter *adapter); 1454void qlcnic_watchdog_task(struct work_struct *work); 1455void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, 1456 struct qlcnic_host_rds_ring *rds_ring); 1457int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max); 1458void qlcnic_set_multi(struct net_device *netdev); 1459void qlcnic_free_mac_list(struct qlcnic_adapter *adapter); 1460int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32); 1461int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter); 1462int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable); 1463int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd); 1464int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable); 1465void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup); 1466 1467int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu); 1468int qlcnic_change_mtu(struct net_device *netdev, int new_mtu); 1469netdev_features_t qlcnic_fix_features(struct net_device *netdev, 1470 netdev_features_t features); 1471int qlcnic_set_features(struct net_device *netdev, netdev_features_t features); 1472int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable); 1473int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable); 1474int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter); 1475void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter, 1476 struct qlcnic_host_tx_ring *tx_ring); 1477void qlcnic_fetch_mac(struct qlcnic_adapter *, u32, u32, u8, u8 *); 1478void qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring); 1479void qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter); 1480int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode); 1481 1482/* Functions from qlcnic_ethtool.c */ 1483int qlcnic_check_loopback_buff(unsigned char *data, u8 mac[]); 1484 1485/* Functions from qlcnic_main.c */ 1486int qlcnic_reset_context(struct qlcnic_adapter *); 1487void qlcnic_issue_cmd(struct qlcnic_adapter *adapter, struct qlcnic_cmd_args *); 1488void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings); 1489int qlcnic_diag_alloc_res(struct net_device *netdev, int test); 1490netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev); 1491int qlcnic_validate_max_rss(struct net_device *netdev, u8 max_hw, u8 val); 1492int qlcnic_set_max_rss(struct qlcnic_adapter *adapter, u8 data); 1493void qlcnic_dev_request_reset(struct qlcnic_adapter *); 1494void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter); 1495 1496/* Management functions */ 1497int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*); 1498int qlcnic_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8); 1499int qlcnic_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *); 1500int qlcnic_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*); 1501 1502/* eSwitch management functions */ 1503int qlcnic_config_switch_port(struct qlcnic_adapter *, 1504 struct qlcnic_esw_func_cfg *); 1505int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *, 1506 struct qlcnic_esw_func_cfg *); 1507int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8); 1508int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8, 1509 struct __qlcnic_esw_statistics *); 1510int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8, 1511 struct __qlcnic_esw_statistics *); 1512int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8); 1513extern int qlcnic_config_tso; 1514 1515/* 1516 * QLOGIC Board information 1517 */ 1518 1519#define QLCNIC_MAX_BOARD_NAME_LEN 100 1520struct qlcnic_brdinfo { 1521 unsigned short vendor; 1522 unsigned short device; 1523 unsigned short sub_vendor; 1524 unsigned short sub_device; 1525 char short_name[QLCNIC_MAX_BOARD_NAME_LEN]; 1526}; 1527 1528static const struct qlcnic_brdinfo qlcnic_boards[] = { 1529 {0x1077, 0x8020, 0x1077, 0x203, 1530 "8200 Series Single Port 10GbE Converged Network Adapter " 1531 "(TCP/IP Networking)"}, 1532 {0x1077, 0x8020, 0x1077, 0x207, 1533 "8200 Series Dual Port 10GbE Converged Network Adapter " 1534 "(TCP/IP Networking)"}, 1535 {0x1077, 0x8020, 0x1077, 0x20b, 1536 "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"}, 1537 {0x1077, 0x8020, 0x1077, 0x20c, 1538 "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"}, 1539 {0x1077, 0x8020, 0x1077, 0x20f, 1540 "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"}, 1541 {0x1077, 0x8020, 0x103c, 0x3733, 1542 "NC523SFP 10Gb 2-port Server Adapter"}, 1543 {0x1077, 0x8020, 0x103c, 0x3346, 1544 "CN1000Q Dual Port Converged Network Adapter"}, 1545 {0x1077, 0x8020, 0x1077, 0x210, 1546 "QME8242-k 10GbE Dual Port Mezzanine Card"}, 1547 {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"}, 1548}; 1549 1550#define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards) 1551 1552static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring) 1553{ 1554 if (likely(tx_ring->producer < tx_ring->sw_consumer)) 1555 return tx_ring->sw_consumer - tx_ring->producer; 1556 else 1557 return tx_ring->sw_consumer + tx_ring->num_desc - 1558 tx_ring->producer; 1559} 1560 1561extern const struct ethtool_ops qlcnic_ethtool_ops; 1562 1563struct qlcnic_nic_template { 1564 int (*config_bridged_mode) (struct qlcnic_adapter *, u32); 1565 int (*config_led) (struct qlcnic_adapter *, u32, u32); 1566 int (*start_firmware) (struct qlcnic_adapter *); 1567}; 1568 1569#define QLCDB(adapter, lvl, _fmt, _args...) do { \ 1570 if (NETIF_MSG_##lvl & adapter->msg_enable) \ 1571 printk(KERN_INFO "%s: %s: " _fmt, \ 1572 dev_name(&adapter->pdev->dev), \ 1573 __func__, ##_args); \ 1574 } while (0) 1575 1576#endif /* __QLCNIC_H_ */ 1577