Searched refs:ctrl_reg (Results 1 - 25 of 36) sorted by relevance

12

/drivers/rtc/
H A Drtc-pm8xxx.c45 * @ctrl_reg: rtc control register.
47 * @ctrl_reg_lock: spinlock protecting access to ctrl_reg.
56 u8 ctrl_reg; member in struct:pm8xxx_rtc
110 u8 value[NUM_8_BIT_RTC_REGS], reg = 0, alarm_enabled = 0, ctrl_reg; local
123 ctrl_reg = rtc_dd->ctrl_reg;
125 if (ctrl_reg & PM8xxx_RTC_ALARM_ENABLE) {
127 ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE;
128 rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base,
135 rtc_dd->ctrl_reg
234 u8 value[NUM_8_BIT_RTC_REGS], ctrl_reg; local
312 u8 ctrl_reg; local
342 u8 ctrl_reg; local
388 u8 ctrl_reg; local
[all...]
/drivers/misc/ibmasm/
H A Dlowlevel.h67 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; local
68 writel( readl(ctrl_reg) & ~mask, ctrl_reg);
73 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; local
74 writel( readl(ctrl_reg) | mask, ctrl_reg);
/drivers/watchdog/
H A Dmachzwd.c193 unsigned int ctrl_reg = 0; local
201 ctrl_reg = zf_get_control();
202 ctrl_reg |= (ENABLE_WD1|ENABLE_WD2); /* disable wd1 and wd2 */
203 ctrl_reg &= ~(ENABLE_WD1|ENABLE_WD2);
204 zf_set_control(ctrl_reg);
216 unsigned int ctrl_reg = 0; local
232 ctrl_reg = zf_get_control();
233 ctrl_reg |= (ENABLE_WD1|zf_action);
234 zf_set_control(ctrl_reg);
243 unsigned int ctrl_reg local
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/drivers/char/hw_random/
H A Dppc4xx-rng.c56 void __iomem *ctrl_reg; local
65 ctrl_reg = of_iomap(ctrl, 0);
66 if (!ctrl_reg) {
71 val = in_le32(ctrl_reg + PPC4XX_TRNG_DEV_CTRL);
78 out_le32(ctrl_reg + PPC4XX_TRNG_DEV_CTRL, val);
79 iounmap(ctrl_reg);
/drivers/pci/hotplug/
H A Dshpchp.h202 struct ctrl_reg { struct
220 BASE_OFFSET = offsetof(struct ctrl_reg, base_offset),
221 SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1),
222 SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2),
223 SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config),
224 SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config),
225 MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl),
226 PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface),
227 CMD = offsetof(struct ctrl_reg, cmd),
228 CMD_STATUS = offsetof(struct ctrl_reg, cmd_statu
[all...]
H A Dcpqphp.h122 struct ctrl_reg { /* offset */ struct
154 SLOT_RST = offsetof(struct ctrl_reg, slot_RST),
155 SLOT_ENABLE = offsetof(struct ctrl_reg, slot_enable),
156 MISC = offsetof(struct ctrl_reg, misc),
157 LED_CONTROL = offsetof(struct ctrl_reg, led_control),
158 INT_INPUT_CLEAR = offsetof(struct ctrl_reg, int_input_clear),
159 INT_MASK = offsetof(struct ctrl_reg, int_mask),
160 CTRL_RESERVED0 = offsetof(struct ctrl_reg, reserved0),
161 CTRL_RESERVED1 = offsetof(struct ctrl_reg, reserved1),
162 CTRL_RESERVED2 = offsetof(struct ctrl_reg, reserved
[all...]
/drivers/isdn/hisax/
H A Dnj_s.c103 cs->hw.njet.ctrl_reg = 0xff; /* Reset On */
104 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg);
109 cs->hw.njet.ctrl_reg = 0x40; /* Reset Off and status read clear */
111 cs->hw.njet.ctrl_reg = 0x00; /* Reset Off and status read clear */
112 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg);
197 cs->hw.njet.ctrl_reg = 0xff; /* Reset On */
198 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg);
201 cs->hw.njet.ctrl_reg = 0x00; /* Reset Off and status read clear */
202 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg);
H A Dnj_u.c86 cs->hw.njet.ctrl_reg = 0xff; /* Reset On */
87 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg);
89 cs->hw.njet.ctrl_reg = 0x40; /* Reset Off and status read clear */
91 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg);
158 cs->hw.njet.ctrl_reg = 0xff; /* Reset On */
159 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg);
162 cs->hw.njet.ctrl_reg = 0x00; /* Reset Off and status read clear */
163 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg);
H A Denternow_pci.c156 cs->hw.njet.ctrl_reg = 0x07;
157 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL);
160 cs->hw.njet.ctrl_reg = 0x30;
161 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL);
336 cs->hw.njet.ctrl_reg = 0x07; // geändert von 0xff
337 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL);
341 cs->hw.njet.ctrl_reg = 0x30; /* Reset Off and status read clear */
342 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL);
H A Delsa.c470 cs->hw.elsa.ctrl_reg |= 0x50;
471 cs->hw.elsa.ctrl_reg &= ~ELSA_ISDN_RESET; /* Reset On */
472 byteout(cs->hw.elsa.ctrl, cs->hw.elsa.ctrl_reg);
476 cs->hw.elsa.ctrl_reg |= ELSA_ISDN_RESET; /* Reset Off */
477 byteout(cs->hw.elsa.ctrl, cs->hw.elsa.ctrl_reg);
614 cs->hw.elsa.ctrl_reg |= ELSA_STAT_LED;
616 cs->hw.elsa.ctrl_reg &= ~ELSA_STAT_LED;
618 cs->hw.elsa.ctrl_reg ^= ELSA_STAT_LED;
622 cs->hw.elsa.ctrl_reg |= ELSA_LINE_LED;
624 cs->hw.elsa.ctrl_reg
[all...]
H A Ddiva.c779 cs->hw.diva.ctrl_reg = 0; /* Reset On */
780 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
782 cs->hw.diva.ctrl_reg |= DIVA_RESET; /* Reset Off */
783 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
786 cs->hw.diva.ctrl_reg |= DIVA_ISA_LED_A;
790 cs->hw.diva.ctrl_reg |= DIVA_PCI_LED_A;
792 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
809 cs->hw.diva.ctrl_reg |= (DIVA_ISA == cs->subtyp) ?
812 cs->hw.diva.ctrl_reg ^= (DIVA_ISA == cs->subtyp) ?
817 cs->hw.diva.ctrl_reg |
[all...]
/drivers/bluetooth/
H A Dbluecard_cs.c79 unsigned char ctrl_reg; member in struct:bluecard_info_t
265 info->ctrl_reg |= REG_CONTROL_RTS;
266 outb(info->ctrl_reg, iobase + REG_CONTROL);
310 info->ctrl_reg &= ~0x03;
311 info->ctrl_reg |= baud_reg;
312 outb(info->ctrl_reg, iobase + REG_CONTROL);
315 info->ctrl_reg &= ~REG_CONTROL_RTS;
316 outb(info->ctrl_reg, iobase + REG_CONTROL);
515 info->ctrl_reg &= ~REG_CONTROL_INTERRUPT;
516 outb(info->ctrl_reg, iobas
[all...]
/drivers/net/ethernet/intel/ixgb/
H A Dixgb_hw.c73 u32 ctrl_reg; local
75 ctrl_reg = IXGB_CTRL0_RST |
86 IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg);
88 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
93 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
96 ASSERT(!(ctrl_reg & IXGB_CTRL0_RST));
100 ctrl_reg = /* Enable interrupt from XFP and SerDes */
106 IXGB_WRITE_REG(hw, CTRL1, ctrl_reg);
113 return ctrl_reg;
124 u32 ctrl_reg; local
301 u32 ctrl_reg; local
639 u32 ctrl_reg; local
[all...]
/drivers/staging/comedi/drivers/
H A Dme4000.c634 info->ao_context[i].ctrl_reg =
650 info->ao_context[i].ctrl_reg =
666 info->ao_context[i].ctrl_reg =
682 info->ao_context[i].ctrl_reg =
712 info->ai_context.ctrl_reg = info->me4000_regbase + ME4000_AI_CTRL_REG;
745 info->dio_context.ctrl_reg = info->me4000_regbase + ME4000_DIO_CTRL_REG;
763 info->cnt_context.ctrl_reg = info->timer_regbase + ME4000_CNT_CTRL_REG;
1026 tmp = me4000_inl(dev, info->ai_context.ctrl_reg);
1030 me4000_outl(dev, tmp, info->ai_context.ctrl_reg);
1035 me4000_outl(dev, tmp, info->ai_context.ctrl_reg);
[all...]
H A Dme4000.h336 unsigned long ctrl_reg; member in struct:me4000_ao_context
348 unsigned long ctrl_reg; member in struct:me4000_ai_context
365 unsigned long ctrl_reg; member in struct:me4000_dio_context
373 unsigned long ctrl_reg; member in struct:me4000_cnt_context
/drivers/gpu/drm/gma500/
H A Dmdfld_dsi_pkg_sender.c232 u32 ctrl_reg; local
237 ctrl_reg = sender->mipi_hs_gen_ctrl_reg;
241 ctrl_reg = sender->mipi_lp_gen_ctrl_reg;
249 REG_WRITE(ctrl_reg, val);
258 u32 ctrl_reg; local
267 ctrl_reg = sender->mipi_hs_gen_ctrl_reg;
272 ctrl_reg = sender->mipi_lp_gen_ctrl_reg;
313 REG_WRITE(ctrl_reg, val);
/drivers/usb/otg/
H A Dab8500-usb.c119 u8 ctrl_reg; local
123 &ctrl_reg);
126 ctrl_reg |= AB8500_BIT_PHY_CTRL_HOST_EN;
128 ctrl_reg &= ~AB8500_BIT_PHY_CTRL_HOST_EN;
131 ctrl_reg |= AB8500_BIT_PHY_CTRL_DEVICE_EN;
133 ctrl_reg &= ~AB8500_BIT_PHY_CTRL_DEVICE_EN;
139 ctrl_reg);
/drivers/media/video/davinci/
H A Dvpif.h393 u32 ctrl_reg; local
395 ctrl_reg = VPIF_CH0_CTRL;
397 ctrl_reg = VPIF_CH1_CTRL;
400 vpif_clr_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT);
402 vpif_clr_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT);
407 u32 ctrl_reg; local
409 ctrl_reg = VPIF_CH0_CTRL;
411 ctrl_reg = VPIF_CH1_CTRL;
414 vpif_set_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT);
416 vpif_set_bit(ctrl_reg, VPIF_CH_HANC_EN_BI
[all...]
/drivers/mmc/host/
H A Dmvsdio.c613 u32 ctrl_reg = 0; local
635 ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN;
636 ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST;
639 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK;
640 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN;
643 ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN;
646 ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS;
658 ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN;
661 host->ctrl = ctrl_reg;
662 mvsd_write(MVSD_HOST_CTRL, ctrl_reg);
[all...]
/drivers/input/keyboard/
H A Dpmic8xxx-keypad.c96 * @ctrl_reg - control register value
110 u8 ctrl_reg; member in struct:pmic8xxx_kp
475 kp->ctrl_reg |= KEYP_CTRL_KEYP_EN;
477 rc = pmic8xxx_kp_write_u8(kp, kp->ctrl_reg, KEYP_CTRL);
488 kp->ctrl_reg &= ~KEYP_CTRL_KEYP_EN;
490 rc = pmic8xxx_kp_write_u8(kp, kp->ctrl_reg, KEYP_CTRL);
690 kp->ctrl_reg = ctrl_val;
/drivers/net/ethernet/intel/e1000/
H A De1000_ethtool.c1124 u32 ctrl_reg; local
1129 ctrl_reg = er32(CTRL);
1130 ctrl_reg |= (E1000_CTRL_ILOS | /* Invert Loss-Of-Signal */
1136 ew32(CTRL, ctrl_reg);
1191 u32 ctrl_reg = 0; local
1206 ctrl_reg = er32(CTRL);
1212 ctrl_reg = er32(CTRL);
1213 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1214 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1221 ctrl_reg |
[all...]
/drivers/net/ethernet/intel/e1000e/
H A Dethtool.c1228 u32 ctrl_reg = 0; local
1239 ctrl_reg = er32(CTRL);
1240 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1241 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1246 ew32(CTRL, ctrl_reg);
1319 ctrl_reg = er32(CTRL);
1320 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1321 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1327 ctrl_reg |= E1000_CTRL_SLU; /* Set Link Up */
1331 ctrl_reg |
[all...]
/drivers/net/ethernet/xilinx/
H A Dxilinx_emaclite.c755 u32 ctrl_reg; local
765 ctrl_reg = in_be32(lp->base_addr + XEL_MDIOCTRL_OFFSET);
770 ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
798 u32 ctrl_reg; local
812 ctrl_reg = in_be32(lp->base_addr + XEL_MDIOCTRL_OFFSET);
818 ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
/drivers/video/
H A Dsm501fb.c718 void __iomem *ctrl_reg = fbi->regs + SM501_DC_PANEL_CONTROL; local
721 control = smc501_readl(ctrl_reg);
727 smc501_writel(control, ctrl_reg);
732 smc501_writel(control, ctrl_reg);
744 smc501_writel(control, ctrl_reg);
755 smc501_writel(control, ctrl_reg);
767 smc501_writel(control, ctrl_reg);
778 smc501_writel(control, ctrl_reg);
784 smc501_writel(control, ctrl_reg);
789 smc501_writel(control, ctrl_reg);
[all...]
/drivers/regulator/
H A Dwm831x-ldo.c183 int ctrl_reg = ldo->base + WM831X_LDO_CONTROL; local
194 ret = wm831x_reg_read(wm831x, ctrl_reg);
209 int ctrl_reg = ldo->base + WM831X_LDO_CONTROL; local
223 ret = wm831x_set_bits(wm831x, ctrl_reg,
236 ret = wm831x_set_bits(wm831x, ctrl_reg,

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