Searched refs:dpll (Results 1 - 10 of 10) sorted by relevance
/drivers/gpu/drm/gma500/ |
H A D | psb_intel_display.c | 610 u32 dpll = 0, fp = 0, dspcntr, pipeconf; local 654 dpll = DPLL_VGA_MODE_DIS; 656 dpll |= DPLLB_MODE_LVDS; 657 dpll |= DPLL_DVO_HIGH_SPEED; 659 dpll |= DPLLB_MODE_DAC_SERIAL; 663 dpll |= DPLL_DVO_HIGH_SPEED; 664 dpll |= 669 dpll |= (1 << (clock.p1 - 1)) << 16; 672 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 675 dpll | 1119 u32 dpll; local [all...] |
H A D | mdfld_intel_display.c | 787 u32 dpll = 0, fp = 0; local 1073 dpll = REG_READ(dpll_reg); 1075 if (dpll & DPLL_VCO_ENABLE) { 1076 dpll &= ~DPLL_VCO_ENABLE; 1077 REG_WRITE(dpll_reg, dpll); 1086 dpll &= ~MDFLD_P1_MASK; 1087 REG_WRITE(dpll_reg, dpll); 1094 if (dpll & MDFLD_PWR_GATE_EN) { 1095 dpll &= ~MDFLD_PWR_GATE_EN; 1096 REG_WRITE(dpll_reg, dpll); [all...] |
H A D | oaktrail_crtc.c | 308 u32 dpll = 0, fp = 0, dspcntr, pipeconf; local 427 dpll = 0; /*BIT16 = 0 for 100MHz reference */ 441 dpll |= DPLL_VGA_MODE_DIS; 444 dpll |= DPLL_VCO_ENABLE; 447 dpll |= DPLLA_MODE_LVDS; 449 dpll |= DPLLB_MODE_DAC_SERIAL; 455 dpll |= DPLL_DVO_HIGH_SPEED; 456 dpll |= 463 dpll |= (1 << (clock.p1 - 2)) << 17; 465 dpll | [all...] |
H A D | cdv_intel_display.c | 729 u32 dpll = 0, dspcntr, pipeconf; local 776 dpll = DPLL_VGA_MODE_DIS; 779 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 780 dpll |= 3; 782 dpll |= PLL_REF_INPUT_DREFCLK; 784 dpll |= DPLL_SYNCLOCK_ENABLE; 785 dpll |= DPLL_VGA_MODE_DIS; 787 dpll |= DPLLB_MODE_LVDS; 789 dpll |= DPLLB_MODE_DAC_SERIAL; 790 /* dpll | 1301 u32 dpll; local [all...] |
H A D | mdfld_device.c | 361 u32 dpll = 0; local 513 dpll = PSB_RVDC32(dpll_reg); 515 if (!(dpll & DPLL_VCO_ENABLE)) { 519 if (dpll & MDFLD_PWR_GATE_EN) { 520 dpll &= ~MDFLD_PWR_GATE_EN; 521 PSB_WVDC32(dpll, dpll_reg);
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/drivers/ata/ |
H A D | pata_hpt3x2n.c | 317 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); local 324 if ((flags & USE_DPLL) != dpll && alt->qc_active) 333 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); local 335 if ((flags & USE_DPLL) != dpll) { 337 flags |= dpll; 340 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23);
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H A D | pata_hpt37x.c | 983 int dpll, adjust; local 986 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; 988 f_low = (MHz[clock_slot] * 48) / MHz[dpll]; 1016 if (dpll == 3) 1022 MHz[clock_slot], MHz[dpll]);
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/drivers/video/intelfb/ |
H A D | intelfbhw.c | 682 static void intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, argument 688 if (dpll & DPLL_P1_FORCE_DIV2) 691 p1 = (dpll >> DPLL_P1_SHIFT) & 0xff; 695 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK; 697 if (dpll & DPLL_P1_FORCE_DIV2) 700 p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK; 701 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK; 1048 u32 *dpll, *fp0, *fp1; local 1063 dpll = &hw->dpll_b; 1075 dpll 1285 const u32 *dpll, *fp0, *fp1, *pipe_conf; local [all...] |
/drivers/gpu/drm/i915/ |
H A D | intel_display.c | 5159 u32 dpll, dspcntr, pipeconf, vsyncshift; local 5238 dpll = DPLL_VGA_MODE_DIS; 5242 dpll |= DPLLB_MODE_LVDS; 5244 dpll |= DPLLB_MODE_DAC_SERIAL; 5249 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; 5251 dpll |= DPLL_DVO_HIGH_SPEED; 5254 dpll |= DPLL_DVO_HIGH_SPEED; 5258 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; 5260 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 5262 dpll | 5405 I915_WRITE(DPLL(pipe), dpll); local 5427 I915_WRITE(DPLL(pipe), dpll); local 5668 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; local 6006 I915_WRITE(PCH_DPLL(pipe), dpll); local 6017 I915_WRITE(PCH_DPLL(pipe), dpll); local 6881 u32 dpll = I915_READ(DPLL(pipe)); local 7042 int dpll; local 7089 u32 dpll; local [all...] |
/drivers/ide/ |
H A D | hpt366.c | 853 u32 dpll = (f_high << 16) | f_low | 0x100; local 857 pci_write_config_dword(dev, 0x5c, dpll); 874 pci_read_config_dword (dev, 0x5c, &dpll); 875 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
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