1/* 2 * Copyright é 2006-2011 Intel Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, write to the Free Software Foundation, Inc., 15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16 * 17 * Authors: 18 * Eric Anholt <eric@anholt.net> 19 */ 20 21#include <linux/i2c.h> 22#include <linux/pm_runtime.h> 23 24#include <drm/drmP.h> 25#include "framebuffer.h" 26#include "psb_drv.h" 27#include "psb_intel_drv.h" 28#include "psb_intel_reg.h" 29#include "psb_intel_display.h" 30#include "power.h" 31 32struct psb_intel_clock_t { 33 /* given values */ 34 int n; 35 int m1, m2; 36 int p1, p2; 37 /* derived values */ 38 int dot; 39 int vco; 40 int m; 41 int p; 42}; 43 44struct psb_intel_range_t { 45 int min, max; 46}; 47 48struct psb_intel_p2_t { 49 int dot_limit; 50 int p2_slow, p2_fast; 51}; 52 53#define INTEL_P2_NUM 2 54 55struct psb_intel_limit_t { 56 struct psb_intel_range_t dot, vco, n, m, m1, m2, p, p1; 57 struct psb_intel_p2_t p2; 58}; 59 60#define I8XX_DOT_MIN 25000 61#define I8XX_DOT_MAX 350000 62#define I8XX_VCO_MIN 930000 63#define I8XX_VCO_MAX 1400000 64#define I8XX_N_MIN 3 65#define I8XX_N_MAX 16 66#define I8XX_M_MIN 96 67#define I8XX_M_MAX 140 68#define I8XX_M1_MIN 18 69#define I8XX_M1_MAX 26 70#define I8XX_M2_MIN 6 71#define I8XX_M2_MAX 16 72#define I8XX_P_MIN 4 73#define I8XX_P_MAX 128 74#define I8XX_P1_MIN 2 75#define I8XX_P1_MAX 33 76#define I8XX_P1_LVDS_MIN 1 77#define I8XX_P1_LVDS_MAX 6 78#define I8XX_P2_SLOW 4 79#define I8XX_P2_FAST 2 80#define I8XX_P2_LVDS_SLOW 14 81#define I8XX_P2_LVDS_FAST 14 /* No fast option */ 82#define I8XX_P2_SLOW_LIMIT 165000 83 84#define I9XX_DOT_MIN 20000 85#define I9XX_DOT_MAX 400000 86#define I9XX_VCO_MIN 1400000 87#define I9XX_VCO_MAX 2800000 88#define I9XX_N_MIN 3 89#define I9XX_N_MAX 8 90#define I9XX_M_MIN 70 91#define I9XX_M_MAX 120 92#define I9XX_M1_MIN 10 93#define I9XX_M1_MAX 20 94#define I9XX_M2_MIN 5 95#define I9XX_M2_MAX 9 96#define I9XX_P_SDVO_DAC_MIN 5 97#define I9XX_P_SDVO_DAC_MAX 80 98#define I9XX_P_LVDS_MIN 7 99#define I9XX_P_LVDS_MAX 98 100#define I9XX_P1_MIN 1 101#define I9XX_P1_MAX 8 102#define I9XX_P2_SDVO_DAC_SLOW 10 103#define I9XX_P2_SDVO_DAC_FAST 5 104#define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000 105#define I9XX_P2_LVDS_SLOW 14 106#define I9XX_P2_LVDS_FAST 7 107#define I9XX_P2_LVDS_SLOW_LIMIT 112000 108 109#define INTEL_LIMIT_I8XX_DVO_DAC 0 110#define INTEL_LIMIT_I8XX_LVDS 1 111#define INTEL_LIMIT_I9XX_SDVO_DAC 2 112#define INTEL_LIMIT_I9XX_LVDS 3 113 114static const struct psb_intel_limit_t psb_intel_limits[] = { 115 { /* INTEL_LIMIT_I8XX_DVO_DAC */ 116 .dot = {.min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX}, 117 .vco = {.min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX}, 118 .n = {.min = I8XX_N_MIN, .max = I8XX_N_MAX}, 119 .m = {.min = I8XX_M_MIN, .max = I8XX_M_MAX}, 120 .m1 = {.min = I8XX_M1_MIN, .max = I8XX_M1_MAX}, 121 .m2 = {.min = I8XX_M2_MIN, .max = I8XX_M2_MAX}, 122 .p = {.min = I8XX_P_MIN, .max = I8XX_P_MAX}, 123 .p1 = {.min = I8XX_P1_MIN, .max = I8XX_P1_MAX}, 124 .p2 = {.dot_limit = I8XX_P2_SLOW_LIMIT, 125 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST}, 126 }, 127 { /* INTEL_LIMIT_I8XX_LVDS */ 128 .dot = {.min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX}, 129 .vco = {.min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX}, 130 .n = {.min = I8XX_N_MIN, .max = I8XX_N_MAX}, 131 .m = {.min = I8XX_M_MIN, .max = I8XX_M_MAX}, 132 .m1 = {.min = I8XX_M1_MIN, .max = I8XX_M1_MAX}, 133 .m2 = {.min = I8XX_M2_MIN, .max = I8XX_M2_MAX}, 134 .p = {.min = I8XX_P_MIN, .max = I8XX_P_MAX}, 135 .p1 = {.min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX}, 136 .p2 = {.dot_limit = I8XX_P2_SLOW_LIMIT, 137 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST}, 138 }, 139 { /* INTEL_LIMIT_I9XX_SDVO_DAC */ 140 .dot = {.min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, 141 .vco = {.min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX}, 142 .n = {.min = I9XX_N_MIN, .max = I9XX_N_MAX}, 143 .m = {.min = I9XX_M_MIN, .max = I9XX_M_MAX}, 144 .m1 = {.min = I9XX_M1_MIN, .max = I9XX_M1_MAX}, 145 .m2 = {.min = I9XX_M2_MIN, .max = I9XX_M2_MAX}, 146 .p = {.min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX}, 147 .p1 = {.min = I9XX_P1_MIN, .max = I9XX_P1_MAX}, 148 .p2 = {.dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, 149 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = 150 I9XX_P2_SDVO_DAC_FAST}, 151 }, 152 { /* INTEL_LIMIT_I9XX_LVDS */ 153 .dot = {.min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, 154 .vco = {.min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX}, 155 .n = {.min = I9XX_N_MIN, .max = I9XX_N_MAX}, 156 .m = {.min = I9XX_M_MIN, .max = I9XX_M_MAX}, 157 .m1 = {.min = I9XX_M1_MIN, .max = I9XX_M1_MAX}, 158 .m2 = {.min = I9XX_M2_MIN, .max = I9XX_M2_MAX}, 159 .p = {.min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX}, 160 .p1 = {.min = I9XX_P1_MIN, .max = I9XX_P1_MAX}, 161 /* The single-channel range is 25-112Mhz, and dual-channel 162 * is 80-224Mhz. Prefer single channel as much as possible. 163 */ 164 .p2 = {.dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, 165 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST}, 166 }, 167}; 168 169static const struct psb_intel_limit_t *psb_intel_limit(struct drm_crtc *crtc) 170{ 171 const struct psb_intel_limit_t *limit; 172 173 if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 174 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS]; 175 else 176 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC]; 177 return limit; 178} 179 180/** Derive the pixel clock for the given refclk and divisors for 8xx chips. */ 181 182static void i8xx_clock(int refclk, struct psb_intel_clock_t *clock) 183{ 184 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); 185 clock->p = clock->p1 * clock->p2; 186 clock->vco = refclk * clock->m / (clock->n + 2); 187 clock->dot = clock->vco / clock->p; 188} 189 190/** Derive the pixel clock for the given refclk and divisors for 9xx chips. */ 191 192static void i9xx_clock(int refclk, struct psb_intel_clock_t *clock) 193{ 194 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); 195 clock->p = clock->p1 * clock->p2; 196 clock->vco = refclk * clock->m / (clock->n + 2); 197 clock->dot = clock->vco / clock->p; 198} 199 200static void psb_intel_clock(struct drm_device *dev, int refclk, 201 struct psb_intel_clock_t *clock) 202{ 203 return i9xx_clock(refclk, clock); 204} 205 206/** 207 * Returns whether any output on the specified pipe is of the specified type 208 */ 209bool psb_intel_pipe_has_type(struct drm_crtc *crtc, int type) 210{ 211 struct drm_device *dev = crtc->dev; 212 struct drm_mode_config *mode_config = &dev->mode_config; 213 struct drm_connector *l_entry; 214 215 list_for_each_entry(l_entry, &mode_config->connector_list, head) { 216 if (l_entry->encoder && l_entry->encoder->crtc == crtc) { 217 struct psb_intel_encoder *psb_intel_encoder = 218 psb_intel_attached_encoder(l_entry); 219 if (psb_intel_encoder->type == type) 220 return true; 221 } 222 } 223 return false; 224} 225 226#define INTELPllInvalid(s) { /* ErrorF (s) */; return false; } 227/** 228 * Returns whether the given set of divisors are valid for a given refclk with 229 * the given connectors. 230 */ 231 232static bool psb_intel_PLL_is_valid(struct drm_crtc *crtc, 233 struct psb_intel_clock_t *clock) 234{ 235 const struct psb_intel_limit_t *limit = psb_intel_limit(crtc); 236 237 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) 238 INTELPllInvalid("p1 out of range\n"); 239 if (clock->p < limit->p.min || limit->p.max < clock->p) 240 INTELPllInvalid("p out of range\n"); 241 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) 242 INTELPllInvalid("m2 out of range\n"); 243 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 244 INTELPllInvalid("m1 out of range\n"); 245 if (clock->m1 <= clock->m2) 246 INTELPllInvalid("m1 <= m2\n"); 247 if (clock->m < limit->m.min || limit->m.max < clock->m) 248 INTELPllInvalid("m out of range\n"); 249 if (clock->n < limit->n.min || limit->n.max < clock->n) 250 INTELPllInvalid("n out of range\n"); 251 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) 252 INTELPllInvalid("vco out of range\n"); 253 /* XXX: We may need to be checking "Dot clock" 254 * depending on the multiplier, connector, etc., 255 * rather than just a single range. 256 */ 257 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) 258 INTELPllInvalid("dot out of range\n"); 259 260 return true; 261} 262 263/** 264 * Returns a set of divisors for the desired target clock with the given 265 * refclk, or FALSE. The returned values represent the clock equation: 266 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 267 */ 268static bool psb_intel_find_best_PLL(struct drm_crtc *crtc, int target, 269 int refclk, 270 struct psb_intel_clock_t *best_clock) 271{ 272 struct drm_device *dev = crtc->dev; 273 struct psb_intel_clock_t clock; 274 const struct psb_intel_limit_t *limit = psb_intel_limit(crtc); 275 int err = target; 276 277 if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 278 (REG_READ(LVDS) & LVDS_PORT_EN) != 0) { 279 /* 280 * For LVDS, if the panel is on, just rely on its current 281 * settings for dual-channel. We haven't figured out how to 282 * reliably set up different single/dual channel state, if we 283 * even can. 284 */ 285 if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) == 286 LVDS_CLKB_POWER_UP) 287 clock.p2 = limit->p2.p2_fast; 288 else 289 clock.p2 = limit->p2.p2_slow; 290 } else { 291 if (target < limit->p2.dot_limit) 292 clock.p2 = limit->p2.p2_slow; 293 else 294 clock.p2 = limit->p2.p2_fast; 295 } 296 297 memset(best_clock, 0, sizeof(*best_clock)); 298 299 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 300 clock.m1++) { 301 for (clock.m2 = limit->m2.min; 302 clock.m2 < clock.m1 && clock.m2 <= limit->m2.max; 303 clock.m2++) { 304 for (clock.n = limit->n.min; 305 clock.n <= limit->n.max; clock.n++) { 306 for (clock.p1 = limit->p1.min; 307 clock.p1 <= limit->p1.max; 308 clock.p1++) { 309 int this_err; 310 311 psb_intel_clock(dev, refclk, &clock); 312 313 if (!psb_intel_PLL_is_valid 314 (crtc, &clock)) 315 continue; 316 317 this_err = abs(clock.dot - target); 318 if (this_err < err) { 319 *best_clock = clock; 320 err = this_err; 321 } 322 } 323 } 324 } 325 } 326 327 return err != target; 328} 329 330void psb_intel_wait_for_vblank(struct drm_device *dev) 331{ 332 /* Wait for 20ms, i.e. one cycle at 50hz. */ 333 mdelay(20); 334} 335 336static int psb_intel_pipe_set_base(struct drm_crtc *crtc, 337 int x, int y, struct drm_framebuffer *old_fb) 338{ 339 struct drm_device *dev = crtc->dev; 340 /* struct drm_i915_master_private *master_priv; */ 341 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 342 struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb); 343 int pipe = psb_intel_crtc->pipe; 344 unsigned long start, offset; 345 int dspbase = (pipe == 0 ? DSPABASE : DSPBBASE); 346 int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF); 347 int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE; 348 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; 349 u32 dspcntr; 350 int ret = 0; 351 352 if (!gma_power_begin(dev, true)) 353 return 0; 354 355 /* no fb bound */ 356 if (!crtc->fb) { 357 dev_dbg(dev->dev, "No FB bound\n"); 358 goto psb_intel_pipe_cleaner; 359 } 360 361 /* We are displaying this buffer, make sure it is actually loaded 362 into the GTT */ 363 ret = psb_gtt_pin(psbfb->gtt); 364 if (ret < 0) 365 goto psb_intel_pipe_set_base_exit; 366 start = psbfb->gtt->offset; 367 368 offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8); 369 370 REG_WRITE(dspstride, crtc->fb->pitches[0]); 371 372 dspcntr = REG_READ(dspcntr_reg); 373 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; 374 375 switch (crtc->fb->bits_per_pixel) { 376 case 8: 377 dspcntr |= DISPPLANE_8BPP; 378 break; 379 case 16: 380 if (crtc->fb->depth == 15) 381 dspcntr |= DISPPLANE_15_16BPP; 382 else 383 dspcntr |= DISPPLANE_16BPP; 384 break; 385 case 24: 386 case 32: 387 dspcntr |= DISPPLANE_32BPP_NO_ALPHA; 388 break; 389 default: 390 dev_err(dev->dev, "Unknown color depth\n"); 391 ret = -EINVAL; 392 psb_gtt_unpin(psbfb->gtt); 393 goto psb_intel_pipe_set_base_exit; 394 } 395 REG_WRITE(dspcntr_reg, dspcntr); 396 397 398 if (0 /* FIXMEAC - check what PSB needs */) { 399 REG_WRITE(dspbase, offset); 400 REG_READ(dspbase); 401 REG_WRITE(dspsurf, start); 402 REG_READ(dspsurf); 403 } else { 404 REG_WRITE(dspbase, start + offset); 405 REG_READ(dspbase); 406 } 407 408psb_intel_pipe_cleaner: 409 /* If there was a previous display we can now unpin it */ 410 if (old_fb) 411 psb_gtt_unpin(to_psb_fb(old_fb)->gtt); 412 413psb_intel_pipe_set_base_exit: 414 gma_power_end(dev); 415 return ret; 416} 417 418/** 419 * Sets the power management mode of the pipe and plane. 420 * 421 * This code should probably grow support for turning the cursor off and back 422 * on appropriately at the same time as we're turning the pipe off/on. 423 */ 424static void psb_intel_crtc_dpms(struct drm_crtc *crtc, int mode) 425{ 426 struct drm_device *dev = crtc->dev; 427 /* struct drm_i915_master_private *master_priv; */ 428 /* struct drm_i915_private *dev_priv = dev->dev_private; */ 429 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 430 int pipe = psb_intel_crtc->pipe; 431 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; 432 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; 433 int dspbase_reg = (pipe == 0) ? DSPABASE : DSPBBASE; 434 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; 435 u32 temp; 436 437 /* XXX: When our outputs are all unaware of DPMS modes other than off 438 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. 439 */ 440 switch (mode) { 441 case DRM_MODE_DPMS_ON: 442 case DRM_MODE_DPMS_STANDBY: 443 case DRM_MODE_DPMS_SUSPEND: 444 /* Enable the DPLL */ 445 temp = REG_READ(dpll_reg); 446 if ((temp & DPLL_VCO_ENABLE) == 0) { 447 REG_WRITE(dpll_reg, temp); 448 REG_READ(dpll_reg); 449 /* Wait for the clocks to stabilize. */ 450 udelay(150); 451 REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); 452 REG_READ(dpll_reg); 453 /* Wait for the clocks to stabilize. */ 454 udelay(150); 455 REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); 456 REG_READ(dpll_reg); 457 /* Wait for the clocks to stabilize. */ 458 udelay(150); 459 } 460 461 /* Enable the pipe */ 462 temp = REG_READ(pipeconf_reg); 463 if ((temp & PIPEACONF_ENABLE) == 0) 464 REG_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE); 465 466 /* Enable the plane */ 467 temp = REG_READ(dspcntr_reg); 468 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { 469 REG_WRITE(dspcntr_reg, 470 temp | DISPLAY_PLANE_ENABLE); 471 /* Flush the plane changes */ 472 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); 473 } 474 475 psb_intel_crtc_load_lut(crtc); 476 477 /* Give the overlay scaler a chance to enable 478 * if it's on this pipe */ 479 /* psb_intel_crtc_dpms_video(crtc, true); TODO */ 480 break; 481 case DRM_MODE_DPMS_OFF: 482 /* Give the overlay scaler a chance to disable 483 * if it's on this pipe */ 484 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */ 485 486 /* Disable the VGA plane that we never use */ 487 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); 488 489 /* Disable display plane */ 490 temp = REG_READ(dspcntr_reg); 491 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { 492 REG_WRITE(dspcntr_reg, 493 temp & ~DISPLAY_PLANE_ENABLE); 494 /* Flush the plane changes */ 495 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); 496 REG_READ(dspbase_reg); 497 } 498 499 /* Next, disable display pipes */ 500 temp = REG_READ(pipeconf_reg); 501 if ((temp & PIPEACONF_ENABLE) != 0) { 502 REG_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); 503 REG_READ(pipeconf_reg); 504 } 505 506 /* Wait for vblank for the disable to take effect. */ 507 psb_intel_wait_for_vblank(dev); 508 509 temp = REG_READ(dpll_reg); 510 if ((temp & DPLL_VCO_ENABLE) != 0) { 511 REG_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE); 512 REG_READ(dpll_reg); 513 } 514 515 /* Wait for the clocks to turn off. */ 516 udelay(150); 517 break; 518 } 519 520 /*Set FIFO Watermarks*/ 521 REG_WRITE(DSPARB, 0x3F3E); 522} 523 524static void psb_intel_crtc_prepare(struct drm_crtc *crtc) 525{ 526 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 527 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); 528} 529 530static void psb_intel_crtc_commit(struct drm_crtc *crtc) 531{ 532 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 533 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); 534} 535 536void psb_intel_encoder_prepare(struct drm_encoder *encoder) 537{ 538 struct drm_encoder_helper_funcs *encoder_funcs = 539 encoder->helper_private; 540 /* lvds has its own version of prepare see psb_intel_lvds_prepare */ 541 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); 542} 543 544void psb_intel_encoder_commit(struct drm_encoder *encoder) 545{ 546 struct drm_encoder_helper_funcs *encoder_funcs = 547 encoder->helper_private; 548 /* lvds has its own version of commit see psb_intel_lvds_commit */ 549 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); 550} 551 552void psb_intel_encoder_destroy(struct drm_encoder *encoder) 553{ 554 struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder); 555 556 drm_encoder_cleanup(encoder); 557 kfree(intel_encoder); 558} 559 560static bool psb_intel_crtc_mode_fixup(struct drm_crtc *crtc, 561 struct drm_display_mode *mode, 562 struct drm_display_mode *adjusted_mode) 563{ 564 return true; 565} 566 567 568/** 569 * Return the pipe currently connected to the panel fitter, 570 * or -1 if the panel fitter is not present or not in use 571 */ 572static int psb_intel_panel_fitter_pipe(struct drm_device *dev) 573{ 574 u32 pfit_control; 575 576 pfit_control = REG_READ(PFIT_CONTROL); 577 578 /* See if the panel fitter is in use */ 579 if ((pfit_control & PFIT_ENABLE) == 0) 580 return -1; 581 /* Must be on PIPE 1 for PSB */ 582 return 1; 583} 584 585static int psb_intel_crtc_mode_set(struct drm_crtc *crtc, 586 struct drm_display_mode *mode, 587 struct drm_display_mode *adjusted_mode, 588 int x, int y, 589 struct drm_framebuffer *old_fb) 590{ 591 struct drm_device *dev = crtc->dev; 592 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 593 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 594 int pipe = psb_intel_crtc->pipe; 595 int fp_reg = (pipe == 0) ? FPA0 : FPB0; 596 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; 597 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; 598 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; 599 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; 600 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; 601 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; 602 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B; 603 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B; 604 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B; 605 int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE; 606 int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS; 607 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC; 608 int refclk; 609 struct psb_intel_clock_t clock; 610 u32 dpll = 0, fp = 0, dspcntr, pipeconf; 611 bool ok, is_sdvo = false; 612 bool is_lvds = false, is_tv = false; 613 struct drm_mode_config *mode_config = &dev->mode_config; 614 struct drm_connector *connector; 615 616 /* No scan out no play */ 617 if (crtc->fb == NULL) { 618 crtc_funcs->mode_set_base(crtc, x, y, old_fb); 619 return 0; 620 } 621 622 list_for_each_entry(connector, &mode_config->connector_list, head) { 623 struct psb_intel_encoder *psb_intel_encoder = 624 psb_intel_attached_encoder(connector); 625 626 if (!connector->encoder 627 || connector->encoder->crtc != crtc) 628 continue; 629 630 switch (psb_intel_encoder->type) { 631 case INTEL_OUTPUT_LVDS: 632 is_lvds = true; 633 break; 634 case INTEL_OUTPUT_SDVO: 635 is_sdvo = true; 636 break; 637 case INTEL_OUTPUT_TVOUT: 638 is_tv = true; 639 break; 640 } 641 } 642 643 refclk = 96000; 644 645 ok = psb_intel_find_best_PLL(crtc, adjusted_mode->clock, refclk, 646 &clock); 647 if (!ok) { 648 dev_err(dev->dev, "Couldn't find PLL settings for mode!\n"); 649 return 0; 650 } 651 652 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; 653 654 dpll = DPLL_VGA_MODE_DIS; 655 if (is_lvds) { 656 dpll |= DPLLB_MODE_LVDS; 657 dpll |= DPLL_DVO_HIGH_SPEED; 658 } else 659 dpll |= DPLLB_MODE_DAC_SERIAL; 660 if (is_sdvo) { 661 int sdvo_pixel_multiply = 662 adjusted_mode->clock / mode->clock; 663 dpll |= DPLL_DVO_HIGH_SPEED; 664 dpll |= 665 (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; 666 } 667 668 /* compute bitmask from p1 value */ 669 dpll |= (1 << (clock.p1 - 1)) << 16; 670 switch (clock.p2) { 671 case 5: 672 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 673 break; 674 case 7: 675 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 676 break; 677 case 10: 678 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 679 break; 680 case 14: 681 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 682 break; 683 } 684 685 if (is_tv) { 686 /* XXX: just matching BIOS for now */ 687/* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 688 dpll |= 3; 689 } 690 dpll |= PLL_REF_INPUT_DREFCLK; 691 692 /* setup pipeconf */ 693 pipeconf = REG_READ(pipeconf_reg); 694 695 /* Set up the display plane register */ 696 dspcntr = DISPPLANE_GAMMA_ENABLE; 697 698 if (pipe == 0) 699 dspcntr |= DISPPLANE_SEL_PIPE_A; 700 else 701 dspcntr |= DISPPLANE_SEL_PIPE_B; 702 703 dspcntr |= DISPLAY_PLANE_ENABLE; 704 pipeconf |= PIPEACONF_ENABLE; 705 dpll |= DPLL_VCO_ENABLE; 706 707 708 /* Disable the panel fitter if it was on our pipe */ 709 if (psb_intel_panel_fitter_pipe(dev) == pipe) 710 REG_WRITE(PFIT_CONTROL, 0); 711 712 drm_mode_debug_printmodeline(mode); 713 714 if (dpll & DPLL_VCO_ENABLE) { 715 REG_WRITE(fp_reg, fp); 716 REG_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); 717 REG_READ(dpll_reg); 718 udelay(150); 719 } 720 721 /* The LVDS pin pair needs to be on before the DPLLs are enabled. 722 * This is an exception to the general rule that mode_set doesn't turn 723 * things on. 724 */ 725 if (is_lvds) { 726 u32 lvds = REG_READ(LVDS); 727 728 lvds &= ~LVDS_PIPEB_SELECT; 729 if (pipe == 1) 730 lvds |= LVDS_PIPEB_SELECT; 731 732 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 733 /* Set the B0-B3 data pairs corresponding to 734 * whether we're going to 735 * set the DPLLs for dual-channel mode or not. 736 */ 737 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 738 if (clock.p2 == 7) 739 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 740 741 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 742 * appropriately here, but we need to look more 743 * thoroughly into how panels behave in the two modes. 744 */ 745 746 REG_WRITE(LVDS, lvds); 747 REG_READ(LVDS); 748 } 749 750 REG_WRITE(fp_reg, fp); 751 REG_WRITE(dpll_reg, dpll); 752 REG_READ(dpll_reg); 753 /* Wait for the clocks to stabilize. */ 754 udelay(150); 755 756 /* write it again -- the BIOS does, after all */ 757 REG_WRITE(dpll_reg, dpll); 758 759 REG_READ(dpll_reg); 760 /* Wait for the clocks to stabilize. */ 761 udelay(150); 762 763 REG_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) | 764 ((adjusted_mode->crtc_htotal - 1) << 16)); 765 REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | 766 ((adjusted_mode->crtc_hblank_end - 1) << 16)); 767 REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | 768 ((adjusted_mode->crtc_hsync_end - 1) << 16)); 769 REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | 770 ((adjusted_mode->crtc_vtotal - 1) << 16)); 771 REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | 772 ((adjusted_mode->crtc_vblank_end - 1) << 16)); 773 REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | 774 ((adjusted_mode->crtc_vsync_end - 1) << 16)); 775 /* pipesrc and dspsize control the size that is scaled from, 776 * which should always be the user's requested size. 777 */ 778 REG_WRITE(dspsize_reg, 779 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); 780 REG_WRITE(dsppos_reg, 0); 781 REG_WRITE(pipesrc_reg, 782 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 783 REG_WRITE(pipeconf_reg, pipeconf); 784 REG_READ(pipeconf_reg); 785 786 psb_intel_wait_for_vblank(dev); 787 788 REG_WRITE(dspcntr_reg, dspcntr); 789 790 /* Flush the plane changes */ 791 crtc_funcs->mode_set_base(crtc, x, y, old_fb); 792 793 psb_intel_wait_for_vblank(dev); 794 795 return 0; 796} 797 798/** Loads the palette/gamma unit for the CRTC with the prepared values */ 799void psb_intel_crtc_load_lut(struct drm_crtc *crtc) 800{ 801 struct drm_device *dev = crtc->dev; 802 struct drm_psb_private *dev_priv = 803 (struct drm_psb_private *)dev->dev_private; 804 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 805 int palreg = PALETTE_A; 806 int i; 807 808 /* The clocks have to be on to load the palette. */ 809 if (!crtc->enabled) 810 return; 811 812 switch (psb_intel_crtc->pipe) { 813 case 0: 814 break; 815 case 1: 816 palreg = PALETTE_B; 817 break; 818 case 2: 819 palreg = PALETTE_C; 820 break; 821 default: 822 dev_err(dev->dev, "Illegal Pipe Number.\n"); 823 return; 824 } 825 826 if (gma_power_begin(dev, false)) { 827 for (i = 0; i < 256; i++) { 828 REG_WRITE(palreg + 4 * i, 829 ((psb_intel_crtc->lut_r[i] + 830 psb_intel_crtc->lut_adj[i]) << 16) | 831 ((psb_intel_crtc->lut_g[i] + 832 psb_intel_crtc->lut_adj[i]) << 8) | 833 (psb_intel_crtc->lut_b[i] + 834 psb_intel_crtc->lut_adj[i])); 835 } 836 gma_power_end(dev); 837 } else { 838 for (i = 0; i < 256; i++) { 839 dev_priv->regs.psb.save_palette_a[i] = 840 ((psb_intel_crtc->lut_r[i] + 841 psb_intel_crtc->lut_adj[i]) << 16) | 842 ((psb_intel_crtc->lut_g[i] + 843 psb_intel_crtc->lut_adj[i]) << 8) | 844 (psb_intel_crtc->lut_b[i] + 845 psb_intel_crtc->lut_adj[i]); 846 } 847 848 } 849} 850 851/** 852 * Save HW states of giving crtc 853 */ 854static void psb_intel_crtc_save(struct drm_crtc *crtc) 855{ 856 struct drm_device *dev = crtc->dev; 857 /* struct drm_psb_private *dev_priv = 858 (struct drm_psb_private *)dev->dev_private; */ 859 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 860 struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state; 861 int pipeA = (psb_intel_crtc->pipe == 0); 862 uint32_t paletteReg; 863 int i; 864 865 if (!crtc_state) { 866 dev_err(dev->dev, "No CRTC state found\n"); 867 return; 868 } 869 870 crtc_state->saveDSPCNTR = REG_READ(pipeA ? DSPACNTR : DSPBCNTR); 871 crtc_state->savePIPECONF = REG_READ(pipeA ? PIPEACONF : PIPEBCONF); 872 crtc_state->savePIPESRC = REG_READ(pipeA ? PIPEASRC : PIPEBSRC); 873 crtc_state->saveFP0 = REG_READ(pipeA ? FPA0 : FPB0); 874 crtc_state->saveFP1 = REG_READ(pipeA ? FPA1 : FPB1); 875 crtc_state->saveDPLL = REG_READ(pipeA ? DPLL_A : DPLL_B); 876 crtc_state->saveHTOTAL = REG_READ(pipeA ? HTOTAL_A : HTOTAL_B); 877 crtc_state->saveHBLANK = REG_READ(pipeA ? HBLANK_A : HBLANK_B); 878 crtc_state->saveHSYNC = REG_READ(pipeA ? HSYNC_A : HSYNC_B); 879 crtc_state->saveVTOTAL = REG_READ(pipeA ? VTOTAL_A : VTOTAL_B); 880 crtc_state->saveVBLANK = REG_READ(pipeA ? VBLANK_A : VBLANK_B); 881 crtc_state->saveVSYNC = REG_READ(pipeA ? VSYNC_A : VSYNC_B); 882 crtc_state->saveDSPSTRIDE = REG_READ(pipeA ? DSPASTRIDE : DSPBSTRIDE); 883 884 /*NOTE: DSPSIZE DSPPOS only for psb*/ 885 crtc_state->saveDSPSIZE = REG_READ(pipeA ? DSPASIZE : DSPBSIZE); 886 crtc_state->saveDSPPOS = REG_READ(pipeA ? DSPAPOS : DSPBPOS); 887 888 crtc_state->saveDSPBASE = REG_READ(pipeA ? DSPABASE : DSPBBASE); 889 890 paletteReg = pipeA ? PALETTE_A : PALETTE_B; 891 for (i = 0; i < 256; ++i) 892 crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2)); 893} 894 895/** 896 * Restore HW states of giving crtc 897 */ 898static void psb_intel_crtc_restore(struct drm_crtc *crtc) 899{ 900 struct drm_device *dev = crtc->dev; 901 /* struct drm_psb_private * dev_priv = 902 (struct drm_psb_private *)dev->dev_private; */ 903 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 904 struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state; 905 /* struct drm_crtc_helper_funcs * crtc_funcs = crtc->helper_private; */ 906 int pipeA = (psb_intel_crtc->pipe == 0); 907 uint32_t paletteReg; 908 int i; 909 910 if (!crtc_state) { 911 dev_err(dev->dev, "No crtc state\n"); 912 return; 913 } 914 915 if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) { 916 REG_WRITE(pipeA ? DPLL_A : DPLL_B, 917 crtc_state->saveDPLL & ~DPLL_VCO_ENABLE); 918 REG_READ(pipeA ? DPLL_A : DPLL_B); 919 udelay(150); 920 } 921 922 REG_WRITE(pipeA ? FPA0 : FPB0, crtc_state->saveFP0); 923 REG_READ(pipeA ? FPA0 : FPB0); 924 925 REG_WRITE(pipeA ? FPA1 : FPB1, crtc_state->saveFP1); 926 REG_READ(pipeA ? FPA1 : FPB1); 927 928 REG_WRITE(pipeA ? DPLL_A : DPLL_B, crtc_state->saveDPLL); 929 REG_READ(pipeA ? DPLL_A : DPLL_B); 930 udelay(150); 931 932 REG_WRITE(pipeA ? HTOTAL_A : HTOTAL_B, crtc_state->saveHTOTAL); 933 REG_WRITE(pipeA ? HBLANK_A : HBLANK_B, crtc_state->saveHBLANK); 934 REG_WRITE(pipeA ? HSYNC_A : HSYNC_B, crtc_state->saveHSYNC); 935 REG_WRITE(pipeA ? VTOTAL_A : VTOTAL_B, crtc_state->saveVTOTAL); 936 REG_WRITE(pipeA ? VBLANK_A : VBLANK_B, crtc_state->saveVBLANK); 937 REG_WRITE(pipeA ? VSYNC_A : VSYNC_B, crtc_state->saveVSYNC); 938 REG_WRITE(pipeA ? DSPASTRIDE : DSPBSTRIDE, crtc_state->saveDSPSTRIDE); 939 940 REG_WRITE(pipeA ? DSPASIZE : DSPBSIZE, crtc_state->saveDSPSIZE); 941 REG_WRITE(pipeA ? DSPAPOS : DSPBPOS, crtc_state->saveDSPPOS); 942 943 REG_WRITE(pipeA ? PIPEASRC : PIPEBSRC, crtc_state->savePIPESRC); 944 REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE); 945 REG_WRITE(pipeA ? PIPEACONF : PIPEBCONF, crtc_state->savePIPECONF); 946 947 psb_intel_wait_for_vblank(dev); 948 949 REG_WRITE(pipeA ? DSPACNTR : DSPBCNTR, crtc_state->saveDSPCNTR); 950 REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE); 951 952 psb_intel_wait_for_vblank(dev); 953 954 paletteReg = pipeA ? PALETTE_A : PALETTE_B; 955 for (i = 0; i < 256; ++i) 956 REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]); 957} 958 959static int psb_intel_crtc_cursor_set(struct drm_crtc *crtc, 960 struct drm_file *file_priv, 961 uint32_t handle, 962 uint32_t width, uint32_t height) 963{ 964 struct drm_device *dev = crtc->dev; 965 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 966 int pipe = psb_intel_crtc->pipe; 967 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR; 968 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE; 969 uint32_t temp; 970 size_t addr = 0; 971 struct gtt_range *gt; 972 struct drm_gem_object *obj; 973 int ret; 974 975 /* if we want to turn of the cursor ignore width and height */ 976 if (!handle) { 977 /* turn off the cursor */ 978 temp = CURSOR_MODE_DISABLE; 979 980 if (gma_power_begin(dev, false)) { 981 REG_WRITE(control, temp); 982 REG_WRITE(base, 0); 983 gma_power_end(dev); 984 } 985 986 /* Unpin the old GEM object */ 987 if (psb_intel_crtc->cursor_obj) { 988 gt = container_of(psb_intel_crtc->cursor_obj, 989 struct gtt_range, gem); 990 psb_gtt_unpin(gt); 991 drm_gem_object_unreference(psb_intel_crtc->cursor_obj); 992 psb_intel_crtc->cursor_obj = NULL; 993 } 994 995 return 0; 996 } 997 998 /* Currently we only support 64x64 cursors */ 999 if (width != 64 || height != 64) { 1000 dev_dbg(dev->dev, "we currently only support 64x64 cursors\n"); 1001 return -EINVAL; 1002 } 1003 1004 obj = drm_gem_object_lookup(dev, file_priv, handle); 1005 if (!obj) 1006 return -ENOENT; 1007 1008 if (obj->size < width * height * 4) { 1009 dev_dbg(dev->dev, "buffer is to small\n"); 1010 return -ENOMEM; 1011 } 1012 1013 gt = container_of(obj, struct gtt_range, gem); 1014 1015 /* Pin the memory into the GTT */ 1016 ret = psb_gtt_pin(gt); 1017 if (ret) { 1018 dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle); 1019 return ret; 1020 } 1021 1022 1023 addr = gt->offset; /* Or resource.start ??? */ 1024 1025 psb_intel_crtc->cursor_addr = addr; 1026 1027 temp = 0; 1028 /* set the pipe for the cursor */ 1029 temp |= (pipe << 28); 1030 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; 1031 1032 if (gma_power_begin(dev, false)) { 1033 REG_WRITE(control, temp); 1034 REG_WRITE(base, addr); 1035 gma_power_end(dev); 1036 } 1037 1038 /* unpin the old bo */ 1039 if (psb_intel_crtc->cursor_obj) { 1040 gt = container_of(psb_intel_crtc->cursor_obj, 1041 struct gtt_range, gem); 1042 psb_gtt_unpin(gt); 1043 drm_gem_object_unreference(psb_intel_crtc->cursor_obj); 1044 psb_intel_crtc->cursor_obj = obj; 1045 } 1046 return 0; 1047} 1048 1049static int psb_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 1050{ 1051 struct drm_device *dev = crtc->dev; 1052 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 1053 int pipe = psb_intel_crtc->pipe; 1054 uint32_t temp = 0; 1055 uint32_t addr; 1056 1057 1058 if (x < 0) { 1059 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT); 1060 x = -x; 1061 } 1062 if (y < 0) { 1063 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT); 1064 y = -y; 1065 } 1066 1067 temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT); 1068 temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT); 1069 1070 addr = psb_intel_crtc->cursor_addr; 1071 1072 if (gma_power_begin(dev, false)) { 1073 REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp); 1074 REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, addr); 1075 gma_power_end(dev); 1076 } 1077 return 0; 1078} 1079 1080void psb_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, 1081 u16 *green, u16 *blue, uint32_t type, uint32_t size) 1082{ 1083 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 1084 int i; 1085 1086 if (size != 256) 1087 return; 1088 1089 for (i = 0; i < 256; i++) { 1090 psb_intel_crtc->lut_r[i] = red[i] >> 8; 1091 psb_intel_crtc->lut_g[i] = green[i] >> 8; 1092 psb_intel_crtc->lut_b[i] = blue[i] >> 8; 1093 } 1094 1095 psb_intel_crtc_load_lut(crtc); 1096} 1097 1098static int psb_crtc_set_config(struct drm_mode_set *set) 1099{ 1100 int ret; 1101 struct drm_device *dev = set->crtc->dev; 1102 struct drm_psb_private *dev_priv = dev->dev_private; 1103 1104 if (!dev_priv->rpm_enabled) 1105 return drm_crtc_helper_set_config(set); 1106 1107 pm_runtime_forbid(&dev->pdev->dev); 1108 ret = drm_crtc_helper_set_config(set); 1109 pm_runtime_allow(&dev->pdev->dev); 1110 return ret; 1111} 1112 1113/* Returns the clock of the currently programmed mode of the given pipe. */ 1114static int psb_intel_crtc_clock_get(struct drm_device *dev, 1115 struct drm_crtc *crtc) 1116{ 1117 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 1118 int pipe = psb_intel_crtc->pipe; 1119 u32 dpll; 1120 u32 fp; 1121 struct psb_intel_clock_t clock; 1122 bool is_lvds; 1123 struct drm_psb_private *dev_priv = dev->dev_private; 1124 1125 if (gma_power_begin(dev, false)) { 1126 dpll = REG_READ((pipe == 0) ? DPLL_A : DPLL_B); 1127 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 1128 fp = REG_READ((pipe == 0) ? FPA0 : FPB0); 1129 else 1130 fp = REG_READ((pipe == 0) ? FPA1 : FPB1); 1131 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); 1132 gma_power_end(dev); 1133 } else { 1134 dpll = (pipe == 0) ? 1135 dev_priv->regs.psb.saveDPLL_A : 1136 dev_priv->regs.psb.saveDPLL_B; 1137 1138 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 1139 fp = (pipe == 0) ? 1140 dev_priv->regs.psb.saveFPA0 : 1141 dev_priv->regs.psb.saveFPB0; 1142 else 1143 fp = (pipe == 0) ? 1144 dev_priv->regs.psb.saveFPA1 : 1145 dev_priv->regs.psb.saveFPB1; 1146 1147 is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS & 1148 LVDS_PORT_EN); 1149 } 1150 1151 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 1152 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 1153 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 1154 1155 if (is_lvds) { 1156 clock.p1 = 1157 ffs((dpll & 1158 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 1159 DPLL_FPA01_P1_POST_DIV_SHIFT); 1160 clock.p2 = 14; 1161 1162 if ((dpll & PLL_REF_INPUT_MASK) == 1163 PLLB_REF_INPUT_SPREADSPECTRUMIN) { 1164 /* XXX: might not be 66MHz */ 1165 i8xx_clock(66000, &clock); 1166 } else 1167 i8xx_clock(48000, &clock); 1168 } else { 1169 if (dpll & PLL_P1_DIVIDE_BY_TWO) 1170 clock.p1 = 2; 1171 else { 1172 clock.p1 = 1173 ((dpll & 1174 DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 1175 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 1176 } 1177 if (dpll & PLL_P2_DIVIDE_BY_4) 1178 clock.p2 = 4; 1179 else 1180 clock.p2 = 2; 1181 1182 i8xx_clock(48000, &clock); 1183 } 1184 1185 /* XXX: It would be nice to validate the clocks, but we can't reuse 1186 * i830PllIsValid() because it relies on the xf86_config connector 1187 * configuration being accurate, which it isn't necessarily. 1188 */ 1189 1190 return clock.dot; 1191} 1192 1193/** Returns the currently programmed mode of the given pipe. */ 1194struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev, 1195 struct drm_crtc *crtc) 1196{ 1197 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 1198 int pipe = psb_intel_crtc->pipe; 1199 struct drm_display_mode *mode; 1200 int htot; 1201 int hsync; 1202 int vtot; 1203 int vsync; 1204 struct drm_psb_private *dev_priv = dev->dev_private; 1205 1206 if (gma_power_begin(dev, false)) { 1207 htot = REG_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); 1208 hsync = REG_READ((pipe == 0) ? HSYNC_A : HSYNC_B); 1209 vtot = REG_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B); 1210 vsync = REG_READ((pipe == 0) ? VSYNC_A : VSYNC_B); 1211 gma_power_end(dev); 1212 } else { 1213 htot = (pipe == 0) ? 1214 dev_priv->regs.psb.saveHTOTAL_A : 1215 dev_priv->regs.psb.saveHTOTAL_B; 1216 hsync = (pipe == 0) ? 1217 dev_priv->regs.psb.saveHSYNC_A : 1218 dev_priv->regs.psb.saveHSYNC_B; 1219 vtot = (pipe == 0) ? 1220 dev_priv->regs.psb.saveVTOTAL_A : 1221 dev_priv->regs.psb.saveVTOTAL_B; 1222 vsync = (pipe == 0) ? 1223 dev_priv->regs.psb.saveVSYNC_A : 1224 dev_priv->regs.psb.saveVSYNC_B; 1225 } 1226 1227 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 1228 if (!mode) 1229 return NULL; 1230 1231 mode->clock = psb_intel_crtc_clock_get(dev, crtc); 1232 mode->hdisplay = (htot & 0xffff) + 1; 1233 mode->htotal = ((htot & 0xffff0000) >> 16) + 1; 1234 mode->hsync_start = (hsync & 0xffff) + 1; 1235 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; 1236 mode->vdisplay = (vtot & 0xffff) + 1; 1237 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; 1238 mode->vsync_start = (vsync & 0xffff) + 1; 1239 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; 1240 1241 drm_mode_set_name(mode); 1242 drm_mode_set_crtcinfo(mode, 0); 1243 1244 return mode; 1245} 1246 1247void psb_intel_crtc_destroy(struct drm_crtc *crtc) 1248{ 1249 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 1250 struct gtt_range *gt; 1251 1252 /* Unpin the old GEM object */ 1253 if (psb_intel_crtc->cursor_obj) { 1254 gt = container_of(psb_intel_crtc->cursor_obj, 1255 struct gtt_range, gem); 1256 psb_gtt_unpin(gt); 1257 drm_gem_object_unreference(psb_intel_crtc->cursor_obj); 1258 psb_intel_crtc->cursor_obj = NULL; 1259 } 1260 kfree(psb_intel_crtc->crtc_state); 1261 drm_crtc_cleanup(crtc); 1262 kfree(psb_intel_crtc); 1263} 1264 1265const struct drm_crtc_helper_funcs psb_intel_helper_funcs = { 1266 .dpms = psb_intel_crtc_dpms, 1267 .mode_fixup = psb_intel_crtc_mode_fixup, 1268 .mode_set = psb_intel_crtc_mode_set, 1269 .mode_set_base = psb_intel_pipe_set_base, 1270 .prepare = psb_intel_crtc_prepare, 1271 .commit = psb_intel_crtc_commit, 1272}; 1273 1274const struct drm_crtc_funcs psb_intel_crtc_funcs = { 1275 .save = psb_intel_crtc_save, 1276 .restore = psb_intel_crtc_restore, 1277 .cursor_set = psb_intel_crtc_cursor_set, 1278 .cursor_move = psb_intel_crtc_cursor_move, 1279 .gamma_set = psb_intel_crtc_gamma_set, 1280 .set_config = psb_crtc_set_config, 1281 .destroy = psb_intel_crtc_destroy, 1282}; 1283 1284/* 1285 * Set the default value of cursor control and base register 1286 * to zero. This is a workaround for h/w defect on Oaktrail 1287 */ 1288static void psb_intel_cursor_init(struct drm_device *dev, int pipe) 1289{ 1290 u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR }; 1291 u32 base[3] = { CURABASE, CURBBASE, CURCBASE }; 1292 1293 REG_WRITE(control[pipe], 0); 1294 REG_WRITE(base[pipe], 0); 1295} 1296 1297void psb_intel_crtc_init(struct drm_device *dev, int pipe, 1298 struct psb_intel_mode_device *mode_dev) 1299{ 1300 struct drm_psb_private *dev_priv = dev->dev_private; 1301 struct psb_intel_crtc *psb_intel_crtc; 1302 int i; 1303 uint16_t *r_base, *g_base, *b_base; 1304 1305 /* We allocate a extra array of drm_connector pointers 1306 * for fbdev after the crtc */ 1307 psb_intel_crtc = 1308 kzalloc(sizeof(struct psb_intel_crtc) + 1309 (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), 1310 GFP_KERNEL); 1311 if (psb_intel_crtc == NULL) 1312 return; 1313 1314 psb_intel_crtc->crtc_state = 1315 kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL); 1316 if (!psb_intel_crtc->crtc_state) { 1317 dev_err(dev->dev, "Crtc state error: No memory\n"); 1318 kfree(psb_intel_crtc); 1319 return; 1320 } 1321 1322 /* Set the CRTC operations from the chip specific data */ 1323 drm_crtc_init(dev, &psb_intel_crtc->base, dev_priv->ops->crtc_funcs); 1324 1325 drm_mode_crtc_set_gamma_size(&psb_intel_crtc->base, 256); 1326 psb_intel_crtc->pipe = pipe; 1327 psb_intel_crtc->plane = pipe; 1328 1329 r_base = psb_intel_crtc->base.gamma_store; 1330 g_base = r_base + 256; 1331 b_base = g_base + 256; 1332 for (i = 0; i < 256; i++) { 1333 psb_intel_crtc->lut_r[i] = i; 1334 psb_intel_crtc->lut_g[i] = i; 1335 psb_intel_crtc->lut_b[i] = i; 1336 r_base[i] = i << 8; 1337 g_base[i] = i << 8; 1338 b_base[i] = i << 8; 1339 1340 psb_intel_crtc->lut_adj[i] = 0; 1341 } 1342 1343 psb_intel_crtc->mode_dev = mode_dev; 1344 psb_intel_crtc->cursor_addr = 0; 1345 1346 drm_crtc_helper_add(&psb_intel_crtc->base, 1347 dev_priv->ops->crtc_helper); 1348 1349 /* Setup the array of drm_connector pointer array */ 1350 psb_intel_crtc->mode_set.crtc = &psb_intel_crtc->base; 1351 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || 1352 dev_priv->plane_to_crtc_mapping[psb_intel_crtc->plane] != NULL); 1353 dev_priv->plane_to_crtc_mapping[psb_intel_crtc->plane] = 1354 &psb_intel_crtc->base; 1355 dev_priv->pipe_to_crtc_mapping[psb_intel_crtc->pipe] = 1356 &psb_intel_crtc->base; 1357 psb_intel_crtc->mode_set.connectors = 1358 (struct drm_connector **) (psb_intel_crtc + 1); 1359 psb_intel_crtc->mode_set.num_connectors = 0; 1360 psb_intel_cursor_init(dev, pipe); 1361} 1362 1363int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 1364 struct drm_file *file_priv) 1365{ 1366 struct drm_psb_private *dev_priv = dev->dev_private; 1367 struct drm_psb_get_pipe_from_crtc_id_arg *pipe_from_crtc_id = data; 1368 struct drm_mode_object *drmmode_obj; 1369 struct psb_intel_crtc *crtc; 1370 1371 if (!dev_priv) { 1372 dev_err(dev->dev, "called with no initialization\n"); 1373 return -EINVAL; 1374 } 1375 1376 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, 1377 DRM_MODE_OBJECT_CRTC); 1378 1379 if (!drmmode_obj) { 1380 dev_err(dev->dev, "no such CRTC id\n"); 1381 return -EINVAL; 1382 } 1383 1384 crtc = to_psb_intel_crtc(obj_to_crtc(drmmode_obj)); 1385 pipe_from_crtc_id->pipe = crtc->pipe; 1386 1387 return 0; 1388} 1389 1390struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, int pipe) 1391{ 1392 struct drm_crtc *crtc = NULL; 1393 1394 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1395 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 1396 if (psb_intel_crtc->pipe == pipe) 1397 break; 1398 } 1399 return crtc; 1400} 1401 1402int psb_intel_connector_clones(struct drm_device *dev, int type_mask) 1403{ 1404 int index_mask = 0; 1405 struct drm_connector *connector; 1406 int entry = 0; 1407 1408 list_for_each_entry(connector, &dev->mode_config.connector_list, 1409 head) { 1410 struct psb_intel_encoder *psb_intel_encoder = 1411 psb_intel_attached_encoder(connector); 1412 if (type_mask & (1 << psb_intel_encoder->type)) 1413 index_mask |= (1 << entry); 1414 entry++; 1415 } 1416 return index_mask; 1417} 1418 1419/* current intel driver doesn't take advantage of encoders 1420 always give back the encoder for the connector 1421*/ 1422struct drm_encoder *psb_intel_best_encoder(struct drm_connector *connector) 1423{ 1424 struct psb_intel_encoder *psb_intel_encoder = 1425 psb_intel_attached_encoder(connector); 1426 1427 return &psb_intel_encoder->base; 1428} 1429 1430void psb_intel_connector_attach_encoder(struct psb_intel_connector *connector, 1431 struct psb_intel_encoder *encoder) 1432{ 1433 connector->encoder = encoder; 1434 drm_mode_connector_attach_encoder(&connector->base, 1435 &encoder->base); 1436} 1437