Searched refs:hsync_end (Results 1 - 25 of 41) sorted by relevance

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/drivers/gpu/drm/gma500/
H A Dmdfld_tpo_vid.c47 mode->hsync_end = mode->hsync_start +
65 dev_dbg(dev->dev, "HSE is %d\n", mode->hsync_end);
75 mode->hsync_end = 876;
H A Dmdfld_tmd_vid.c50 mode->hsync_end = mode->hsync_start + \
68 dev_dbg(dev->dev, "HSE is %d\n", mode->hsync_end);
78 mode->hsync_end = 490;
H A Dintel_bios.c62 panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start +
79 if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal)
80 panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1;
H A Dmdfld_dsi_dpi.c437 pclk_hsync = mode->hsync_end - mode->hsync_start;
438 pclk_hbp = mode->htotal - mode->hsync_end;
698 adjusted_mode->hsync_end = fixed_mode->hsync_end;
800 ((mode->hsync_end - 1) << 16) | (mode->hsync_start - 1));
H A Doaktrail_lvds.c270 mode->hsync_end = mode->hsync_start + \
288 printk(KERN_INFO "HSE is %d\n", mode->hsync_end);
H A Dcdv_intel_lvds.c302 adjusted_mode->hsync_end = panel_fixed_mode->hsync_end;
H A Dpsb_drv.c524 mode->hsync_end = umode->hsync_end;
H A Dpsb_intel_lvds.c423 adjusted_mode->hsync_end = panel_fixed_mode->hsync_end;
H A Dtc35876x-dsi-lvds.c591 mode->hsync_end = 1400;
601 dev_info(&dev->pdev->dev, "HSE = %d\n", mode->hsync_end);
/drivers/staging/omapdrm/
H A Domap_connector.c43 mode->hsync_end = mode->hsync_start + timings->hsw;
44 mode->htotal = mode->hsync_end + timings->hbp;
67 timings->hsw = mode->hsync_end - mode->hsync_start;
68 timings->hbp = mode->htotal - mode->hsync_end;
235 mode->hsync_end, mode->htotal,
302 mode->hsync_end, mode->htotal,
/drivers/gpu/drm/exynos/
H A Dexynos_drm_connector.c58 mode->hsync_end = mode->hsync_start + timing->hsync_len;
59 mode->htotal = mode->hsync_end + timing->left_margin;
89 timing->hsync_len = mode->hsync_end - mode->hsync_start;
90 timing->left_margin = mode->htotal - mode->hsync_end;
/drivers/gpu/drm/i915/
H A Dintel_tv.c357 int hsync_end, hblank_start, hblank_end, htotal; member in struct:tv_mode
425 .hsync_end = 64, .hblank_end = 124,
467 .hsync_end = 64, .hblank_end = 124,
510 .hsync_end = 64, .hblank_end = 124,
553 .hsync_end = 64, .hblank_end = 124,
596 .hsync_end = 64, .hblank_end = 128,
641 .hsync_end = 64, .hblank_end = 142,
683 .hsync_end = 64, .hblank_end = 122,
707 .hsync_end = 64, .hblank_end = 139,
731 .hsync_end
[all...]
H A Dintel_panel.c41 adjusted_mode->hsync_end = fixed_mode->hsync_end;
H A Dintel_bios.c84 panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start +
111 if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal)
112 panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1;
H A Dintel_dvo.c153 C(hsync_end);
H A Dintel_lvds.c810 scan->hsync_end == fixed_mode->hsync_end &&
/drivers/gpu/drm/
H A Ddrm_modes.c56 mode->hsync_end, mode->htotal,
219 drm_mode->hsync_end = drm_mode->hdisplay + hblank / 2;
220 drm_mode->hsync_start = drm_mode->hsync_end -
254 drm_mode->hsync_end = drm_mode->hdisplay + CVT_RB_H_BLANK / 2;
255 drm_mode->hsync_start = drm_mode->hsync_end - CVT_RB_H_SYNC;
444 drm_mode->hsync_end = drm_mode->hsync_start + hsync;
674 p->crtc_hsync_end = p->hsync_end;
787 mode1->hsync_end == mode2->hsync_end &&
H A Ddrm_edid.c729 mode->hsync_end = mode->hsync_end - 1;
868 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
877 if (mode->hsync_end > mode->htotal)
878 mode->htotal = mode->hsync_end + 1;
915 (mode->hsync_end - mode->hdisplay == 80) &&
916 (mode->hsync_end - mode->hsync_start == 32) &&
/drivers/gpu/drm/radeon/
H A Dradeon_encoders.c271 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
284 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
/drivers/video/
H A Dgbefb.c534 timing->hsync_end = timing->hsync_start + var->hsync_len;
570 SET_GBE_FIELD(VT_HSYNC, HSYNC_OFF, val, timing->hsync_end);
997 var->left_margin = timing.htotal - timing.hsync_end;
1001 var->hsync_len = timing.hsync_end - timing.hsync_start;
H A Dsgivwfb.c343 var->left_margin = timing->htotal - timing->hsync_end;
347 var->hsync_len = timing->hsync_end - timing->hsync_start;
536 currentTiming->hsync_end);
/drivers/video/vermilion/
H A Dvermilion.c784 u32 htotal, hactive, hblank_start, hblank_end, hsync_start, hsync_end; local
802 hsync_end = hsync_start + var->hsync_len;
850 ((hsync_end - 1) << 16) | (hsync_start - 1));
/drivers/video/intelfb/
H A Dintelfbhw.c1050 u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive; local
1178 hsync_end = hsync_start + var->hsync_len;
1179 htotal = hsync_end + var->left_margin;
1184 hactive, hsync_start, hsync_end, htotal, hblank_start,
1208 hsync_end--;
1209 if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1243 *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
/drivers/gpu/drm/nouveau/
H A Dnv17_tv.c271 mode->hsync_end = mode->hsync_start + 8;
531 regs->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
H A Dnv50_crtc.c655 hsynce = mode->hsync_end - mode->hsync_start - 1;
656 hbackp = mode->htotal - mode->hsync_end;

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