Searched refs:htotal (Results 1 - 25 of 68) sorted by relevance

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/drivers/gpu/drm/gma500/
H A Dmdfld_tpo_vid.c50 mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) |
66 dev_dbg(dev->dev, "htotal is %d\n", mode->htotal);
76 mode->htotal = 887;
H A Dmdfld_tmd_vid.c53 mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) | \
69 dev_dbg(dev->dev, "htotal is %d\n", mode->htotal);
79 mode->htotal = 499;
H A Dintel_bios.c64 panel_fixed_mode->htotal = panel_fixed_mode->hdisplay +
79 if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal)
80 panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1;
156 if (panel_fixed_mode->htotal > 0 && panel_fixed_mode->vtotal > 0) {
H A Dmdfld_dsi_dpi.c438 pclk_hbp = mode->htotal - mode->hsync_end;
505 (mode->vtotal * mode->htotal * dsi_config->bpp /
699 adjusted_mode->htotal = fixed_mode->htotal;
797 REG_WRITE(HTOTAL_A, ((mode->htotal - 1) << 16) | (mode->hdisplay - 1));
798 REG_WRITE(HBLANK_A, ((mode->htotal - 1) << 16) | (mode->hdisplay - 1));
/drivers/video/geode/
H A Ddisplay_gx.c65 int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal; local
138 htotal = hblankend;
148 ((htotal - 1) << 16));
H A Ddisplay_gx1.c85 int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal; local
156 htotal = hblankend;
165 val = (hactive - 1) | ((htotal - 1) << 16);
/drivers/video/
H A Dfbcvt.c44 u32 htotal; member in struct:fb_cvt_data
132 hsync = (FB_CVT_CELLSIZE * cvt->htotal)/100;
177 pixclock = (cvt->f_refresh * cvt->vtotal * cvt->htotal)/1000;
179 pixclock = (cvt->htotal * 1000000)/cvt->hperiod;
365 cvt.htotal = cvt.active_pixels + cvt.hblank;
368 cvt.hfreq = cvt.pixclock/cvt.htotal;
H A Dfbmon.c706 int vtotal, htotal; local
718 htotal = mode->xres + mode->right_margin + mode->hsync_len
729 hscan = (pixclock + htotal / 2) / htotal;
1090 u32 htotal; member in struct:__fb_timings
1129 * duty cycle = percent of htotal assigned to inactive display
1162 * duty cycle = percent of htotal assigned to inactive display
1222 timings->htotal = timings->hactive + timings->hblank;
1223 timings->dclk = timings->htotal * timings->hfreq;
1233 timings->htotal
1412 u32 hfreq, vfreq, htotal, vtotal, pixclock; local
[all...]
H A Damifb.c154 - htotal: Last value on the line (i.e. line length = htotal + 1)
221 be 1 more than htotal.
755 u_short htotal; /* vmode */ member in struct:amifb_par
978 * htotal 8 2048 8
1018 /* hsstrt/hsstop/htotal/vsstrt/vsstop/vtotal/hcenter (sync timings) */
1022 #define htotal2hw(htotal) (div8(htotal) - 1)
1026 #define hcenter2hw(htotal) (div8(htotal))
1128 u_int htotal, vtotal; local
[all...]
H A Dgbefb.c524 timing->htotal = var->left_margin + var->xres +
528 timing->fields_sec = 1000 * timing->cfreq / timing->htotal *
532 timing->hblank_end = timing->htotal;
559 SET_GBE_FIELD(VT_XYMAX, MAXX, val, timing->htotal);
607 timing->htotal - (20 - timing->hblank_end));
617 timing->htotal - (GBE_CRS_MAGIC -
629 temp += timing->htotal; /* allow blank to wrap around */
634 GBE_PIXEN_MAGIC_OFF) % timing->htotal));
997 var->left_margin = timing.htotal - timing.hsync_end;
H A Dsgivwfb.c343 var->left_margin = timing->htotal - timing->hsync_end;
577 currentTiming->htotal - (20 -
590 currentTiming->htotal - (DBE_CRS_MAGIC -
617 SET_DBE_FIELD(VT_XYMAX, VT_MAXX, outputVal, currentTiming->htotal);
651 htmp += currentTiming->htotal; /* allow blank to wrap around */
655 2) % currentTiming->htotal));
H A Dcirrusfb.c689 int hdispend, hsyncstart, hsyncend, htotal; local
724 htotal = (hsyncend + var->left_margin) / 8;
759 htotal /= 2;
765 htotal -= 5;
774 dev_dbg(info->device, "CRT0: %d\n", htotal);
775 vga_wcrt(regbase, VGA_CRTC_H_TOTAL, htotal);
784 dev_dbg(info->device, "CRT3: 128+%d\n", (htotal + 5) % 32);
786 128 + ((htotal + 5) % 32));
792 if ((htotal + 5) & 32)
847 if ((htotal
[all...]
H A Dsh_mobile_hdmi.c295 u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset; local
298 htotal = mode->xres + mode->right_margin + mode->left_margin
325 htotal, hblank, hdelay, mode->hsync_len,
330 hdmi_write(hdmi, htotal, HDMI_EXTERNAL_H_TOTAL_7_0);
331 hdmi_write(hdmi, htotal >> 8, HDMI_EXTERNAL_H_TOTAL_11_8);
/drivers/gpu/drm/
H A Ddrm_modes.c56 mode->hsync_end, mode->htotal,
218 drm_mode->htotal = drm_mode->hdisplay + hblank;
221 (drm_mode->htotal * CVT_HSYNC_PERCENTAGE) / 100;
252 drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK;
261 drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod;
445 drm_mode->htotal = total_pixels;
604 if (mode->htotal < 0)
607 calc_val = (mode->clock * 1000) / mode->htotal; /* hsync in Hz */
638 else if (mode->htotal > 0 && mode->vtotal > 0) {
643 calc_val /= mode->htotal;
[all...]
/drivers/staging/omapdrm/
H A Domap_connector.c44 mode->htotal = mode->hsync_end + timings->hbp;
68 timings->hbp = mode->htotal - mode->hsync_end;
235 mode->hsync_end, mode->htotal,
302 mode->hsync_end, mode->htotal,
/drivers/video/sis/
H A Dinitextlfb.c40 int *htotal, int *vtotal, unsigned char rateindex);
177 sisfb_gettotalfrommode(struct SiS_Private *SiS_Pr, unsigned char modeno, int *htotal, argument
214 *htotal = (((cr_data & 0xff) | ((unsigned short) (sr_data & 0x03) << 8)) + 5) * 8;
/drivers/video/matrox/
H A Dmatroxfb_maven.c211 unsigned int htotal, unsigned int vtotal,
224 scrlen = htotal * (vtotal - 1);
225 fwant = htotal * vtotal;
229 fwant, fxtal, htotal, vtotal, fmax);
262 if (ln > htotal)
284 unsigned int htotal, unsigned int vtotal,
290 fvco = matroxfb_PLL_mavenclock(&maven1000_pll, ctl, htotal, vtotal, in, feed, &p, htotal2);
733 m->htotal = h - 2;
785 /* htotal - 2 */
786 m->regs[0xA0] = m->htotal;
209 matroxfb_PLL_mavenclock(const struct matrox_pll_features2* pll, const struct matrox_pll_ctl* ctl, unsigned int htotal, unsigned int vtotal, unsigned int* in, unsigned int* feed, unsigned int* post, unsigned int* h2) argument
283 matroxfb_mavenclock(const struct matrox_pll_ctl *ctl, unsigned int htotal, unsigned int vtotal, unsigned int* in, unsigned int* feed, unsigned int* post, unsigned int* htotal2) argument
[all...]
/drivers/gpu/drm/i915/
H A Dintel_tv.c357 int hsync_end, hblank_start, hblank_end, htotal; member in struct:tv_mode
426 .hblank_start = 836, .htotal = 857,
468 .hblank_start = 836, .htotal = 857,
511 .hblank_start = 836, .htotal = 857,
554 .hblank_start = 836, .htotal = 857,
597 .hblank_start = 844, .htotal = 863,
642 .hblank_start = 844, .htotal = 863,
684 .hblank_start = 842, .htotal = 857,
708 .hblank_start = 859, .htotal = 863,
732 .hblank_start = 1580, .htotal
[all...]
H A Dintel_panel.c42 adjusted_mode->htotal = fixed_mode->htotal;
H A Dintel_bios.c86 panel_fixed_mode->htotal = panel_fixed_mode->hdisplay +
111 if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal)
112 panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1;
/drivers/gpu/drm/exynos/
H A Dexynos_drm_connector.c59 mode->htotal = mode->hsync_end + timing->left_margin;
90 timing->left_margin = mode->htotal - mode->hsync_end;
/drivers/gpu/drm/radeon/
H A Dradeon_encoders.c267 unsigned hblank = native_mode->htotal - native_mode->hdisplay;
282 adjusted_mode->htotal = native_mode->hdisplay + hblank;
/drivers/video/vermilion/
H A Dvermilion.c784 u32 htotal, hactive, hblank_start, hblank_end, hsync_start, hsync_end; local
796 htotal =
800 hblank_end = htotal;
821 ": Set mode Hfreq : %d kHz, Vfreq : %d Hz.\n", clock / htotal,
822 ((clock / htotal) * 1000) / vtotal);
846 VML_WRITE32(par, VML_HTOTAL_A, ((htotal - 1) << 16) | (hactive - 1));
/drivers/gpu/drm/nouveau/
H A Dnv17_tv.c209 mode->htotal / 1000 *
268 mode->htotal = output_mode->htotal;
269 mode->hsync_start = (mode->hdisplay + (mode->htotal
528 regs->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
/drivers/gpu/drm/i2c/
H A Dch7006_mode.c115 .htotal = ht, \
188 mode->mode.htotal != drm_mode->htotal ||

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