Searched refs:hw_addr (Results 1 - 25 of 52) sorted by relevance

123

/drivers/net/ethernet/intel/ixgb/
H A Dixgb_osdep.h49 writel((value), ((a)->hw_addr + IXGB_##reg)))
52 readl((a)->hw_addr + IXGB_##reg))
55 writel((value), ((a)->hw_addr + IXGB_##reg + ((offset) << 2))))
58 readl((a)->hw_addr + IXGB_##reg + ((offset) << 2)))
/drivers/net/ethernet/intel/e1000/
H A De1000_osdep.h55 (readl(hw->hw_addr + ((hw->mac_type >= e1000_82543) \
59 (writel((value), (hw->hw_addr + ((hw->mac_type >= e1000_82543) \
63 writel((value), ((a)->hw_addr + \
68 readl((a)->hw_addr + \
76 writew((value), ((a)->hw_addr + \
81 readw((a)->hw_addr + \
86 writeb((value), ((a)->hw_addr + \
91 readb((a)->hw_addr + \
H A De1000_main.c997 hw->hw_addr = pci_ioremap_bar(pdev, BAR_0);
998 if (!hw->hw_addr)
1256 iounmap(hw->hw_addr);
1294 iounmap(hw->hw_addr);
2012 writel(0, hw->hw_addr + tx_ring->tdh);
2013 writel(0, hw->hw_addr + tx_ring->tdt);
2124 writel(0, hw->hw_addr + rx_ring->rdh);
2125 writel(0, hw->hw_addr + rx_ring->rdt);
3035 writel(i, hw->hw_addr + tx_ring->tdt);
3453 readl(adapter->hw.hw_addr
[all...]
/drivers/net/ethernet/atheros/atlx/
H A Datlx.c136 rctl = ioread32(hw->hw_addr + REG_MAC_CTRL);
145 iowrite32(rctl, hw->hw_addr + REG_MAC_CTRL);
148 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
149 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
164 iowrite32(IMR_NORMAL_MASK, adapter->hw.hw_addr + REG_IMR);
165 ioread32(adapter->hw.hw_addr + REG_IMR);
174 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
175 ioread32(adapter->hw.hw_addr + REG_IMR);
235 ctrl = ioread32(adapter->hw.hw_addr + REG_MAC_CTRL);
237 iowrite32(ctrl, adapter->hw.hw_addr
[all...]
H A Datl2.h52 ((a)->hw_addr + (reg))))
54 #define ATL2_WRITE_FLUSH(a) (ioread32((a)->hw_addr))
56 #define ATL2_READ_REG(a, reg) (ioread32((a)->hw_addr + (reg)))
59 ((a)->hw_addr + (reg))))
61 #define ATL2_READ_REGB(a, reg) (ioread8((a)->hw_addr + (reg)))
64 ((a)->hw_addr + (reg))))
66 #define ATL2_READ_REGW(a, reg) (ioread16((a)->hw_addr + (reg)))
69 (iowrite32((value), (((a)->hw_addr + (reg)) + ((offset) << 2))))
72 (ioread32(((a)->hw_addr + (reg)) + ((offset) << 2)))
383 u8 __iomem *hw_addr; member in struct:atl2_hw
[all...]
H A Datl1.c269 * iowrite32(0, hw->hw_addr + REG_IMR);
270 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
279 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
280 ioread32(hw->hw_addr + REG_MASTER_CTRL);
282 iowrite16(1, hw->hw_addr + REG_PHY_ENABLE);
283 ioread16(hw->hw_addr + REG_PHY_ENABLE);
290 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
316 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
319 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
322 value = ioread16(hw->hw_addr
[all...]
/drivers/net/ethernet/intel/ixgbevf/
H A Dregs.h73 #define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
75 #define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg))
78 writel((value), ((a)->hw_addr + (reg) + ((offset) << 2))))
81 readl((a)->hw_addr + (reg) + ((offset) << 2)))
H A Dethtool.c531 before = readl(adapter->hw.hw_addr + R); \
533 (adapter->hw.hw_addr + R)); \
534 val = readl(adapter->hw.hw_addr + R); \
541 writel(before, adapter->hw.hw_addr + R); \
544 writel(before, adapter->hw.hw_addr + R); \
551 before = readl(adapter->hw.hw_addr + R); \
552 writel((W & M), (adapter->hw.hw_addr + R)); \
553 val = readl(adapter->hw.hw_addr + R); \
558 writel(before, (adapter->hw.hw_addr + R)); \
561 writel(before, (adapter->hw.hw_addr
[all...]
H A Dvf.h128 u8 __iomem *hw_addr; member in struct:ixgbe_hw
/drivers/net/ethernet/atheros/atl1c/
H A Datl1c.h385 u8 __iomem *hw_addr; /* inner register address */ member in struct:atl1c_hw
598 writel((value), ((a)->hw_addr + reg)))
601 readl((a)->hw_addr))
605 readl((a)->hw_addr + reg); \
606 *(u32 *)pdata = readl((a)->hw_addr + reg); \
608 *(u32 *)pdata = readl((a)->hw_addr + reg); \
613 writeb((value), ((a)->hw_addr + reg)))
616 readb((a)->hw_addr + reg))
619 writew((value), ((a)->hw_addr + reg)))
622 readw((a)->hw_addr
[all...]
/drivers/net/ethernet/intel/igbvf/
H A Dregs.h100 #define er32(reg) readl(hw->hw_addr + E1000_##reg)
101 #define ew32(reg, val) writel((val), hw->hw_addr + E1000_##reg)
103 readl(hw->hw_addr + E1000_##reg + (offset << 2))
105 writel((val), hw->hw_addr + E1000_##reg + (offset << 2))
H A Dvf.h242 u8 __iomem *hw_addr; member in struct:e1000_hw
H A Dnetdev.c232 writel(i, adapter->hw.hw_addr + rx_ring->tail);
519 writel(0, adapter->hw.hw_addr + tx_ring->head);
520 writel(0, adapter->hw.hw_addr + tx_ring->tail);
602 writel(0, adapter->hw.hw_addr + rx_ring->head);
603 writel(0, adapter->hw.hw_addr + rx_ring->tail);
866 adapter->hw.hw_addr + tx_ring->itr_register);
896 adapter->hw.hw_addr + adapter->rx_ring->itr_register);
971 writel(tx_ring->itr_val, hw->hw_addr + tx_ring->itr_register);
974 writel(rx_ring->itr_val, hw->hw_addr + rx_ring->itr_register);
2175 writel(i, adapter->hw.hw_addr
[all...]
/drivers/net/ethernet/micrel/
H A Dks8842.c163 void __iomem *hw_addr; member in struct:ks8842_adapter
180 iowrite32(1, adapter->hw_addr + REQ_TIMB_DMA_RESUME);
185 iowrite16(bank, adapter->hw_addr + REG_SELECT_BANK);
192 iowrite8(value, adapter->hw_addr + offset);
199 iowrite16(value, adapter->hw_addr + offset);
207 reg = ioread16(adapter->hw_addr + offset);
209 iowrite16(reg, adapter->hw_addr + offset);
217 reg = ioread16(adapter->hw_addr + offset);
219 iowrite16(reg, adapter->hw_addr + offset);
226 iowrite32(value, adapter->hw_addr
[all...]
H A Dks8851_mll.c386 * @hw_addr : start address of data register.
432 void __iomem *hw_addr; member in struct:ks_net
490 data = ioread16(ks->hw_addr);
506 return ioread16(ks->hw_addr);
522 iowrite16(value_write, ks->hw_addr);
537 iowrite16(value, ks->hw_addr);
551 *wptr++ = (u16)ioread16(ks->hw_addr);
565 iowrite16(*wptr++, ks->hw_addr);
759 ioread8(ks->hw_addr);
1536 ks->hw_addr
[all...]
/drivers/gpu/drm/via/
H A Dvia_dma.c86 uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base; local
88 return ((hw_addr <= dev_priv->dma_low) ?
89 (dev_priv->dma_high + hw_addr - dev_priv->dma_low) :
90 (hw_addr - dev_priv->dma_low));
100 uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base; local
102 return ((hw_addr <= dev_priv->dma_low) ?
103 (dev_priv->dma_low - hw_addr) :
104 (dev_priv->dma_wrap + dev_priv->dma_low - hw_addr));
115 uint32_t cur_addr, hw_addr, next_addr; local
123 hw_addr
[all...]
/drivers/net/ethernet/atheros/atl1e/
H A Datl1e.h316 u8 __iomem *hw_addr; /* inner register address */ member in struct:atl1e_hw
474 writel((value), ((a)->hw_addr + reg)))
477 readl((a)->hw_addr))
480 readl((a)->hw_addr + reg))
483 writeb((value), ((a)->hw_addr + reg)))
486 readb((a)->hw_addr + reg))
489 writew((value), ((a)->hw_addr + reg)))
492 readw((a)->hw_addr + reg))
495 writel((value), (((a)->hw_addr + reg) + ((offset) << 2))))
498 readl(((a)->hw_addr
[all...]
/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_common.h110 #define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
117 #define IXGBE_WRITE_REG64(a, reg, value) writeq((value), ((a)->hw_addr + (reg)))
119 #define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg))
122 writel((value), ((a)->hw_addr + (reg) + ((offset) << 2))))
125 readl((a)->hw_addr + (reg) + ((offset) << 2)))
/drivers/net/ethernet/chelsio/cxgb4vf/
H A Dadapter.h460 * @hw_addr: the Ethernet address
466 u8 hw_addr[])
468 memcpy(adapter->port[pidx]->dev_addr, hw_addr, ETH_ALEN);
469 memcpy(adapter->port[pidx]->perm_addr, hw_addr, ETH_ALEN);
465 t4_os_set_hw_addr(struct adapter *adapter, int pidx, u8 hw_addr[]) argument
/drivers/net/ethernet/intel/igb/
H A De1000_regs.h330 #define wr32(reg, value) (writel(value, hw->hw_addr + reg))
331 #define rd32(reg) (readl(hw->hw_addr + reg))
335 (writel(value, hw->hw_addr + reg + ((offset) << 2)))
337 (readl(hw->hw_addr + reg + ((offset) << 2)))
/drivers/net/ethernet/ti/
H A Ddavinci_cpdma.c79 u32 hw_addr; member in struct:cpdma_desc_pool
141 cpdma_desc_pool_create(struct device *dev, u32 phys, u32 hw_addr, argument
166 pool->hw_addr = hw_addr;
171 pool->hw_addr = pool->phys;
208 return pool->hw_addr + (__force dma_addr_t)desc -
215 return dma ? pool->iomap + dma - pool->hw_addr : NULL;
/drivers/net/wireless/ath/ath6kl/
H A Dmain.c1120 if (memcmp(ha->addr, mc_filter->hw_addr,
1134 mc_filter->hw_addr);
1136 vif->fw_vif_idx, mc_filter->hw_addr,
1140 mc_filter->hw_addr);
1154 if (memcmp(ha->addr, mc_filter->hw_addr,
1169 memcpy(mc_filter->hw_addr, ha->addr,
1174 mc_filter->hw_addr);
1176 vif->fw_vif_idx, mc_filter->hw_addr,
1180 mc_filter->hw_addr);
/drivers/net/ethernet/i825xx/
H A Deexpress.c1065 unsigned short hw_addr[3]; local
1079 hw_addr[0] = eexp_hw_readeeprom(ioaddr,2);
1080 hw_addr[1] = eexp_hw_readeeprom(ioaddr,3);
1081 hw_addr[2] = eexp_hw_readeeprom(ioaddr,4);
1084 if (!((hw_addr[2]==0x00aa && ((hw_addr[1] & 0xff00)==0x0000)) ||
1085 (hw_addr[2]==0x0080 && ((hw_addr[1] & 0xff00)==0x5F00))))
1088 hw_addr[2],hw_addr[
[all...]
/drivers/net/usb/
H A Dkaweth.c205 eth_addr_t hw_addr; member in struct:kaweth_ethernet_configuration
1101 dev_info(&intf->dev, "Read MAC address %pM\n", kaweth->configuration.hw_addr);
1103 if(!memcmp(&kaweth->configuration.hw_addr,
1158 memcpy(netdev->dev_addr, &kaweth->configuration.hw_addr,
1159 sizeof(kaweth->configuration.hw_addr));
/drivers/net/ethernet/chelsio/cxgb/
H A Dsubr.c1089 u8 hw_addr[6]; local
1113 mac->ops->macaddress_get(mac, hw_addr);
1114 else if (vpd_macaddress_get(adapter, i, hw_addr)) {
1119 memcpy(adapter->port[i].dev->dev_addr, hw_addr, ETH_ALEN);

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