Searched refs:mclk (Results 1 - 25 of 66) sorted by relevance

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/drivers/staging/iio/dds/
H A Dad9834.h43 * @mclk: external master clock
56 unsigned int mclk; member in struct:ad9834_state
79 * @mclk: master clock in Hz
92 unsigned int mclk; member in struct:ad9834_platform_data
H A Dad9832.h62 * @mclk: external master clock
80 unsigned long mclk; member in struct:ad9832_state
107 * @mclk: master clock in Hz
117 unsigned long mclk; member in struct:ad9832_platform_data
H A Dad9832.c25 static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout) argument
29 do_div(freqreg, mclk);
38 if (fout > (st->mclk / 2))
41 regval = ad9832_calc_freqreg(st->mclk, fout);
232 st->mclk = pdata->mclk;
H A Dad9834.c28 static unsigned int ad9834_calc_freqreg(unsigned long mclk, unsigned long fout) argument
31 do_div(freqreg, mclk);
40 if (fout > (st->mclk / 2))
43 regval = ad9834_calc_freqreg(st->mclk, fout);
344 st->mclk = pdata->mclk;
/drivers/media/dvb/frontends/
H A Dstv6110.h43 u32 mclk; member in struct:stv6110_config
H A Dstv0900_sw.c56 max_carrier /= intp->mclk / 1000;
83 max_carrier /= intp->mclk / 1000;
89 freq_inc /= intp->mclk >> 10;
149 max_carrier /= intp->mclk / 1000;
309 u32 mclk,
324 intval1 = (mclk) >> 16;
327 rem1 = (mclk) % 0x10000;
337 u32 mclk, u32 srate,
342 dprintk("%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk,
347 symb /= (mclk >> 1
308 stv0900_get_symbol_rate(struct stv0900_internal *intp, u32 mclk, enum fe_stv0900_demod_num demod) argument
336 stv0900_set_symbol_rate(struct stv0900_internal *intp, u32 mclk, u32 srate, enum fe_stv0900_demod_num demod) argument
360 stv0900_set_max_symbol_rate(struct stv0900_internal *intp, u32 mclk, u32 srate, enum fe_stv0900_demod_num demod) argument
388 stv0900_set_min_symbol_rate(struct stv0900_internal *intp, u32 mclk, u32 srate, enum fe_stv0900_demod_num demod) argument
1141 stv0900_get_carr_freq(struct stv0900_internal *intp, u32 mclk, enum fe_stv0900_demod_num demod) argument
[all...]
H A Dstv6110.c39 u32 mclk; member in struct:stv6110_priv
215 ((((priv->mclk / 1000000) - 16) & 0x1f) << 3);
244 freq = divider * (priv->mclk / 1000);
262 dprintk("%s, freq=%d kHz, mclk=%d Hz\n", __func__,
263 frequency, priv->mclk);
268 ((((priv->mclk / 1000000) - 16) & 0x1f) << 3);
304 p_calc = (priv->mclk / 100000);
309 p_calc_opt = (priv->mclk / 100000);
313 ref = priv->mclk / ((1 << (r_div_opt + 1)) * (1 << (p + 1)));
343 vco_freq = divider * ((priv->mclk / 100
[all...]
H A Dstv0299.h71 u32 mclk; member in struct:stv0299_config
H A Dbsbe1.h99 .mclk = 88000000UL,
H A Dbsru6.h134 .mclk = 88000000UL,
H A Dstb0899_algo.c218 derot_limit = (internal->sub_range / 2L) / internal->mclk;
219 derot_step = (params->srate / 2L) / internal->mclk;
287 derot_limit = (internal->sub_range / 2L) / internal->mclk;
295 dprintk(state->verbose, FE_DEBUG, 1, "Derot Freq=%d, mclk=%d", derot_freq, internal->mclk);
398 derot_step = (params->srate / 4L) / internal->mclk;
399 derot_limit = (internal->sub_range / 2L) / internal->mclk;
410 dprintk(state->verbose, FE_DEBUG, 1, "Derot freq=%d, mclk=%d", derot_freq, internal->mclk);
447 tp_freq = internal->freq + (internal->derot_freq * internal->mclk) / 100
[all...]
H A Dstv090x.c861 sym /= (state->internal->mclk >> 12);
864 sym /= (state->internal->mclk >> 10);
867 sym /= (state->internal->mclk >> 7);
888 sym /= (state->internal->mclk >> 12);
891 sym /= (state->internal->mclk >> 10);
894 sym /= (state->internal->mclk >> 7);
922 sym /= (state->internal->mclk >> 12);
925 sym /= (state->internal->mclk >> 10);
928 sym /= (state->internal->mclk >> 7);
1458 freq_abs /= (state->internal->mclk / 100
2529 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk) argument
4213 stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk) argument
[all...]
/drivers/mfd/
H A Dsm501.c392 unsigned long mclk; member in struct:sm501_clock
408 unsigned long mclk,
423 diff = DIV_ROUND_CLOSEST(mclk, divider << shift) - freq;
431 clock->mclk = mclk;
453 unsigned long mclk; local
464 mclk = (24000000UL * m / n) >> k;
467 mclk, &best_diff)) {
477 return clock->mclk / (clock->divider << clock->shift);
491 unsigned long mclk; local
405 sm501_calc_clock(unsigned long freq, struct sm501_clock *clock, int max_div, unsigned long mclk, long *best_diff) argument
[all...]
H A Dtwl6040-core.c273 twl6040->mclk = 32768;
297 twl6040->mclk = 0;
320 twl6040->mclk = 0;
379 if (twl6040->mclk != freq_in) {
437 twl6040->mclk = freq_in;
/drivers/staging/cxt1e1/
H A Dpmcc4_cpld.h40 volatile u_int32_t mclk;/* r/w: Master Clock Register */ member in struct:c4_cpld
/drivers/gpu/drm/nouveau/
H A Dnva3_pm.c235 struct creg mclk; member in struct:nva3_pm_state
258 ret = calc_clk(dev, 0x12, 0x4000, perflvl->memory, &info->mclk);
319 if (info->mclk.clk || info->mclk.pll) {
323 prog_pll(dev, 0x02, 0x004000, &info->mclk);
/drivers/mmc/host/
H A Dmmci.c153 if (desired >= host->mclk) {
157 host->cclk = host->mclk;
160 * DB8500 TRM says f = mclk / (clkdiv + 2)
161 * => clkdiv = (mclk / f) - 2
165 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
168 host->cclk = host->mclk / (clk + 2);
171 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
172 * => clkdiv = mclk / (2 * f) - 1
174 clk = host->mclk / (2 * desired) - 1;
177 host->cclk = host->mclk / (
[all...]
H A Dmmci.h180 unsigned int mclk; member in struct:mmci_host
/drivers/gpu/drm/radeon/
H A Dradeon_pm.c179 u32 sclk, mclk; local
192 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
193 clock_info[rdev->pm.requested_clock_mode_index].mclk;
194 if (mclk > rdev->pm.default_mclk)
195 mclk = rdev->pm.default_mclk;
224 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
226 radeon_set_memory_clock(rdev, mclk);
228 rdev->pm.current_mclk = mclk;
229 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
351 clock_info->mclk * 1
[all...]
/drivers/i2c/busses/
H A Di2c-sh7760.c389 * peripheral module clock (mclk, usually around 33MHz):
390 * iclk = mclk/(CDF + 1). iclk must be < 20MHz.
395 struct clk *mclk; local
400 mclk = clk_get(NULL, "peripheral_clk");
401 if (IS_ERR(mclk)) {
402 return PTR_ERR(mclk);
404 mck = mclk->rate;
405 clk_put(mclk);
/drivers/media/video/
H A Dpxa_camera.c215 unsigned long mclk; member in struct:pxa_camera_dev
861 unsigned long mclk = pcdev->mclk; local
869 /* mclk <= ciclk / 4 (27.4.2) */
870 if (mclk > lcdclk / 4) {
871 mclk = lcdclk / 4;
872 dev_warn(dev, "Limiting master clock to %lu\n", mclk);
875 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
876 div = (lcdclk + 2 * mclk - 1) / (2 * mclk)
[all...]
H A Dmx1_camera.c117 unsigned long mclk; member in struct:mx1_camera_dev
390 unsigned int mclk = pcdev->mclk; local
400 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
404 lcdclk / 1000, mclk / 1000, div);
750 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
752 if (!pcdev->mclk) {
756 pcdev->mclk = 20000000;
/drivers/media/video/davinci/
H A Ddm644x_ccdc.c64 struct clk *mclk; member in struct:ccdc_oper_config
992 ccdc_cfg.mclk = clk_get(&pdev->dev, "master");
993 if (IS_ERR(ccdc_cfg.mclk)) {
994 status = PTR_ERR(ccdc_cfg.mclk);
997 if (clk_enable(ccdc_cfg.mclk)) {
1018 clk_put(ccdc_cfg.mclk);
1032 clk_put(ccdc_cfg.mclk);
1049 clk_disable(ccdc_cfg.mclk);
1058 clk_enable(ccdc_cfg.mclk);
H A Ddm355_ccdc.c63 struct clk *mclk; member in struct:ccdc_oper_config
1001 ccdc_cfg.mclk = clk_get(&pdev->dev, "master");
1002 if (IS_ERR(ccdc_cfg.mclk)) {
1003 status = PTR_ERR(ccdc_cfg.mclk);
1006 if (clk_enable(ccdc_cfg.mclk)) {
1039 clk_put(ccdc_cfg.mclk);
1053 clk_put(ccdc_cfg.mclk);
/drivers/spi/
H A Dspi-mpc512x-psc.c43 u32 mclk; member in struct:mpc512x_psc_spi
108 bclkdiv = (mps->mclk / cs->speed_hz) - 1;
110 bclkdiv = (mps->mclk / 1000000) - 1; /* default 1MHz */
340 mps->mclk = clk_get_rate(spiclk);
369 bclkdiv = (mps->mclk / 1000000) - 1; /* default 1MHz */

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