Searched refs:mw32 (Results 1 - 4 of 4) sorted by relevance

/drivers/scsi/mvsas/
H A Dmv_94xx.c268 mw32(MVS_PCS, tmp);
347 mw32(MVS_PHY_CTL, tmp);
364 mw32(MVS_PHY_CTL, tmp);
367 mw32(MVS_PHY_CTL, tmp);
372 mw32(MVS_PORTS_IMP, 0xFF);
375 mw32(MVS_PA_VSR_ADDR, CMD_CMWK_OOB_DET);
376 mw32(MVS_PA_VSR_PORT, 0x00018080);
378 mw32(MVS_PA_VSR_ADDR, VSR_PHY_MODE2);
381 mw32(MVS_PA_VSR_PORT, 0x0084d4fe);
384 mw32(MVS_PA_VSR_POR
[all...]
H A Dmv_64xx.c54 mw32(MVS_PCS, tmp);
71 mw32(MVS_GBL_PORT_TYPE, 0);
114 mw32(MVS_PHY_CTL, tmp);
116 mw32(MVS_PHY_CTL, reg);
147 mw32(MVS_INT_STAT_SRS_0, tmp);
154 mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32));
166 mw32(MVS_GBL_CTL, 0);
185 mw32(MVS_GBL_CTL, 0);
227 mw32(MVS_PHY_CTL, tmp);
249 mw32(MVS_PHY_CT
[all...]
H A Dmv_chips.h31 #define mw32(reg, val) writel((val), regs + reg) macro
33 mw32(reg, val); \
47 mw32(MVS_CMD_ADDR, addr);
54 mw32(MVS_CMD_ADDR, addr);
55 mw32(MVS_CMD_DATA, val);
69 mw32(MVS_P0_SER_CTLSTAT + port * 4, val);
71 mw32(MVS_P4_SER_CTLSTAT + (port - 4) * 4, val);
193 mw32(MVS_INT_STAT_SRS_0, tmp);
218 mw32(MVS_INT_STAT, stat);
224 mw32(MVS_TX_PROD_ID
[all...]
H A Dmv_94xx.h283 (((i) > 31) ? mw32(MVS_STP_REG_SET_1, tmp) : \
284 mw32(MVS_STP_REG_SET_0, tmp))

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