Searched refs:outl (Results 1 - 25 of 135) sorted by relevance

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/drivers/staging/comedi/drivers/addi-data/
H A Dhwdrv_apci1032.c102 outl(ul_Command1,
104 outl(ul_Command2,
107 outl(0x4, devpriv->iobase + APCI1032_DIGITAL_IP_IRQ);
112 outl(0x6, devpriv->iobase + APCI1032_DIGITAL_IP_IRQ);
118 outl(ul_Command1,
120 outl(ul_Command2,
122 outl(0x0, devpriv->iobase + APCI1032_DIGITAL_IP_IRQ);
255 outl(ui_Temp & APCI1032_DIGITAL_IP_INTERRUPT_DISABLE,
261 outl(ui_Temp, devpriv->iobase + APCI1032_DIGITAL_IP_IRQ); /* enable the interrupt */
282 outl(
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H A Dhwdrv_apci035.c130 outl(ui_Command, devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 12);
136 outl(data[3], devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 4);
140 outl(data[2], devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 8);
176 outl(ui_Command, devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 12);
189 outl(ui_Command, devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 12);
202 outl(ui_Command, devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 12);
213 outl(ui_Command, devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 12);
218 outl(data[11],
223 outl(data[10],
237 outl(ui_Comman
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H A Dhwdrv_apci1564.c99 outl(data[2],
102 outl(data[3],
106 outl(0x4,
111 outl(0x6,
117 outl(0x0,
120 outl(0x0,
123 outl(0x0,
288 outl(ul_Command,
335 outl(data[0],
369 outl(dat
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H A Dhwdrv_apci3501.c178 outl(data[0], devpriv->iobase + APCI3501_DIGITAL_OP);
183 outl(data[0],
202 outl(data[0],
215 outl(data[0],
304 outl(data[0],
378 outl(ul_Command1,
422 outl(0x0, devpriv->iobase + APCI3501_WATCHDOG + APCI3501_TCW_PROG); /* disable Wa */
426 outl(0x02,
430 outl(0x0, devpriv->iobase + APCI3501_WATCHDOG + APCI3501_TCW_PROG); /* disable Timer interrupt */
434 outl(dat
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H A Dhwdrv_apci2032.c112 outl(ul_Command, devpriv->iobase + APCI2032_DIGITAL_OP_INTERRUPT);
152 outl(data[0], devpriv->iobase + APCI2032_DIGITAL_OP);
191 outl(data[0],
210 outl(data[0],
279 outl(data[0],
388 outl(0x0,
392 outl(data[1],
429 outl(0x0, devpriv->iobase + APCI2032_DIGITAL_OP_WATCHDOG + APCI2032_TCW_PROG); /* disable the watchdog */
432 outl(0x0001,
437 outl(
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H A DAPCI1710_Ssi.c227 outl(b_SSIProfile + 1, devpriv->s_BoardInfos.ui_Address + 4 + (64 * b_ModulNbr));
230 outl(b_SSIProfile, devpriv->s_BoardInfos.ui_Address + 4 + (64 * b_ModulNbr));
247 outl(ui_TimerValue, devpriv->s_BoardInfos.ui_Address + (64 * b_ModulNbr));
253 outl(7 * b_SSICountingMode, devpriv->s_BoardInfos.ui_Address + 12 + (64 * b_ModulNbr));
452 outl(0, devpriv->s_BoardInfos.
582 outl(0, devpriv->s_BoardInfos.
754 outl(1, devpriv->s_BoardInfos.ui_Address + 16 +
763 outl(0, devpriv->s_BoardInfos.ui_Address + 16 +
H A DAPCI1710_82x54.c334 outl(devpriv->s_ModuleInfo[b_ModulNbr].s_82X54ModuleInfo.s_82X54TimerInfo[b_TimerNbr].dw_ConfigurationWord, devpriv->s_BoardInfos.ui_Address + 32 + (b_TimerNbr * 4) + (64 * b_ModulNbr));
337 outl((unsigned int) b_TimerMode, devpriv->s_BoardInfos.ui_Address + 16 + (b_TimerNbr * 4) + (64 * b_ModulNbr));
340 outl(ul_ReloadValue, devpriv->s_BoardInfos.ui_Address + 0 + (b_TimerNbr * 4) + (64 * b_ModulNbr));
489 outl(devpriv->s_ModuleInfo[b_ModulNbr].s_82X54ModuleInfo.s_82X54TimerInfo[b_TimerNbr].dw_ConfigurationWord, devpriv->s_BoardInfos.ui_Address + 32 + (b_TimerNbr * 4) + (64 * b_ModulNbr));
497 outl(devpriv->s_ModuleInfo[b_ModulNbr].s_82X54ModuleInfo.s_82X54TimerInfo[b_TimerNbr].dw_ConfigurationWord, devpriv->s_BoardInfos.ui_Address + 32 + (b_TimerNbr * 4) + (64 * b_ModulNbr));
509 outl(1, devpriv->s_BoardInfos.ui_Address + 44 + (b_TimerNbr * 4) + (64 * b_ModulNbr));
524 outl(devpriv->s_ModuleInfo[b_ModulNbr].s_82X54ModuleInfo.s_82X54TimerInfo[b_TimerNbr].dw_ConfigurationWord, devpriv->s_BoardInfos.ui_Address + 32 + (b_TimerNbr * 4) + (64 * b_ModulNbr));
531 outl(0, devpriv->s_BoardInfos.ui_Address + 44 + (b_TimerNbr * 4) + (64 * b_ModulNbr));
629 outl(0x17, devpriv->s_BoardInfos.ui_Address + 12 + (64 * b_ModulNbr));
784 outl((
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H A Dhwdrv_apci3200.c664 outl(data[0], devpriv->i_IobaseAddon);
680 outl(data[0], devpriv->i_IobaseAddon);
696 outl(data[0], devpriv->i_IobaseAddon);
724 outl(data[0], devpriv->i_IobaseAddon);
1237 /* outl(0 | ui_ChannelNo , devpriv->iobase+i_Offset + 0x4); */
1238 outl(0 | ui_ChannelNo,
1251 /* outl(0 , devpriv->iobase+i_Offset + 0x0); */
1252 outl(0, devpriv->iobase + s_BoardInfos[dev->minor].i_Offset + 0x0);
1265 /* outl(ul_Config , devpriv->iobase+i_Offset + 0x0); */
1266 outl(ul_Confi
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H A DAPCI1710_Inp_cpt.c189 outl(ul_StartValue,
281 outl(devpriv->
527 outl(devpriv->
580 outl(devpriv->
624 outl(devpriv->s_ModuleInfo[b_ModulNbr].
802 outl(ul_WriteValue,
H A DAPCI1710_INCCPT.c484 outl(devpriv->s_ModuleInfo[b_ModulNbr].
585 outl(3, devpriv->s_BoardInfos.
592 outl(1, devpriv->s_BoardInfos.
617 outl(0, devpriv->s_BoardInfos.
1205 outl(devpriv->s_ModuleInfo[b_ModulNbr].
1412 outl(ui_CompareValue, devpriv->s_BoardInfos.
1930 outl(ul_TimerValue, devpriv->s_BoardInfos.ui_Address + 32 + (64 * b_ModulNbr));
2114 outl(1, devpriv->s_BoardInfos.
2188 outl(1, devpriv->s_BoardInfos.
2478 outl(devpri
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/drivers/net/ethernet/smsc/
H A Depic100.c186 #undef outl macro
192 #define outl writel macro
420 outl(0x4200, ioaddr + GENCTL);
424 outl(0x0008, ioaddr + TEST1);
427 outl(0x12, ioaddr + MIICfg);
429 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
430 outl(0x0200, ioaddr + GENCTL);
484 outl(inl(ioaddr + NVCTL) & ~0x483C, ioaddr + NVCTL);
485 outl(0x0008, ioaddr + GENCTL);
555 outl(
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/drivers/net/ethernet/dec/tulip/
H A Dxircom_cb.c348 outl(status,card->io_port+CSR5);
489 outl(val, card->io_port + CSR0);
495 outl(val, card->io_port + CSR0);
500 outl(val, card->io_port + CSR0);
521 outl(val, card->io_port + CSR1);
536 outl(val, card->io_port + CSR2);
574 outl(address, card->io_port + CSR3); /* Receive descr list address */
599 outl(address, card->io_port + CSR4); /* xmit descr list address */
611 outl(val, card->io_port + CSR3); /* Receive descriptor address */
612 outl(va
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H A Duli526x.c114 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
116 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
118 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
368 outl(0x10000, db->ioaddr + DCR0); //Diagnosis mode
369 outl(0x1c0, db->ioaddr + DCR13); //Reset dianostic pointer port
370 outl(0, db->ioaddr + DCR14); //Clear reset port
371 outl(0x10, db->ioaddr + DCR14); //Reset ID Table pointer
372 outl(0, db->ioaddr + DCR14); //Clear reset port
373 outl(0, db->ioaddr + DCR13); //Clear CR13
374 outl(
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H A Ddmfe.c182 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
184 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
186 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
623 outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
625 outl(db->cr0_data, ioaddr + DCR0);
636 outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
638 outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
641 outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
665 outl(db->cr7_data, ioaddr + DCR7);
668 outl(d
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/drivers/staging/comedi/drivers/
H A Dadl_pci9118.c481 outl(devpriv->AdFunctionReg, dev->iobase + PCI9118_ADFUNC);
493 outl(0, dev->iobase + PCI9118_DELFIFO); /* flush FIFO */
507 outl(0, dev->iobase + PCI9118_DELFIFO); /* flush FIFO */
521 outl(0, dev->iobase + PCI9118_DELFIFO); /* flush FIFO */
543 outl(data[n], dev->iobase + chanreg);
588 outl(s->state & 0x0f, dev->iobase + PCI9118_DO);
602 outl(devpriv->AdFunctionReg, dev->iobase + PCI9118_ADFUNC);
603 outl(0x30, dev->iobase + PCI9118_CNTCTRL);
604 outl((devpriv->dmabuf_hw[1 - devpriv->dma_actbuf] >> 1) & 0xff,
606 outl((devpri
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/drivers/video/backlight/
H A Dcr_bllcd.c89 outl(cur, addr);
92 outl(cur, addr);
126 outl(cur, addr);
131 outl(cur, addr);
138 outl(cur | CRVML_LVDS_ON, addr);
150 outl(cur, addr);
154 outl(cur & ~CRVML_PANEL_ON, addr);
/drivers/net/ethernet/sis/
H A Dsis900.c334 outl(rfcrSave | RELOAD, ioaddr + cr);
335 outl(0, ioaddr + cr);
338 outl(rfcrSave & ~RFEN, rfcr + ioaddr);
342 outl((i << RFADDR_shift), ioaddr + rfcr);
350 outl(rfcrSave | RFEN, rfcr + ioaddr);
379 outl(EEREQ, ee_addr);
390 outl(EEDONE, ee_addr);
397 outl(EEDONE, ee_addr);
537 outl(ACCESSMODE | inl(ioaddr + cr), ioaddr + cr);
819 outl(
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/drivers/watchdog/
H A DiTCO_vendor_support.c92 outl(val32, SMI_EN); /* Needed to activate watchdog */
102 outl(val32, SMI_EN); /* Needed to deactivate watchdog */
281 outl(val32, SMI_EN);
292 outl(val32, SMI_EN);
/drivers/scsi/
H A D3w-xxxx.h258 #define TW_CLEAR_ALL_INTERRUPTS(x) (outl(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
259 #define TW_CLEAR_ATTENTION_INTERRUPT(x) (outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
260 #define TW_CLEAR_HOST_INTERRUPT(x) (outl(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
261 #define TW_DISABLE_INTERRUPTS(x) (outl(TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
262 #define TW_ENABLE_AND_CLEAR_INTERRUPTS(x) (outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | TW_CONTROL_UNMASK_RESPONSE_INTERRUPT | TW_CONTROL_ENABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
263 #define TW_MASK_COMMAND_INTERRUPT(x) (outl(TW_CONTROL_MASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
264 #define TW_UNMASK_COMMAND_INTERRUPT(x) (outl(TW_CONTROL_UNMASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
265 #define TW_SOFT_RESET(x) (outl(TW_CONTROL_ISSUE_SOFT_RESET | \
/drivers/staging/vt6655/
H A Dupc.h68 outl(dwData, dwIOAddress); \
138 outl(dwData, dwIOAddress); \
/drivers/staging/vt6656/
H A Dupc.h68 outl(dwData, dwIOAddress); \
138 outl(dwData, dwIOAddress); \
/drivers/ide/
H A Dcs5530.c59 outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3));
120 outl(timings, basereg + 4); /* write drive0 config register */
126 outl(reg, basereg + 4); /* write drive0 config register */
127 outl(timings, basereg + 12); /* write drive1 config register */
237 outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0);
239 outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8);
/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_irq.c45 outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
192 outl(SVGA_IRQFLAG_ANY_FENCE,
223 outl(SVGA_IRQFLAG_FENCE_GOAL,
302 outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
323 outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
/drivers/net/ethernet/
H A Dmipsnet.c125 outl(skb->len, regaddr(dev, txDataCount));
189 outl(0, regaddr(dev, interruptControl));
195 outl(MIPSNET_INTCTL_TXDONE,
200 outl(MIPSNET_INTCTL_RXDONE, regaddr(dev, interruptControl));
225 outl(MIPSNET_INTCTL_TESTBIT, regaddr(dev, interruptControl));
/drivers/block/
H A Dsmart1,2.h159 outl(c->busaddr, h->io_mem_addr + COMMAND_FIFO);
164 outl(val, h->io_mem_addr + INTR_MASK);
217 outl(c->busaddr, h->io_mem_addr + SMART1_LISTADDR);

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