Searched refs:sq_gpr_resource_mgmt_1 (Results 1 - 6 of 6) sorted by relevance

/drivers/gpu/drm/radeon/
H A Devergreen_blit_kms.c280 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3; local
530 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
564 radeon_ring_write(ring, sq_gpr_resource_mgmt_1);
H A Dr600_blit.c318 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; local
455 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(num_ps_gprs) |
484 OUT_RING(sq_gpr_resource_mgmt_1);
H A Dr600_blit_kms.c283 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; local
421 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
451 radeon_ring_write(ring, sq_gpr_resource_mgmt_1);
H A Dr600_cp.c745 u32 sq_gpr_resource_mgmt_1 = 0; local
990 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) |
1010 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
1025 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
1039 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
1055 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
H A Dr600.c1515 u32 sq_gpr_resource_mgmt_1 = 0; local
1737 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1757 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1772 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1786 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1802 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
H A Devergreen.c1722 u32 sq_gpr_resource_mgmt_1; local
2261 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2262 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2263 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2296 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);

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