Searched refs:vsync_start (Results 1 - 25 of 41) sorted by relevance

12

/drivers/gpu/drm/gma500/
H A Dmdfld_tpo_vid.c52 mode->vsync_start =
56 mode->vsync_start + ((ti->vsync_pulse_width_hi << 8) |
67 dev_dbg(dev->dev, "VSS is %d\n", mode->vsync_start);
77 mode->vsync_start = 487;
H A Dmdfld_tmd_vid.c55 mode->vsync_start = \
59 mode->vsync_start + ((ti->vsync_pulse_width_hi << 8) | \
70 dev_dbg(dev->dev, "VSS is %d\n", mode->vsync_start);
80 mode->vsync_start = 861;
H A Dintel_bios.c69 panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay +
71 panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start +
H A Doaktrail_lvds.c275 mode->vsync_start = \
279 mode->vsync_start + ((ti->vsync_pulse_width_hi << 4) | \
290 printk(KERN_INFO "VSS is %d\n", mode->vsync_start);
H A Dmdfld_dsi_dpi.c440 pclk_vfp = mode->vsync_start - mode->vdisplay;
441 pclk_vsync = mode->vsync_end - mode->vsync_start;
701 adjusted_mode->vsync_start = fixed_mode->vsync_start;
805 ((mode->vsync_end - 1) << 16) | (mode->vsync_start - 1));
H A Dcdv_intel_lvds.c305 adjusted_mode->vsync_start = panel_fixed_mode->vsync_start;
H A Dpsb_drv.c528 mode->vsync_start = umode->vsync_start;
H A Dpsb_intel_lvds.c426 adjusted_mode->vsync_start = panel_fixed_mode->vsync_start;
H A Dtc35876x-dsi-lvds.c593 mode->vsync_start = 814;
603 dev_info(&dev->pdev->dev, "VSS = %d\n", mode->vsync_start);
/drivers/staging/omapdrm/
H A Domap_connector.c47 mode->vsync_start = mode->vdisplay + timings->vfp;
48 mode->vsync_end = mode->vsync_start + timings->vsw;
71 timings->vfp = mode->vsync_start - mode->vdisplay;
72 timings->vsw = mode->vsync_end - mode->vsync_start;
236 mode->vdisplay, mode->vsync_start,
303 mode->vdisplay, mode->vsync_start,
/drivers/gpu/drm/exynos/
H A Dexynos_drm_connector.c62 mode->vsync_start = mode->vdisplay + timing->lower_margin;
63 mode->vsync_end = mode->vsync_start + timing->vsync_len;
93 timing->lower_margin = mode->vsync_start - mode->vdisplay;
94 timing->vsync_len = mode->vsync_end - mode->vsync_start;
/drivers/gpu/drm/radeon/
H A Dradeon_encoders.c270 unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
272 unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
287 adjusted_mode->vsync_start = native_mode->vdisplay + vover;
288 adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
/drivers/gpu/drm/
H A Ddrm_modes.c57 mode->vdisplay, mode->vsync_start,
225 drm_mode->vsync_start = drm_mode->vdisplay + CVT_MIN_V_PORCH;
226 drm_mode->vsync_end = drm_mode->vsync_start + vsync;
257 drm_mode->vsync_start = drm_mode->vdisplay + CVT_RB_VFPORCH;
258 drm_mode->vsync_end = drm_mode->vsync_start + vsync;
447 drm_mode->vsync_start = vdisplay_rnd + vodd_front_porch_lines;
448 drm_mode->vsync_end = drm_mode->vsync_start + V_SYNC_RQD;
678 p->crtc_vsync_start = p->vsync_start;
791 mode1->vsync_start == mode2->vsync_start
[all...]
H A Ddrm_edid.c801 mode->vsync_start *= 2;
872 mode->vsync_start = mode->vdisplay + vsync_offset;
873 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
917 (mode->vsync_start - mode->vdisplay == 3);
/drivers/gpu/drm/i915/
H A Dintel_panel.c45 adjusted_mode->vsync_start = fixed_mode->vsync_start;
H A Dintel_crt.c374 uint32_t vsync_start = (vsync & 0xffff) + 1; local
376 vblank_start = vsync_start;
H A Dintel_bios.c91 panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay +
93 panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start +
H A Dintel_dvo.c156 C(vsync_start);
H A Dintel_tv.c1145 .vsync_start = 1027,
1399 mode_ptr->vsync_start = vactive_s + 1;
1401 if (mode_ptr->vsync_end <= mode_ptr->vsync_start)
1402 mode_ptr->vsync_end = mode_ptr->vsync_start + 1;
/drivers/video/
H A Dneofb.c265 int vsync_start = var->yres + var->lower_margin; local
266 int vsync_end = vsync_start + var->vsync_len;
299 | ((vsync_start & 0x100) >> 6)
303 | ((vsync_start & 0x200) >> 2);
316 par->CRTC[16] = vsync_start & 0xFF;
733 int vsync_start, vtotal; local
741 vsync_start = info->var.yres + info->var.lower_margin;
742 vtotal = vsync_start + info->var.vsync_len + info->var.upper_margin;
790 | (((vsync_start) & 0x400) >> 8)
791 | (((vsync_start)
[all...]
H A Dgbefb.c536 timing->vsync_start = var->yres + var->lower_margin + 1;
537 timing->vsync_end = timing->vsync_start + var->vsync_len;
565 SET_GBE_FIELD(VT_VSYNC, VSYNC_ON, val, timing->vsync_start);
1000 var->lower_margin = timing.vsync_start - timing.height;
1002 var->vsync_len = timing.vsync_end - timing.vsync_start;
H A Dsgivwfb.c346 var->lower_margin = timing->vsync_start - timing->height;
348 var->vsync_len = timing->vsync_end - timing->vsync_start;
528 currentTiming->vsync_start);
/drivers/video/vermilion/
H A Dvermilion.c785 u32 vtotal, vactive, vblank_start, vblank_end, vsync_start, vsync_end; local
809 vsync_start = vactive + var->lower_margin;
810 vsync_end = vsync_start + var->vsync_len;
855 ((vsync_end - 1) << 16) | (vsync_start - 1));
/drivers/gpu/drm/nouveau/
H A Dnv17_tv.c276 mode->vsync_start = output_mode->vsync_start;
538 output_mode->vsync_start - 1;
/drivers/video/intelfb/
H A Dintelfbhw.c1051 u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive; local
1190 vsync_start = vactive + var->lower_margin;
1191 vsync_end = vsync_start + var->vsync_len;
1198 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1224 vsync_start--;
1225 if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1248 *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);

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