/drivers/video/ |
H A D | wmt_ge_rops.c | 67 writel(p->var.bits_per_pixel == 32 ? 3 : 69 writel(p->var.bits_per_pixel == 15 ? 1 : 0, regbase + GE_HIGHCOLOR_OFF); 70 writel(p->fix.smem_start, regbase + GE_DESTBASE_OFF); 71 writel(p->var.xres_virtual - 1, regbase + GE_DESTDISPW_OFF); 72 writel(p->var.yres_virtual - 1, regbase + GE_DESTDISPH_OFF); 73 writel(rect->dx, regbase + GE_DESTAREAX_OFF); 74 writel(rect->dy, regbase + GE_DESTAREAY_OFF); 75 writel(rect->width - 1, regbase + GE_DESTAREAW_OFF); 76 writel(rect->height - 1, regbase + GE_DESTAREAH_OFF); 78 writel(pa [all...] |
H A D | w100fb.c | 133 writel(param, remapped_regs + regs); 297 writel(W100_FB_BASE, remapped_regs + mmDST_OFFSET); 298 writel(par->xres, remapped_regs + mmDST_PITCH); 299 writel(W100_FB_BASE, remapped_regs + mmSRC_OFFSET); 300 writel(par->xres, remapped_regs + mmSRC_PITCH); 303 writel(0, remapped_regs + mmSC_TOP_LEFT); 304 writel((par->yres << 16) | par->xres, remapped_regs + mmSC_BOTTOM_RIGHT); 305 writel(0x1fff1fff, remapped_regs + mmSRC_SC_BOTTOM_RIGHT); 315 writel(dp_cntl.val, remapped_regs + mmDP_CNTL); 332 writel(gm [all...] |
H A D | wm8505fb.c | 56 writel(0, fbi->regbase + i); 59 writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR); 60 writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR1); 63 writel(0x1c, fbi->regbase + WMT_GOVR_COLORSPACE); 64 writel(1, fbi->regbase + WMT_GOVR_COLORSPACE1); 67 writel(info->var.xres, fbi->regbase + WMT_GOVR_XRES); 68 writel(info->var.xres_virtual, fbi->regbase + WMT_GOVR_XRES_VIRTUAL); 71 writel(0xf, fbi->regbase + WMT_GOVR_FHI); 72 writel(4, fbi->regbase + WMT_GOVR_DVO_SET); 73 writel( [all...] |
/drivers/net/ethernet/chelsio/cxgb/ |
H A D | tp.c | 31 writel(val, ap->regs + A_TP_IN_CONFIG); 32 writel(F_TP_OUT_CSPI_CPL | 36 writel(V_IP_TTL(64) | 46 writel(F_ENABLE_TX_DROP | F_ENABLE_TX_ERROR | 77 writel(0xffffffff, 79 writel(tp_intr | FPGA_PCIX_INTERRUPT_TP, 85 writel(0, tp->adapter->regs + A_TP_INT_ENABLE); 86 writel(tp_intr | F_PL_INTR_TP, 98 writel(0, tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE); 99 writel(tp_int [all...] |
H A D | espi.c | 66 writel(V_WRITE_DATA(wr_data) | 72 writel(0, adapter->regs + A_ESPI_GOSTAT); 93 writel(F_ESPI_RX_CORE_RST, adapter->regs + A_ESPI_RX_RESET); 112 writel(F_ESPI_RX_CORE_RST | F_ESPI_RX_LNK_RST, 130 writel(enable, espi->adapter->regs + A_ESPI_INTR_ENABLE); 131 writel(pl_intr | F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); 137 writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS); 138 writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE); 145 writel(0, espi->adapter->regs + A_ESPI_INTR_ENABLE); 146 writel(pl_int [all...] |
/drivers/video/exynos/ |
H A D | exynos_dp_reg.c | 37 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); 41 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); 51 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); 65 writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP); 71 writel(INT_POL, dp->reg_base + EXYNOS_DP_INT_CTL); 74 writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1); 75 writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2); 76 writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3); 77 writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4); 78 writel( [all...] |
H A D | exynos_mipi_dsi_lowlevel.c | 40 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); 51 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); 62 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC); 90 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTMSK); 100 writel(reg & ~(cfg), dsim->reg_base + EXYNOS_DSIM_FIFOCTRL); 104 writel(reg, dsim->reg_base + EXYNOS_DSIM_FIFOCTRL); 113 writel(DSIM_AFC_CTL(value), dsim->reg_base + EXYNOS_DSIM_PHYACCHR); 128 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL); 139 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL); 145 writel(re [all...] |
/drivers/video/via/ |
H A D | accel.c | 48 writel(gemode, engine + VIA_REG_GEMODE); 105 writel(tmp, engine + 0x08); 114 writel(tmp, engine + 0x0C); 122 writel(tmp, engine + 0x10); 125 writel(fg_color, engine + 0x18); 128 writel(bg_color, engine + 0x1C); 138 writel(tmp, engine + 0x30); 147 writel(tmp, engine + 0x34); 159 writel(tmp, engine + 0x38); 172 writel(ge_cm [all...] |
/drivers/scsi/bfa/ |
H A D | bfa_ioc_cb.c | 86 writel(~0U, ioc->ioc_regs.err_set); 206 writel(1, ioc->ioc_regs.ioc_sem_reg); 225 writel(BFI_IOC_FAIL, ioc->ioc_regs.ioc_fwstate); 285 writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG)); 286 writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG)); 287 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); 288 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); 289 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); 290 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); 291 writel( [all...] |
H A D | bfa_ioc_ct.c | 74 writel(1, ioc->ioc_regs.ioc_usage_reg); 76 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); 77 writel(0, ioc->ioc_regs.ioc_fail_sync); 96 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); 105 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); 107 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); 132 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); 136 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); 146 writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt); 147 writel(__FW_INIT_HALT_ [all...] |
/drivers/media/video/s5p-jpeg/ |
H A D | jpeg-hw.h | 36 writel(1, regs + S5P_JPG_SW_RESET); 47 writel(S5P_POWER_ON, regs + S5P_JPGCLKCON); 63 writel(reg, regs + S5P_JPGCMOD); 75 writel(reg, regs + S5P_JPGCMOD); 90 writel(reg, regs + S5P_JPGMOD); 105 writel(reg, regs + S5P_JPGMOD); 120 writel(reg, regs + S5P_JPGDRI_U); 125 writel(reg, regs + S5P_JPGDRI_L); 135 writel(reg, regs + S5P_JPG_QTBL); 146 writel(re [all...] |
/drivers/video/geode/ |
H A D | display_gx1.c | 90 writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK); 97 writel(tcfg, par->dc_regs + DC_TIMING_CFG); 104 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); 108 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); 114 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); 135 writel(0, par->dc_regs + DC_FB_ST_OFFSET); 138 writel(info->fix.line_length >> 2, par->dc_regs + DC_LINE_DELTA); 139 writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2, 166 writel(val, par->dc_regs + DC_H_TIMING_1); 168 writel(va [all...] |
/drivers/net/ethernet/brocade/bna/ |
H A D | bfa_ioc_ct.c | 129 writel(1, ioc->ioc_regs.ioc_usage_reg); 131 writel(0, ioc->ioc_regs.ioc_fail_sync); 155 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); 180 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); 191 writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt); 192 writel(__FW_INIT_HALT_P, ioc->ioc_regs.alt_ll_halt); 429 writel(r32, rb + FNC_PERS_REG); 439 writel(1, ioc->ioc_regs.lpu_read_stat); 464 writel(r32 & __MSIX_VT_OFST_, 469 writel(__MSIX_VT_NUMVT [all...] |
/drivers/mfd/ |
H A D | db5500-prcmu.c | 180 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); 222 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); 241 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR); 243 writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR); 245 writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ); 246 writel(PRCMU_DSI_PLLOUT_SEL_SETTING, 249 writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); 252 writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE); 254 writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET); 262 writel(PRCMU_RESET_DSIPL [all...] |
/drivers/isdn/hisax/ |
H A D | telespci.c | 51 writel(WRITE_ADDR_ISAC | off, adr + 0x200); 55 writel(READ_DATA_ISAC, adr + 0x200); 68 writel(WRITE_ADDR_ISAC | off, adr + 0x200); 72 writel(WRITE_DATA_ISAC | data, adr + 0x200); 83 writel(WRITE_ADDR_HSCX | ((hscx ? 0x40 : 0) + off), adr + 0x200); 87 writel(READ_DATA_HSCX, adr + 0x200); 99 writel(WRITE_ADDR_HSCX | ((hscx ? 0x40 : 0) + off), adr + 0x200); 103 writel(WRITE_DATA_HSCX | data, adr + 0x200); 117 writel(WRITE_ADDR_ISAC | 0x1E, adr + 0x200); 119 writel(READ_DATA_ISA [all...] |
/drivers/spi/ |
H A D | spi-sirf.c | 176 writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA); 205 writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA); 235 writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA); 255 writel(spi_stat, sspi->base + SIRFSOC_SPI_INT_STATUS); 261 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN); 273 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN); 297 writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS); 300 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) | 303 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN); 304 writel( [all...] |
/drivers/net/hippi/ |
H A D | rrunner.c | 196 writel(readl(&rrpriv->regs->HostCtrl) | NO_SWAP, 241 writel(HALT_NIC, &rr->regs->HostCtrl); 284 writel(*(u32*)(cmd), ®s->CmdRing[idx]); 312 writel(0x01000000, ®s->TX_state); 313 writel(0xff800000, ®s->RX_state); 314 writel(0, ®s->AssistState); 315 writel(CLEAR_INTA, ®s->LocalCtrl); 316 writel(0x01, ®s->BrkPt); 317 writel(0, ®s->Timer); 318 writel( [all...] |
/drivers/scsi/qla4xxx/ |
H A D | ql4_inline.h | 42 writel(set_rmask(IMR_SCSI_INTR_ENABLE), 46 writel(set_rmask(CSR_SCSI_INTR_ENABLE), &ha->reg->ctrl_status); 56 writel(clr_rmask(IMR_SCSI_INTR_ENABLE), 60 writel(clr_rmask(CSR_SCSI_INTR_ENABLE), &ha->reg->ctrl_status);
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/drivers/usb/dwc3/ |
H A D | io.h | 51 writel(value, base + offset);
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/drivers/usb/otg/ |
H A D | ulpi_viewport.c | 48 writel(ULPI_VIEW_WAKEUP | ULPI_VIEW_WRITE, view); 53 writel(ULPI_VIEW_RUN | ULPI_VIEW_READ | ULPI_VIEW_ADDR(reg), view); 66 writel(ULPI_VIEW_WAKEUP | ULPI_VIEW_WRITE, view); 71 writel(ULPI_VIEW_RUN | ULPI_VIEW_WRITE | ULPI_VIEW_DATA_WRITE(val) |
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/drivers/net/tokenring/ |
H A D | 3c359.c | 221 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 225 writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 229 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 233 writel(IO_WORD_WRITE | EECONTROL , xl_mmio + MMIO_MAC_ACCESS_CMD) ; 237 writel(IO_WORD_READ | EEDATA , xl_mmio + MMIO_MAC_ACCESS_CMD) ; 253 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 257 writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 261 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 265 writel(IO_WORD_WRITE | EEDATA, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 269 writel(IO_WORD_WRIT [all...] |
/drivers/net/ethernet/sun/ |
H A D | sungem.c | 129 writel(cmd, gp->regs + MIF_FRAME); 167 writel(cmd, gp->regs + MIF_FRAME); 192 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK); 198 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK); 369 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST); 380 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB, 393 writel(0, gp->regs + RXDMA_CFG); 407 writel(gp->swrst_base | GREG_SWRST_RXRST, 435 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI); 436 writel(desc_dm [all...] |
/drivers/net/ethernet/stmicro/stmmac/ |
H A D | dwmac1000_dma.c | 41 writel(value, ioaddr + DMA_BUS_MODE); 58 writel(value, ioaddr + DMA_BUS_MODE); 61 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); 65 writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR); 66 writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR); 119 writel(csr6, ioaddr + DMA_CONTROL);
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H A D | dwmac100_dma.c | 43 writel(value, ioaddr + DMA_BUS_MODE); 54 writel(DMA_BUS_MODE_DEFAULT | (pbl << DMA_BUS_MODE_PBL_SHIFT), 58 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); 62 writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR); 63 writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR); 83 writel(csr6, ioaddr + DMA_CONTROL);
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/drivers/usb/gadget/ |
H A D | net2280.h | 29 writel (index, ®s->idxaddr); 37 writel (index, ®s->idxaddr); 38 writel (value, ®s->idxdata); 112 writel ( (1 << CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) 163 writel ( (1 << CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) 173 writel ( (1 << CLEAR_ENDPOINT_HALT) 187 writel ((1 << GPIO3_LED_SELECT) 213 writel (val, &dev->regs->gpioctl); 226 writel (val, &dev->regs->gpioctl); 231 writel (read [all...] |