1/* linux/drivers/video/exynos/exynos_mipi_dsi_lowlevel.c 2 * 3 * Samsung SoC MIPI-DSI lowlevel driver. 4 * 5 * Copyright (c) 2012 Samsung Electronics Co., Ltd 6 * 7 * InKi Dae, <inki.dae@samsung.com> 8 * Donghwa Lee, <dh09.lee@samsung.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13*/ 14 15#include <linux/module.h> 16#include <linux/kernel.h> 17#include <linux/errno.h> 18#include <linux/mutex.h> 19#include <linux/wait.h> 20#include <linux/delay.h> 21#include <linux/fs.h> 22#include <linux/mm.h> 23#include <linux/ctype.h> 24#include <linux/io.h> 25 26#include <video/exynos_mipi_dsim.h> 27 28#include <mach/map.h> 29 30#include "exynos_mipi_dsi_regs.h" 31 32void exynos_mipi_dsi_func_reset(struct mipi_dsim_device *dsim) 33{ 34 unsigned int reg; 35 36 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST); 37 38 reg |= DSIM_FUNCRST; 39 40 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); 41} 42 43void exynos_mipi_dsi_sw_reset(struct mipi_dsim_device *dsim) 44{ 45 unsigned int reg; 46 47 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST); 48 49 reg |= DSIM_SWRST; 50 51 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); 52} 53 54void exynos_mipi_dsi_sw_reset_release(struct mipi_dsim_device *dsim) 55{ 56 unsigned int reg; 57 58 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); 59 60 reg |= INTSRC_SW_RST_RELEASE; 61 62 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC); 63} 64 65int exynos_mipi_dsi_get_sw_reset_release(struct mipi_dsim_device *dsim) 66{ 67 return (readl(dsim->reg_base + EXYNOS_DSIM_INTSRC)) & 68 INTSRC_SW_RST_RELEASE; 69} 70 71unsigned int exynos_mipi_dsi_read_interrupt_mask(struct mipi_dsim_device *dsim) 72{ 73 unsigned int reg; 74 75 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTMSK); 76 77 return reg; 78} 79 80void exynos_mipi_dsi_set_interrupt_mask(struct mipi_dsim_device *dsim, 81 unsigned int mode, unsigned int mask) 82{ 83 unsigned int reg = 0; 84 85 if (mask) 86 reg |= mode; 87 else 88 reg &= ~mode; 89 90 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTMSK); 91} 92 93void exynos_mipi_dsi_init_fifo_pointer(struct mipi_dsim_device *dsim, 94 unsigned int cfg) 95{ 96 unsigned int reg; 97 98 reg = readl(dsim->reg_base + EXYNOS_DSIM_FIFOCTRL); 99 100 writel(reg & ~(cfg), dsim->reg_base + EXYNOS_DSIM_FIFOCTRL); 101 mdelay(10); 102 reg |= cfg; 103 104 writel(reg, dsim->reg_base + EXYNOS_DSIM_FIFOCTRL); 105} 106 107/* 108 * this function set PLL P, M and S value in D-PHY 109 */ 110void exynos_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim, 111 unsigned int value) 112{ 113 writel(DSIM_AFC_CTL(value), dsim->reg_base + EXYNOS_DSIM_PHYACCHR); 114} 115 116void exynos_mipi_dsi_set_main_stand_by(struct mipi_dsim_device *dsim, 117 unsigned int enable) 118{ 119 unsigned int reg; 120 121 reg = readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL); 122 123 reg &= ~DSIM_MAIN_STAND_BY; 124 125 if (enable) 126 reg |= DSIM_MAIN_STAND_BY; 127 128 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL); 129} 130 131void exynos_mipi_dsi_set_main_disp_resol(struct mipi_dsim_device *dsim, 132 unsigned int width_resol, unsigned int height_resol) 133{ 134 unsigned int reg; 135 136 /* standby should be set after configuration so set to not ready*/ 137 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL)) & 138 ~(DSIM_MAIN_STAND_BY); 139 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL); 140 141 reg &= ~((0x7ff << 16) | (0x7ff << 0)); 142 reg |= DSIM_MAIN_VRESOL(height_resol) | DSIM_MAIN_HRESOL(width_resol); 143 144 reg |= DSIM_MAIN_STAND_BY; 145 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL); 146} 147 148void exynos_mipi_dsi_set_main_disp_vporch(struct mipi_dsim_device *dsim, 149 unsigned int cmd_allow, unsigned int vfront, unsigned int vback) 150{ 151 unsigned int reg; 152 153 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MVPORCH)) & 154 ~((DSIM_CMD_ALLOW_MASK) | (DSIM_STABLE_VFP_MASK) | 155 (DSIM_MAIN_VBP_MASK)); 156 157 reg |= (DSIM_CMD_ALLOW_SHIFT(cmd_allow & 0xf) | 158 DSIM_STABLE_VFP_SHIFT(vfront & 0x7ff) | 159 DSIM_MAIN_VBP_SHIFT(vback & 0x7ff)); 160 161 writel(reg, dsim->reg_base + EXYNOS_DSIM_MVPORCH); 162} 163 164void exynos_mipi_dsi_set_main_disp_hporch(struct mipi_dsim_device *dsim, 165 unsigned int front, unsigned int back) 166{ 167 unsigned int reg; 168 169 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MHPORCH)) & 170 ~((DSIM_MAIN_HFP_MASK) | (DSIM_MAIN_HBP_MASK)); 171 172 reg |= DSIM_MAIN_HFP_SHIFT(front) | DSIM_MAIN_HBP_SHIFT(back); 173 174 writel(reg, dsim->reg_base + EXYNOS_DSIM_MHPORCH); 175} 176 177void exynos_mipi_dsi_set_main_disp_sync_area(struct mipi_dsim_device *dsim, 178 unsigned int vert, unsigned int hori) 179{ 180 unsigned int reg; 181 182 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MSYNC)) & 183 ~((DSIM_MAIN_VSA_MASK) | (DSIM_MAIN_HSA_MASK)); 184 185 reg |= (DSIM_MAIN_VSA_SHIFT(vert & 0x3ff) | 186 DSIM_MAIN_HSA_SHIFT(hori)); 187 188 writel(reg, dsim->reg_base + EXYNOS_DSIM_MSYNC); 189} 190 191void exynos_mipi_dsi_set_sub_disp_resol(struct mipi_dsim_device *dsim, 192 unsigned int vert, unsigned int hori) 193{ 194 unsigned int reg; 195 196 reg = (readl(dsim->reg_base + EXYNOS_DSIM_SDRESOL)) & 197 ~(DSIM_SUB_STANDY_MASK); 198 199 writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL); 200 201 reg &= ~(DSIM_SUB_VRESOL_MASK) | ~(DSIM_SUB_HRESOL_MASK); 202 reg |= (DSIM_SUB_VRESOL_SHIFT(vert & 0x7ff) | 203 DSIM_SUB_HRESOL_SHIFT(hori & 0x7ff)); 204 writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL); 205 206 reg |= DSIM_SUB_STANDY_SHIFT(1); 207 writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL); 208} 209 210void exynos_mipi_dsi_init_config(struct mipi_dsim_device *dsim) 211{ 212 struct mipi_dsim_config *dsim_config = dsim->dsim_config; 213 214 unsigned int cfg = (readl(dsim->reg_base + EXYNOS_DSIM_CONFIG)) & 215 ~((1 << 28) | (0x1f << 20) | (0x3 << 5)); 216 217 cfg = ((DSIM_AUTO_FLUSH(dsim_config->auto_flush)) | 218 (DSIM_EOT_DISABLE(dsim_config->eot_disable)) | 219 (DSIM_AUTO_MODE_SHIFT(dsim_config->auto_vertical_cnt)) | 220 (DSIM_HSE_MODE_SHIFT(dsim_config->hse)) | 221 (DSIM_HFP_MODE_SHIFT(dsim_config->hfp)) | 222 (DSIM_HBP_MODE_SHIFT(dsim_config->hbp)) | 223 (DSIM_HSA_MODE_SHIFT(dsim_config->hsa)) | 224 (DSIM_NUM_OF_DATALANE_SHIFT(dsim_config->e_no_data_lane))); 225 226 writel(cfg, dsim->reg_base + EXYNOS_DSIM_CONFIG); 227} 228 229void exynos_mipi_dsi_display_config(struct mipi_dsim_device *dsim, 230 struct mipi_dsim_config *dsim_config) 231{ 232 u32 reg = (readl(dsim->reg_base + EXYNOS_DSIM_CONFIG)) & 233 ~((0x3 << 26) | (1 << 25) | (0x3 << 18) | (0x7 << 12) | 234 (0x3 << 16) | (0x7 << 8)); 235 236 if (dsim_config->e_interface == DSIM_VIDEO) 237 reg |= (1 << 25); 238 else if (dsim_config->e_interface == DSIM_COMMAND) 239 reg &= ~(1 << 25); 240 else { 241 dev_err(dsim->dev, "unknown lcd type.\n"); 242 return; 243 } 244 245 /* main lcd */ 246 reg |= ((u8) (dsim_config->e_burst_mode) & 0x3) << 26 | 247 ((u8) (dsim_config->e_virtual_ch) & 0x3) << 18 | 248 ((u8) (dsim_config->e_pixel_format) & 0x7) << 12; 249 250 writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG); 251} 252 253void exynos_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim, unsigned int lane, 254 unsigned int enable) 255{ 256 unsigned int reg; 257 258 reg = readl(dsim->reg_base + EXYNOS_DSIM_CONFIG); 259 260 if (enable) 261 reg |= DSIM_LANE_ENx(lane); 262 else 263 reg &= ~DSIM_LANE_ENx(lane); 264 265 writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG); 266} 267 268 269void exynos_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim, 270 unsigned int count) 271{ 272 unsigned int cfg; 273 274 /* get the data lane number. */ 275 cfg = DSIM_NUM_OF_DATALANE_SHIFT(count); 276 277 writel(cfg, dsim->reg_base + EXYNOS_DSIM_CONFIG); 278} 279 280void exynos_mipi_dsi_enable_afc(struct mipi_dsim_device *dsim, unsigned int enable, 281 unsigned int afc_code) 282{ 283 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PHYACCHR); 284 285 if (enable) { 286 reg |= (1 << 14); 287 reg &= ~(0x7 << 5); 288 reg |= (afc_code & 0x7) << 5; 289 } else 290 reg &= ~(1 << 14); 291 292 writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR); 293} 294 295void exynos_mipi_dsi_enable_pll_bypass(struct mipi_dsim_device *dsim, 296 unsigned int enable) 297{ 298 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) & 299 ~(DSIM_PLL_BYPASS_SHIFT(0x1)); 300 301 reg |= DSIM_PLL_BYPASS_SHIFT(enable); 302 303 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); 304} 305 306void exynos_mipi_dsi_set_pll_pms(struct mipi_dsim_device *dsim, unsigned int p, 307 unsigned int m, unsigned int s) 308{ 309 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL); 310 311 reg |= ((p & 0x3f) << 13) | ((m & 0x1ff) << 4) | ((s & 0x7) << 1); 312 313 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); 314} 315 316void exynos_mipi_dsi_pll_freq_band(struct mipi_dsim_device *dsim, 317 unsigned int freq_band) 318{ 319 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) & 320 ~(DSIM_FREQ_BAND_SHIFT(0x1f)); 321 322 reg |= DSIM_FREQ_BAND_SHIFT(freq_band & 0x1f); 323 324 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); 325} 326 327void exynos_mipi_dsi_pll_freq(struct mipi_dsim_device *dsim, 328 unsigned int pre_divider, unsigned int main_divider, 329 unsigned int scaler) 330{ 331 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) & 332 ~(0x7ffff << 1); 333 334 reg |= (pre_divider & 0x3f) << 13 | (main_divider & 0x1ff) << 4 | 335 (scaler & 0x7) << 1; 336 337 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); 338} 339 340void exynos_mipi_dsi_pll_stable_time(struct mipi_dsim_device *dsim, 341 unsigned int lock_time) 342{ 343 writel(lock_time, dsim->reg_base + EXYNOS_DSIM_PLLTMR); 344} 345 346void exynos_mipi_dsi_enable_pll(struct mipi_dsim_device *dsim, unsigned int enable) 347{ 348 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) & 349 ~(DSIM_PLL_EN_SHIFT(0x1)); 350 351 reg |= DSIM_PLL_EN_SHIFT(enable & 0x1); 352 353 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); 354} 355 356void exynos_mipi_dsi_set_byte_clock_src(struct mipi_dsim_device *dsim, 357 unsigned int src) 358{ 359 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) & 360 ~(DSIM_BYTE_CLK_SRC_SHIFT(0x3)); 361 362 reg |= (DSIM_BYTE_CLK_SRC_SHIFT(src)); 363 364 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); 365} 366 367void exynos_mipi_dsi_enable_byte_clock(struct mipi_dsim_device *dsim, 368 unsigned int enable) 369{ 370 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) & 371 ~(DSIM_BYTE_CLKEN_SHIFT(0x1)); 372 373 reg |= DSIM_BYTE_CLKEN_SHIFT(enable); 374 375 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); 376} 377 378void exynos_mipi_dsi_set_esc_clk_prs(struct mipi_dsim_device *dsim, 379 unsigned int enable, unsigned int prs_val) 380{ 381 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) & 382 ~(DSIM_ESC_CLKEN_SHIFT(0x1) | 0xffff); 383 384 reg |= DSIM_ESC_CLKEN_SHIFT(enable); 385 if (enable) 386 reg |= prs_val; 387 388 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); 389} 390 391void exynos_mipi_dsi_enable_esc_clk_on_lane(struct mipi_dsim_device *dsim, 392 unsigned int lane_sel, unsigned int enable) 393{ 394 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL); 395 396 if (enable) 397 reg |= DSIM_LANE_ESC_CLKEN(lane_sel); 398 else 399 400 reg &= ~DSIM_LANE_ESC_CLKEN(lane_sel); 401 402 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); 403} 404 405void exynos_mipi_dsi_force_dphy_stop_state(struct mipi_dsim_device *dsim, 406 unsigned int enable) 407{ 408 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE)) & 409 ~(DSIM_FORCE_STOP_STATE_SHIFT(0x1)); 410 411 reg |= (DSIM_FORCE_STOP_STATE_SHIFT(enable & 0x1)); 412 413 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE); 414} 415 416unsigned int exynos_mipi_dsi_is_lane_state(struct mipi_dsim_device *dsim) 417{ 418 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_STATUS); 419 420 /** 421 * check clock and data lane states. 422 * if MIPI-DSI controller was enabled at bootloader then 423 * TX_READY_HS_CLK is enabled otherwise STOP_STATE_CLK. 424 * so it should be checked for two case. 425 */ 426 if ((reg & DSIM_STOP_STATE_DAT(0xf)) && 427 ((reg & DSIM_STOP_STATE_CLK) || 428 (reg & DSIM_TX_READY_HS_CLK))) 429 return 1; 430 431 return 0; 432} 433 434void exynos_mipi_dsi_set_stop_state_counter(struct mipi_dsim_device *dsim, 435 unsigned int cnt_val) 436{ 437 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE)) & 438 ~(DSIM_STOP_STATE_CNT_SHIFT(0x7ff)); 439 440 reg |= (DSIM_STOP_STATE_CNT_SHIFT(cnt_val & 0x7ff)); 441 442 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE); 443} 444 445void exynos_mipi_dsi_set_bta_timeout(struct mipi_dsim_device *dsim, 446 unsigned int timeout) 447{ 448 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_TIMEOUT)) & 449 ~(DSIM_BTA_TOUT_SHIFT(0xff)); 450 451 reg |= (DSIM_BTA_TOUT_SHIFT(timeout)); 452 453 writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT); 454} 455 456void exynos_mipi_dsi_set_lpdr_timeout(struct mipi_dsim_device *dsim, 457 unsigned int timeout) 458{ 459 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_TIMEOUT)) & 460 ~(DSIM_LPDR_TOUT_SHIFT(0xffff)); 461 462 reg |= (DSIM_LPDR_TOUT_SHIFT(timeout)); 463 464 writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT); 465} 466 467void exynos_mipi_dsi_set_cpu_transfer_mode(struct mipi_dsim_device *dsim, 468 unsigned int lp) 469{ 470 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE); 471 472 reg &= ~DSIM_CMD_LPDT_LP; 473 474 if (lp) 475 reg |= DSIM_CMD_LPDT_LP; 476 477 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE); 478} 479 480void exynos_mipi_dsi_set_lcdc_transfer_mode(struct mipi_dsim_device *dsim, 481 unsigned int lp) 482{ 483 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE); 484 485 reg &= ~DSIM_TX_LPDT_LP; 486 487 if (lp) 488 reg |= DSIM_TX_LPDT_LP; 489 490 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE); 491} 492 493void exynos_mipi_dsi_enable_hs_clock(struct mipi_dsim_device *dsim, 494 unsigned int enable) 495{ 496 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) & 497 ~(DSIM_TX_REQUEST_HSCLK_SHIFT(0x1)); 498 499 reg |= DSIM_TX_REQUEST_HSCLK_SHIFT(enable); 500 501 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); 502} 503 504void exynos_mipi_dsi_dp_dn_swap(struct mipi_dsim_device *dsim, 505 unsigned int swap_en) 506{ 507 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PHYACCHR1); 508 509 reg &= ~(0x3 << 0); 510 reg |= (swap_en & 0x3) << 0; 511 512 writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR1); 513} 514 515void exynos_mipi_dsi_hs_zero_ctrl(struct mipi_dsim_device *dsim, 516 unsigned int hs_zero) 517{ 518 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) & 519 ~(0xf << 28); 520 521 reg |= ((hs_zero & 0xf) << 28); 522 523 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); 524} 525 526void exynos_mipi_dsi_prep_ctrl(struct mipi_dsim_device *dsim, unsigned int prep) 527{ 528 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) & 529 ~(0x7 << 20); 530 531 reg |= ((prep & 0x7) << 20); 532 533 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); 534} 535 536unsigned int exynos_mipi_dsi_read_interrupt(struct mipi_dsim_device *dsim) 537{ 538 return readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); 539} 540 541void exynos_mipi_dsi_clear_interrupt(struct mipi_dsim_device *dsim, 542 unsigned int src) 543{ 544 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); 545 546 reg |= src; 547 548 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC); 549} 550 551void exynos_mipi_dsi_set_interrupt(struct mipi_dsim_device *dsim, 552 unsigned int src, unsigned int enable) 553{ 554 unsigned int reg = 0; 555 556 if (enable) 557 reg |= src; 558 else 559 reg &= ~src; 560 561 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC); 562} 563 564unsigned int exynos_mipi_dsi_is_pll_stable(struct mipi_dsim_device *dsim) 565{ 566 unsigned int reg; 567 568 reg = readl(dsim->reg_base + EXYNOS_DSIM_STATUS); 569 570 return reg & (1 << 31) ? 1 : 0; 571} 572 573unsigned int exynos_mipi_dsi_get_fifo_state(struct mipi_dsim_device *dsim) 574{ 575 return readl(dsim->reg_base + EXYNOS_DSIM_FIFOCTRL) & ~(0x1f); 576} 577 578void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim, 579 unsigned int di, unsigned int data0, unsigned int data1) 580{ 581 unsigned int reg = (data1 << 16) | (data0 << 8) | ((di & 0x3f) << 0); 582 583 writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR); 584} 585 586void exynos_mipi_dsi_rd_tx_header(struct mipi_dsim_device *dsim, 587 unsigned int di, unsigned int data0) 588{ 589 unsigned int reg = (data0 << 8) | (di << 0); 590 591 writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR); 592} 593 594unsigned int exynos_mipi_dsi_rd_rx_fifo(struct mipi_dsim_device *dsim) 595{ 596 return readl(dsim->reg_base + EXYNOS_DSIM_RXFIFO); 597} 598 599unsigned int _exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim) 600{ 601 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); 602 603 return (reg & INTSRC_FRAME_DONE) ? 1 : 0; 604} 605 606void _exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim) 607{ 608 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); 609 610 writel(reg | INTSRC_FRAME_DONE, dsim->reg_base + 611 EXYNOS_DSIM_INTSRC); 612} 613 614void exynos_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim, 615 unsigned int tx_data) 616{ 617 writel(tx_data, dsim->reg_base + EXYNOS_DSIM_PAYLOAD); 618} 619