Searched refs:regbase (Results 1 - 19 of 19) sorted by relevance

/drivers/video/
H A Dwmt_ge_rops.c47 static void __iomem *regbase; variable
68 (p->var.bits_per_pixel == 8 ? 0 : 1), regbase + GE_DEPTH_OFF);
69 writel(p->var.bits_per_pixel == 15 ? 1 : 0, regbase + GE_HIGHCOLOR_OFF);
70 writel(p->fix.smem_start, regbase + GE_DESTBASE_OFF);
71 writel(p->var.xres_virtual - 1, regbase + GE_DESTDISPW_OFF);
72 writel(p->var.yres_virtual - 1, regbase + GE_DESTDISPH_OFF);
73 writel(rect->dx, regbase + GE_DESTAREAX_OFF);
74 writel(rect->dy, regbase + GE_DESTAREAY_OFF);
75 writel(rect->width - 1, regbase + GE_DESTAREAW_OFF);
76 writel(rect->height - 1, regbase
[all...]
H A Dvt8500lcdfb.h18 void __iomem *regbase; member in struct:vt8500lcd_info
H A Dcirrusfb.c362 u8 __iomem *regbase; member in struct:cirrusfb_info
402 static void cirrusfb_WaitBLT(u8 __iomem *regbase);
403 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
408 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
417 static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase);
419 caddr_t regbase,
458 long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f;
661 old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40;
667 old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1;
671 vga_wseq(cinfo->regbase, CL_SEQR1
685 u8 __iomem *regbase = cinfo->regbase; local
1895 cirrusfb_get_memsize(struct fb_info *info, u8 __iomem *regbase) argument
2247 unsigned long regbase, ramsize, rambase; local
2628 cirrusfb_WaitBLT(u8 __iomem *regbase) argument
2640 cirrusfb_set_blitter(u8 __iomem *regbase, u_short nwidth, u_short nheight, u_long nsrc, u_long ndest, u_short bltmode, u_short line_length) argument
2700 cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel, u_short curx, u_short cury, u_short destx, u_short desty, u_short width, u_short height, u_short line_length) argument
2744 cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel, u_short x, u_short y, u_short width, u_short height, u32 fg_color, u32 bg_color, u_short line_length, u_char blitmode) argument
2859 cirrusfb_dbg_print_regs(struct fb_info *info, caddr_t regbase, enum cirrusfb_dbg_reg_class reg_class, ...) argument
2905 cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase) argument
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H A Dsvgalib.c23 void svga_wcrt_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value) argument
28 regval = vga_rcrt(regbase, regset->regnum);
37 vga_wcrt(regbase, regset->regnum, regval);
43 void svga_wseq_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value) argument
48 regval = vga_rseq(regbase, regset->regnum);
57 vga_wseq(regbase, regset->regnum, regval);
78 void svga_set_default_gfx_regs(void __iomem *regbase) argument
81 vga_wgfx(regbase, VGA_GFX_SR_VALUE, 0x00);
82 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, 0x00);
83 vga_wgfx(regbase, VGA_GFX_COMPARE_VALU
96 svga_set_default_atc_regs(void __iomem *regbase) argument
119 svga_set_default_seq_regs(void __iomem *regbase) argument
130 svga_set_default_crt_regs(void __iomem *regbase) argument
140 svga_set_textmode_vga_regs(void __iomem *regbase) argument
302 svga_tilecursor(void __iomem *regbase, struct fb_info *info, struct fb_tilecursor *cursor) argument
510 svga_set_timings(void __iomem *regbase, const struct svga_timing_regs *tm, struct fb_var_screeninfo *var, u32 hmul, u32 hdiv, u32 vmul, u32 vdiv, u32 hborder, int node) argument
[all...]
H A Dwm8505fb.c43 void __iomem *regbase; member in struct:wm8505fb_info
56 writel(0, fbi->regbase + i);
59 writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR);
60 writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR1);
63 writel(0x1c, fbi->regbase + WMT_GOVR_COLORSPACE);
64 writel(1, fbi->regbase + WMT_GOVR_COLORSPACE1);
67 writel(info->var.xres, fbi->regbase + WMT_GOVR_XRES);
68 writel(info->var.xres_virtual, fbi->regbase + WMT_GOVR_XRES_VIRTUAL);
71 writel(0xf, fbi->regbase + WMT_GOVR_FHI);
72 writel(4, fbi->regbase
[all...]
H A Dvt8500lcdfb.c116 control0 = readl(fbi->regbase) & ~0xf;
117 writel(0, fbi->regbase);
118 while (readl(fbi->regbase + 0x38) & 0x10)
123 | (info->var.right_margin & 0xff), fbi->regbase + 0x4);
127 | (info->var.lower_margin & 0xff), fbi->regbase + 0x8);
129 | ((info->var.xres - 1) & 0x400), fbi->regbase + 0x10);
130 writel(0x80000000, fbi->regbase + 0x20);
131 writel(control0 | (reg_bpp << 1) | 0x100, fbi->regbase);
190 writel(0xffffffff ^ (1 << 3), fbi->regbase + 0x3c);
192 readl(fbi->regbase
[all...]
H A Dvgastate.c34 static inline unsigned char vga_rcrtcs(void __iomem *regbase, unsigned short iobase, argument
37 vga_w(regbase, iobase + 0x4, reg);
38 return vga_r(regbase, iobase + 0x5);
41 static inline void vga_wcrtcs(void __iomem *regbase, unsigned short iobase, argument
44 vga_w(regbase, iobase + 0x4, reg);
45 vga_w(regbase, iobase + 0x5, val);
/drivers/rtc/
H A Drtc-vt8500.c80 void __iomem *regbase; member in struct:vt8500_rtc
96 isr = readl(vt8500_rtc->regbase + VT8500_RTC_IS);
97 writel(isr, vt8500_rtc->regbase + VT8500_RTC_IS);
114 date = readl(vt8500_rtc->regbase + VT8500_RTC_DR);
115 time = readl(vt8500_rtc->regbase + VT8500_RTC_TR);
142 vt8500_rtc->regbase + VT8500_RTC_DS);
147 vt8500_rtc->regbase + VT8500_RTC_TS);
157 alarm = readl(vt8500_rtc->regbase + VT8500_RTC_AS);
158 isr = readl(vt8500_rtc->regbase + VT8500_RTC_IS);
180 vt8500_rtc->regbase
[all...]
H A Drtc-sh.c92 void __iomem *regbase; member in struct:sh_rtc
109 tmp = readb(rtc->regbase + RCR1);
112 writeb(tmp, rtc->regbase + RCR1);
125 tmp = readb(rtc->regbase + RCR1);
128 writeb(tmp, rtc->regbase + RCR1);
142 tmp = readb(rtc->regbase + RCR2);
145 writeb(tmp, rtc->regbase + RCR2);
226 tmp = readb(rtc->regbase + RCR2);
237 writeb(tmp, rtc->regbase + RCR2);
301 tmp = readb(rtc->regbase
[all...]
/drivers/gpio/
H A Dgpio-pxa.c61 void __iomem *regbase; member in struct:pxa_gpio_chip
97 return container_of(c, struct pxa_gpio_chip, chip)->regbase;
289 chips[i].regbase = gpio_reg_base + BANK_OFF(i);
316 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
317 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
320 writel_relaxed(grer, c->regbase + GRER_OFFSET);
321 writel_relaxed(gfer, c->regbase + GFER_OFFSET);
345 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
348 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET);
350 writel_relaxed(gpdr & ~mask, c->regbase
[all...]
/drivers/ide/
H A Dau1xxx-ide.c325 u32 devwidth, u32 flags, u32 regbase)
328 dev->dev_physaddr = CPHYSADDR(regbase);
365 DEV_FLAGS_OUT | flags, auide->regbase);
369 DEV_FLAGS_IN | flags, auide->regbase);
374 devwidth, DEV_FLAGS_ANYUSE, auide->regbase);
417 DEV_FLAGS_OUT | flags, auide->regbase);
421 DEV_FLAGS_IN | flags, auide->regbase);
455 *ata_regs++ = ahwif->regbase + (i << IDE_REG_SHIFT);
458 *ata_regs = ahwif->regbase + (14 << IDE_REG_SHIFT);
537 ahwif->regbase
324 auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags, u32 regbase) argument
[all...]
H A Dpmac.c57 unsigned long regbase; member in struct:pmac_ide_hwif
1146 unsigned long regbase; local
1183 regbase = (unsigned long) base;
1187 pmif->regbase = regbase;
1204 pmac_ide_init_ports(&hw, pmif->regbase);
1307 pmif->regbase = (unsigned long) base + 0x2000;
1315 pmac_ide_init_ports(&hw, pmif->regbase);
/drivers/macintosh/
H A Dmediabay.c562 u32 __iomem *regbase; local
578 regbase = (u32 __iomem *)ioremap(base, 0x100);
579 if (regbase == NULL) {
587 bay->base = regbase;
/drivers/mfd/
H A Dsm501.c44 void __iomem *regbase; member in struct:sm501_gpio_chip
898 result = smc501_readl(smgpio->regbase + SM501_GPIO_DATA_LOW);
929 void __iomem *regs = smchip->regbase;
953 void __iomem *regs = smchip->regbase;
980 void __iomem *regs = smchip->regbase;
1030 chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH;
1034 chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW;
/drivers/video/kyro/
H A Dfbdev.c694 currentpar->regbase = deviceInfo.pSTGReg =
750 iounmap(currentpar->regbase);
773 iounmap(par->regbase);
/drivers/iommu/
H A Domap-iommu.c950 obj->regbase = ioremap(res->start, resource_size(res));
951 if (!obj->regbase) {
971 iounmap(obj->regbase);
995 iounmap(obj->regbase);
/drivers/video/aty/
H A Daty128fb.c405 void __iomem *regbase; /* remapped mmio */ member in struct:aty128fb_par
499 return readl (par->regbase + regindex);
505 writel (val, par->regbase + regindex);
511 return readb (par->regbase + regindex);
517 writeb (val, par->regbase + regindex);
2065 par->regbase = pci_ioremap_bar(pdev, 2);
2066 if (!par->regbase)
2125 iounmap(par->regbase);
2158 iounmap(par->regbase);
/drivers/net/ethernet/nxp/
H A Dlpc_eth.c558 static void lpc_eth_enable_int(void __iomem *regbase) argument
561 LPC_ENET_INTENABLE(regbase));
564 static void lpc_eth_disable_int(void __iomem *regbase) argument
566 writel(0, LPC_ENET_INTENABLE(regbase));
/drivers/net/ethernet/broadcom/
H A Dtg3.c623 u32 regbase, bit; local
626 regbase = TG3_APE_LOCK_GRANT;
628 regbase = TG3_APE_PER_LOCK_GRANT;
645 tg3_ape_write32(tp, regbase + 4 * i, bit);

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