1/*
2 * omap iommu: tlb and pagetable primitives
3 *
4 * Copyright (C) 2008-2010 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
7 *		Paul Mundt and Toshihiro Kobayashi
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/err.h>
15#include <linux/module.h>
16#include <linux/slab.h>
17#include <linux/interrupt.h>
18#include <linux/ioport.h>
19#include <linux/clk.h>
20#include <linux/platform_device.h>
21#include <linux/iommu.h>
22#include <linux/mutex.h>
23#include <linux/spinlock.h>
24
25#include <asm/cacheflush.h>
26
27#include <plat/iommu.h>
28
29#include <plat/iopgtable.h>
30
31#define for_each_iotlb_cr(obj, n, __i, cr)				\
32	for (__i = 0;							\
33	     (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true);	\
34	     __i++)
35
36/* bitmap of the page sizes currently supported */
37#define OMAP_IOMMU_PGSIZES	(SZ_4K | SZ_64K | SZ_1M | SZ_16M)
38
39/**
40 * struct omap_iommu_domain - omap iommu domain
41 * @pgtable:	the page table
42 * @iommu_dev:	an omap iommu device attached to this domain. only a single
43 *		iommu device can be attached for now.
44 * @lock:	domain lock, should be taken when attaching/detaching
45 */
46struct omap_iommu_domain {
47	u32 *pgtable;
48	struct omap_iommu *iommu_dev;
49	spinlock_t lock;
50};
51
52/* accommodate the difference between omap1 and omap2/3 */
53static const struct iommu_functions *arch_iommu;
54
55static struct platform_driver omap_iommu_driver;
56static struct kmem_cache *iopte_cachep;
57
58/**
59 * omap_install_iommu_arch - Install archtecure specific iommu functions
60 * @ops:	a pointer to architecture specific iommu functions
61 *
62 * There are several kind of iommu algorithm(tlb, pagetable) among
63 * omap series. This interface installs such an iommu algorighm.
64 **/
65int omap_install_iommu_arch(const struct iommu_functions *ops)
66{
67	if (arch_iommu)
68		return -EBUSY;
69
70	arch_iommu = ops;
71	return 0;
72}
73EXPORT_SYMBOL_GPL(omap_install_iommu_arch);
74
75/**
76 * omap_uninstall_iommu_arch - Uninstall archtecure specific iommu functions
77 * @ops:	a pointer to architecture specific iommu functions
78 *
79 * This interface uninstalls the iommu algorighm installed previously.
80 **/
81void omap_uninstall_iommu_arch(const struct iommu_functions *ops)
82{
83	if (arch_iommu != ops)
84		pr_err("%s: not your arch\n", __func__);
85
86	arch_iommu = NULL;
87}
88EXPORT_SYMBOL_GPL(omap_uninstall_iommu_arch);
89
90/**
91 * omap_iommu_save_ctx - Save registers for pm off-mode support
92 * @dev:	client device
93 **/
94void omap_iommu_save_ctx(struct device *dev)
95{
96	struct omap_iommu *obj = dev_to_omap_iommu(dev);
97
98	arch_iommu->save_ctx(obj);
99}
100EXPORT_SYMBOL_GPL(omap_iommu_save_ctx);
101
102/**
103 * omap_iommu_restore_ctx - Restore registers for pm off-mode support
104 * @dev:	client device
105 **/
106void omap_iommu_restore_ctx(struct device *dev)
107{
108	struct omap_iommu *obj = dev_to_omap_iommu(dev);
109
110	arch_iommu->restore_ctx(obj);
111}
112EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx);
113
114/**
115 * omap_iommu_arch_version - Return running iommu arch version
116 **/
117u32 omap_iommu_arch_version(void)
118{
119	return arch_iommu->version;
120}
121EXPORT_SYMBOL_GPL(omap_iommu_arch_version);
122
123static int iommu_enable(struct omap_iommu *obj)
124{
125	int err;
126
127	if (!obj)
128		return -EINVAL;
129
130	if (!arch_iommu)
131		return -ENODEV;
132
133	clk_enable(obj->clk);
134
135	err = arch_iommu->enable(obj);
136
137	clk_disable(obj->clk);
138	return err;
139}
140
141static void iommu_disable(struct omap_iommu *obj)
142{
143	if (!obj)
144		return;
145
146	clk_enable(obj->clk);
147
148	arch_iommu->disable(obj);
149
150	clk_disable(obj->clk);
151}
152
153/*
154 *	TLB operations
155 */
156void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
157{
158	BUG_ON(!cr || !e);
159
160	arch_iommu->cr_to_e(cr, e);
161}
162EXPORT_SYMBOL_GPL(omap_iotlb_cr_to_e);
163
164static inline int iotlb_cr_valid(struct cr_regs *cr)
165{
166	if (!cr)
167		return -EINVAL;
168
169	return arch_iommu->cr_valid(cr);
170}
171
172static inline struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj,
173					     struct iotlb_entry *e)
174{
175	if (!e)
176		return NULL;
177
178	return arch_iommu->alloc_cr(obj, e);
179}
180
181static u32 iotlb_cr_to_virt(struct cr_regs *cr)
182{
183	return arch_iommu->cr_to_virt(cr);
184}
185
186static u32 get_iopte_attr(struct iotlb_entry *e)
187{
188	return arch_iommu->get_pte_attr(e);
189}
190
191static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da)
192{
193	return arch_iommu->fault_isr(obj, da);
194}
195
196static void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l)
197{
198	u32 val;
199
200	val = iommu_read_reg(obj, MMU_LOCK);
201
202	l->base = MMU_LOCK_BASE(val);
203	l->vict = MMU_LOCK_VICT(val);
204
205}
206
207static void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l)
208{
209	u32 val;
210
211	val = (l->base << MMU_LOCK_BASE_SHIFT);
212	val |= (l->vict << MMU_LOCK_VICT_SHIFT);
213
214	iommu_write_reg(obj, val, MMU_LOCK);
215}
216
217static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
218{
219	arch_iommu->tlb_read_cr(obj, cr);
220}
221
222static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
223{
224	arch_iommu->tlb_load_cr(obj, cr);
225
226	iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
227	iommu_write_reg(obj, 1, MMU_LD_TLB);
228}
229
230/**
231 * iotlb_dump_cr - Dump an iommu tlb entry into buf
232 * @obj:	target iommu
233 * @cr:		contents of cam and ram register
234 * @buf:	output buffer
235 **/
236static inline ssize_t iotlb_dump_cr(struct omap_iommu *obj, struct cr_regs *cr,
237				    char *buf)
238{
239	BUG_ON(!cr || !buf);
240
241	return arch_iommu->dump_cr(obj, cr, buf);
242}
243
244/* only used in iotlb iteration for-loop */
245static struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n)
246{
247	struct cr_regs cr;
248	struct iotlb_lock l;
249
250	iotlb_lock_get(obj, &l);
251	l.vict = n;
252	iotlb_lock_set(obj, &l);
253	iotlb_read_cr(obj, &cr);
254
255	return cr;
256}
257
258/**
259 * load_iotlb_entry - Set an iommu tlb entry
260 * @obj:	target iommu
261 * @e:		an iommu tlb entry info
262 **/
263#ifdef PREFETCH_IOTLB
264static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
265{
266	int err = 0;
267	struct iotlb_lock l;
268	struct cr_regs *cr;
269
270	if (!obj || !obj->nr_tlb_entries || !e)
271		return -EINVAL;
272
273	clk_enable(obj->clk);
274
275	iotlb_lock_get(obj, &l);
276	if (l.base == obj->nr_tlb_entries) {
277		dev_warn(obj->dev, "%s: preserve entries full\n", __func__);
278		err = -EBUSY;
279		goto out;
280	}
281	if (!e->prsvd) {
282		int i;
283		struct cr_regs tmp;
284
285		for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp)
286			if (!iotlb_cr_valid(&tmp))
287				break;
288
289		if (i == obj->nr_tlb_entries) {
290			dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
291			err = -EBUSY;
292			goto out;
293		}
294
295		iotlb_lock_get(obj, &l);
296	} else {
297		l.vict = l.base;
298		iotlb_lock_set(obj, &l);
299	}
300
301	cr = iotlb_alloc_cr(obj, e);
302	if (IS_ERR(cr)) {
303		clk_disable(obj->clk);
304		return PTR_ERR(cr);
305	}
306
307	iotlb_load_cr(obj, cr);
308	kfree(cr);
309
310	if (e->prsvd)
311		l.base++;
312	/* increment victim for next tlb load */
313	if (++l.vict == obj->nr_tlb_entries)
314		l.vict = l.base;
315	iotlb_lock_set(obj, &l);
316out:
317	clk_disable(obj->clk);
318	return err;
319}
320
321#else /* !PREFETCH_IOTLB */
322
323static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
324{
325	return 0;
326}
327
328#endif /* !PREFETCH_IOTLB */
329
330static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
331{
332	return load_iotlb_entry(obj, e);
333}
334
335/**
336 * flush_iotlb_page - Clear an iommu tlb entry
337 * @obj:	target iommu
338 * @da:		iommu device virtual address
339 *
340 * Clear an iommu tlb entry which includes 'da' address.
341 **/
342static void flush_iotlb_page(struct omap_iommu *obj, u32 da)
343{
344	int i;
345	struct cr_regs cr;
346
347	clk_enable(obj->clk);
348
349	for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) {
350		u32 start;
351		size_t bytes;
352
353		if (!iotlb_cr_valid(&cr))
354			continue;
355
356		start = iotlb_cr_to_virt(&cr);
357		bytes = iopgsz_to_bytes(cr.cam & 3);
358
359		if ((start <= da) && (da < start + bytes)) {
360			dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
361				__func__, start, da, bytes);
362			iotlb_load_cr(obj, &cr);
363			iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
364		}
365	}
366	clk_disable(obj->clk);
367
368	if (i == obj->nr_tlb_entries)
369		dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da);
370}
371
372/**
373 * flush_iotlb_all - Clear all iommu tlb entries
374 * @obj:	target iommu
375 **/
376static void flush_iotlb_all(struct omap_iommu *obj)
377{
378	struct iotlb_lock l;
379
380	clk_enable(obj->clk);
381
382	l.base = 0;
383	l.vict = 0;
384	iotlb_lock_set(obj, &l);
385
386	iommu_write_reg(obj, 1, MMU_GFLUSH);
387
388	clk_disable(obj->clk);
389}
390
391#if defined(CONFIG_OMAP_IOMMU_DEBUG) || defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE)
392
393ssize_t omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t bytes)
394{
395	if (!obj || !buf)
396		return -EINVAL;
397
398	clk_enable(obj->clk);
399
400	bytes = arch_iommu->dump_ctx(obj, buf, bytes);
401
402	clk_disable(obj->clk);
403
404	return bytes;
405}
406EXPORT_SYMBOL_GPL(omap_iommu_dump_ctx);
407
408static int
409__dump_tlb_entries(struct omap_iommu *obj, struct cr_regs *crs, int num)
410{
411	int i;
412	struct iotlb_lock saved;
413	struct cr_regs tmp;
414	struct cr_regs *p = crs;
415
416	clk_enable(obj->clk);
417	iotlb_lock_get(obj, &saved);
418
419	for_each_iotlb_cr(obj, num, i, tmp) {
420		if (!iotlb_cr_valid(&tmp))
421			continue;
422		*p++ = tmp;
423	}
424
425	iotlb_lock_set(obj, &saved);
426	clk_disable(obj->clk);
427
428	return  p - crs;
429}
430
431/**
432 * omap_dump_tlb_entries - dump cr arrays to given buffer
433 * @obj:	target iommu
434 * @buf:	output buffer
435 **/
436size_t omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t bytes)
437{
438	int i, num;
439	struct cr_regs *cr;
440	char *p = buf;
441
442	num = bytes / sizeof(*cr);
443	num = min(obj->nr_tlb_entries, num);
444
445	cr = kcalloc(num, sizeof(*cr), GFP_KERNEL);
446	if (!cr)
447		return 0;
448
449	num = __dump_tlb_entries(obj, cr, num);
450	for (i = 0; i < num; i++)
451		p += iotlb_dump_cr(obj, cr + i, p);
452	kfree(cr);
453
454	return p - buf;
455}
456EXPORT_SYMBOL_GPL(omap_dump_tlb_entries);
457
458int omap_foreach_iommu_device(void *data, int (*fn)(struct device *, void *))
459{
460	return driver_for_each_device(&omap_iommu_driver.driver,
461				      NULL, data, fn);
462}
463EXPORT_SYMBOL_GPL(omap_foreach_iommu_device);
464
465#endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */
466
467/*
468 *	H/W pagetable operations
469 */
470static void flush_iopgd_range(u32 *first, u32 *last)
471{
472	/* FIXME: L2 cache should be taken care of if it exists */
473	do {
474		asm("mcr	p15, 0, %0, c7, c10, 1 @ flush_pgd"
475		    : : "r" (first));
476		first += L1_CACHE_BYTES / sizeof(*first);
477	} while (first <= last);
478}
479
480static void flush_iopte_range(u32 *first, u32 *last)
481{
482	/* FIXME: L2 cache should be taken care of if it exists */
483	do {
484		asm("mcr	p15, 0, %0, c7, c10, 1 @ flush_pte"
485		    : : "r" (first));
486		first += L1_CACHE_BYTES / sizeof(*first);
487	} while (first <= last);
488}
489
490static void iopte_free(u32 *iopte)
491{
492	/* Note: freed iopte's must be clean ready for re-use */
493	kmem_cache_free(iopte_cachep, iopte);
494}
495
496static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da)
497{
498	u32 *iopte;
499
500	/* a table has already existed */
501	if (*iopgd)
502		goto pte_ready;
503
504	/*
505	 * do the allocation outside the page table lock
506	 */
507	spin_unlock(&obj->page_table_lock);
508	iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL);
509	spin_lock(&obj->page_table_lock);
510
511	if (!*iopgd) {
512		if (!iopte)
513			return ERR_PTR(-ENOMEM);
514
515		*iopgd = virt_to_phys(iopte) | IOPGD_TABLE;
516		flush_iopgd_range(iopgd, iopgd);
517
518		dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte);
519	} else {
520		/* We raced, free the reduniovant table */
521		iopte_free(iopte);
522	}
523
524pte_ready:
525	iopte = iopte_offset(iopgd, da);
526
527	dev_vdbg(obj->dev,
528		 "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
529		 __func__, da, iopgd, *iopgd, iopte, *iopte);
530
531	return iopte;
532}
533
534static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
535{
536	u32 *iopgd = iopgd_offset(obj, da);
537
538	if ((da | pa) & ~IOSECTION_MASK) {
539		dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
540			__func__, da, pa, IOSECTION_SIZE);
541		return -EINVAL;
542	}
543
544	*iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION;
545	flush_iopgd_range(iopgd, iopgd);
546	return 0;
547}
548
549static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
550{
551	u32 *iopgd = iopgd_offset(obj, da);
552	int i;
553
554	if ((da | pa) & ~IOSUPER_MASK) {
555		dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
556			__func__, da, pa, IOSUPER_SIZE);
557		return -EINVAL;
558	}
559
560	for (i = 0; i < 16; i++)
561		*(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER;
562	flush_iopgd_range(iopgd, iopgd + 15);
563	return 0;
564}
565
566static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
567{
568	u32 *iopgd = iopgd_offset(obj, da);
569	u32 *iopte = iopte_alloc(obj, iopgd, da);
570
571	if (IS_ERR(iopte))
572		return PTR_ERR(iopte);
573
574	*iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL;
575	flush_iopte_range(iopte, iopte);
576
577	dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n",
578		 __func__, da, pa, iopte, *iopte);
579
580	return 0;
581}
582
583static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
584{
585	u32 *iopgd = iopgd_offset(obj, da);
586	u32 *iopte = iopte_alloc(obj, iopgd, da);
587	int i;
588
589	if ((da | pa) & ~IOLARGE_MASK) {
590		dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
591			__func__, da, pa, IOLARGE_SIZE);
592		return -EINVAL;
593	}
594
595	if (IS_ERR(iopte))
596		return PTR_ERR(iopte);
597
598	for (i = 0; i < 16; i++)
599		*(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE;
600	flush_iopte_range(iopte, iopte + 15);
601	return 0;
602}
603
604static int
605iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e)
606{
607	int (*fn)(struct omap_iommu *, u32, u32, u32);
608	u32 prot;
609	int err;
610
611	if (!obj || !e)
612		return -EINVAL;
613
614	switch (e->pgsz) {
615	case MMU_CAM_PGSZ_16M:
616		fn = iopgd_alloc_super;
617		break;
618	case MMU_CAM_PGSZ_1M:
619		fn = iopgd_alloc_section;
620		break;
621	case MMU_CAM_PGSZ_64K:
622		fn = iopte_alloc_large;
623		break;
624	case MMU_CAM_PGSZ_4K:
625		fn = iopte_alloc_page;
626		break;
627	default:
628		fn = NULL;
629		BUG();
630		break;
631	}
632
633	prot = get_iopte_attr(e);
634
635	spin_lock(&obj->page_table_lock);
636	err = fn(obj, e->da, e->pa, prot);
637	spin_unlock(&obj->page_table_lock);
638
639	return err;
640}
641
642/**
643 * omap_iopgtable_store_entry - Make an iommu pte entry
644 * @obj:	target iommu
645 * @e:		an iommu tlb entry info
646 **/
647int omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e)
648{
649	int err;
650
651	flush_iotlb_page(obj, e->da);
652	err = iopgtable_store_entry_core(obj, e);
653	if (!err)
654		prefetch_iotlb_entry(obj, e);
655	return err;
656}
657EXPORT_SYMBOL_GPL(omap_iopgtable_store_entry);
658
659/**
660 * iopgtable_lookup_entry - Lookup an iommu pte entry
661 * @obj:	target iommu
662 * @da:		iommu device virtual address
663 * @ppgd:	iommu pgd entry pointer to be returned
664 * @ppte:	iommu pte entry pointer to be returned
665 **/
666static void
667iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte)
668{
669	u32 *iopgd, *iopte = NULL;
670
671	iopgd = iopgd_offset(obj, da);
672	if (!*iopgd)
673		goto out;
674
675	if (iopgd_is_table(*iopgd))
676		iopte = iopte_offset(iopgd, da);
677out:
678	*ppgd = iopgd;
679	*ppte = iopte;
680}
681
682static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da)
683{
684	size_t bytes;
685	u32 *iopgd = iopgd_offset(obj, da);
686	int nent = 1;
687
688	if (!*iopgd)
689		return 0;
690
691	if (iopgd_is_table(*iopgd)) {
692		int i;
693		u32 *iopte = iopte_offset(iopgd, da);
694
695		bytes = IOPTE_SIZE;
696		if (*iopte & IOPTE_LARGE) {
697			nent *= 16;
698			/* rewind to the 1st entry */
699			iopte = iopte_offset(iopgd, (da & IOLARGE_MASK));
700		}
701		bytes *= nent;
702		memset(iopte, 0, nent * sizeof(*iopte));
703		flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte));
704
705		/*
706		 * do table walk to check if this table is necessary or not
707		 */
708		iopte = iopte_offset(iopgd, 0);
709		for (i = 0; i < PTRS_PER_IOPTE; i++)
710			if (iopte[i])
711				goto out;
712
713		iopte_free(iopte);
714		nent = 1; /* for the next L1 entry */
715	} else {
716		bytes = IOPGD_SIZE;
717		if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) {
718			nent *= 16;
719			/* rewind to the 1st entry */
720			iopgd = iopgd_offset(obj, (da & IOSUPER_MASK));
721		}
722		bytes *= nent;
723	}
724	memset(iopgd, 0, nent * sizeof(*iopgd));
725	flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd));
726out:
727	return bytes;
728}
729
730/**
731 * iopgtable_clear_entry - Remove an iommu pte entry
732 * @obj:	target iommu
733 * @da:		iommu device virtual address
734 **/
735static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da)
736{
737	size_t bytes;
738
739	spin_lock(&obj->page_table_lock);
740
741	bytes = iopgtable_clear_entry_core(obj, da);
742	flush_iotlb_page(obj, da);
743
744	spin_unlock(&obj->page_table_lock);
745
746	return bytes;
747}
748
749static void iopgtable_clear_entry_all(struct omap_iommu *obj)
750{
751	int i;
752
753	spin_lock(&obj->page_table_lock);
754
755	for (i = 0; i < PTRS_PER_IOPGD; i++) {
756		u32 da;
757		u32 *iopgd;
758
759		da = i << IOPGD_SHIFT;
760		iopgd = iopgd_offset(obj, da);
761
762		if (!*iopgd)
763			continue;
764
765		if (iopgd_is_table(*iopgd))
766			iopte_free(iopte_offset(iopgd, 0));
767
768		*iopgd = 0;
769		flush_iopgd_range(iopgd, iopgd);
770	}
771
772	flush_iotlb_all(obj);
773
774	spin_unlock(&obj->page_table_lock);
775}
776
777/*
778 *	Device IOMMU generic operations
779 */
780static irqreturn_t iommu_fault_handler(int irq, void *data)
781{
782	u32 da, errs;
783	u32 *iopgd, *iopte;
784	struct omap_iommu *obj = data;
785	struct iommu_domain *domain = obj->domain;
786
787	if (!obj->refcount)
788		return IRQ_NONE;
789
790	clk_enable(obj->clk);
791	errs = iommu_report_fault(obj, &da);
792	clk_disable(obj->clk);
793	if (errs == 0)
794		return IRQ_HANDLED;
795
796	/* Fault callback or TLB/PTE Dynamic loading */
797	if (!report_iommu_fault(domain, obj->dev, da, 0))
798		return IRQ_HANDLED;
799
800	iommu_disable(obj);
801
802	iopgd = iopgd_offset(obj, da);
803
804	if (!iopgd_is_table(*iopgd)) {
805		dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p "
806			"*pgd:px%08x\n", obj->name, errs, da, iopgd, *iopgd);
807		return IRQ_NONE;
808	}
809
810	iopte = iopte_offset(iopgd, da);
811
812	dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x "
813		"pte:0x%p *pte:0x%08x\n", obj->name, errs, da, iopgd, *iopgd,
814		iopte, *iopte);
815
816	return IRQ_NONE;
817}
818
819static int device_match_by_alias(struct device *dev, void *data)
820{
821	struct omap_iommu *obj = to_iommu(dev);
822	const char *name = data;
823
824	pr_debug("%s: %s %s\n", __func__, obj->name, name);
825
826	return strcmp(obj->name, name) == 0;
827}
828
829/**
830 * omap_iommu_attach() - attach iommu device to an iommu domain
831 * @name:	name of target omap iommu device
832 * @iopgd:	page table
833 **/
834static struct omap_iommu *omap_iommu_attach(const char *name, u32 *iopgd)
835{
836	int err = -ENOMEM;
837	struct device *dev;
838	struct omap_iommu *obj;
839
840	dev = driver_find_device(&omap_iommu_driver.driver, NULL,
841				(void *)name,
842				device_match_by_alias);
843	if (!dev)
844		return NULL;
845
846	obj = to_iommu(dev);
847
848	spin_lock(&obj->iommu_lock);
849
850	/* an iommu device can only be attached once */
851	if (++obj->refcount > 1) {
852		dev_err(dev, "%s: already attached!\n", obj->name);
853		err = -EBUSY;
854		goto err_enable;
855	}
856
857	obj->iopgd = iopgd;
858	err = iommu_enable(obj);
859	if (err)
860		goto err_enable;
861	flush_iotlb_all(obj);
862
863	if (!try_module_get(obj->owner))
864		goto err_module;
865
866	spin_unlock(&obj->iommu_lock);
867
868	dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
869	return obj;
870
871err_module:
872	if (obj->refcount == 1)
873		iommu_disable(obj);
874err_enable:
875	obj->refcount--;
876	spin_unlock(&obj->iommu_lock);
877	return ERR_PTR(err);
878}
879
880/**
881 * omap_iommu_detach - release iommu device
882 * @obj:	target iommu
883 **/
884static void omap_iommu_detach(struct omap_iommu *obj)
885{
886	if (!obj || IS_ERR(obj))
887		return;
888
889	spin_lock(&obj->iommu_lock);
890
891	if (--obj->refcount == 0)
892		iommu_disable(obj);
893
894	module_put(obj->owner);
895
896	obj->iopgd = NULL;
897
898	spin_unlock(&obj->iommu_lock);
899
900	dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
901}
902
903/*
904 *	OMAP Device MMU(IOMMU) detection
905 */
906static int __devinit omap_iommu_probe(struct platform_device *pdev)
907{
908	int err = -ENODEV;
909	int irq;
910	struct omap_iommu *obj;
911	struct resource *res;
912	struct iommu_platform_data *pdata = pdev->dev.platform_data;
913
914	if (pdev->num_resources != 2)
915		return -EINVAL;
916
917	obj = kzalloc(sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL);
918	if (!obj)
919		return -ENOMEM;
920
921	obj->clk = clk_get(&pdev->dev, pdata->clk_name);
922	if (IS_ERR(obj->clk))
923		goto err_clk;
924
925	obj->nr_tlb_entries = pdata->nr_tlb_entries;
926	obj->name = pdata->name;
927	obj->dev = &pdev->dev;
928	obj->ctx = (void *)obj + sizeof(*obj);
929	obj->da_start = pdata->da_start;
930	obj->da_end = pdata->da_end;
931
932	spin_lock_init(&obj->iommu_lock);
933	mutex_init(&obj->mmap_lock);
934	spin_lock_init(&obj->page_table_lock);
935	INIT_LIST_HEAD(&obj->mmap);
936
937	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
938	if (!res) {
939		err = -ENODEV;
940		goto err_mem;
941	}
942
943	res = request_mem_region(res->start, resource_size(res),
944				 dev_name(&pdev->dev));
945	if (!res) {
946		err = -EIO;
947		goto err_mem;
948	}
949
950	obj->regbase = ioremap(res->start, resource_size(res));
951	if (!obj->regbase) {
952		err = -ENOMEM;
953		goto err_ioremap;
954	}
955
956	irq = platform_get_irq(pdev, 0);
957	if (irq < 0) {
958		err = -ENODEV;
959		goto err_irq;
960	}
961	err = request_irq(irq, iommu_fault_handler, IRQF_SHARED,
962			  dev_name(&pdev->dev), obj);
963	if (err < 0)
964		goto err_irq;
965	platform_set_drvdata(pdev, obj);
966
967	dev_info(&pdev->dev, "%s registered\n", obj->name);
968	return 0;
969
970err_irq:
971	iounmap(obj->regbase);
972err_ioremap:
973	release_mem_region(res->start, resource_size(res));
974err_mem:
975	clk_put(obj->clk);
976err_clk:
977	kfree(obj);
978	return err;
979}
980
981static int __devexit omap_iommu_remove(struct platform_device *pdev)
982{
983	int irq;
984	struct resource *res;
985	struct omap_iommu *obj = platform_get_drvdata(pdev);
986
987	platform_set_drvdata(pdev, NULL);
988
989	iopgtable_clear_entry_all(obj);
990
991	irq = platform_get_irq(pdev, 0);
992	free_irq(irq, obj);
993	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
994	release_mem_region(res->start, resource_size(res));
995	iounmap(obj->regbase);
996
997	clk_put(obj->clk);
998	dev_info(&pdev->dev, "%s removed\n", obj->name);
999	kfree(obj);
1000	return 0;
1001}
1002
1003static struct platform_driver omap_iommu_driver = {
1004	.probe	= omap_iommu_probe,
1005	.remove	= __devexit_p(omap_iommu_remove),
1006	.driver	= {
1007		.name	= "omap-iommu",
1008	},
1009};
1010
1011static void iopte_cachep_ctor(void *iopte)
1012{
1013	clean_dcache_area(iopte, IOPTE_TABLE_SIZE);
1014}
1015
1016static int omap_iommu_map(struct iommu_domain *domain, unsigned long da,
1017			 phys_addr_t pa, size_t bytes, int prot)
1018{
1019	struct omap_iommu_domain *omap_domain = domain->priv;
1020	struct omap_iommu *oiommu = omap_domain->iommu_dev;
1021	struct device *dev = oiommu->dev;
1022	struct iotlb_entry e;
1023	int omap_pgsz;
1024	u32 ret, flags;
1025
1026	/* we only support mapping a single iommu page for now */
1027	omap_pgsz = bytes_to_iopgsz(bytes);
1028	if (omap_pgsz < 0) {
1029		dev_err(dev, "invalid size to map: %d\n", bytes);
1030		return -EINVAL;
1031	}
1032
1033	dev_dbg(dev, "mapping da 0x%lx to pa 0x%x size 0x%x\n", da, pa, bytes);
1034
1035	flags = omap_pgsz | prot;
1036
1037	iotlb_init_entry(&e, da, pa, flags);
1038
1039	ret = omap_iopgtable_store_entry(oiommu, &e);
1040	if (ret)
1041		dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", ret);
1042
1043	return ret;
1044}
1045
1046static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da,
1047			    size_t size)
1048{
1049	struct omap_iommu_domain *omap_domain = domain->priv;
1050	struct omap_iommu *oiommu = omap_domain->iommu_dev;
1051	struct device *dev = oiommu->dev;
1052
1053	dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size);
1054
1055	return iopgtable_clear_entry(oiommu, da);
1056}
1057
1058static int
1059omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
1060{
1061	struct omap_iommu_domain *omap_domain = domain->priv;
1062	struct omap_iommu *oiommu;
1063	struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1064	int ret = 0;
1065
1066	spin_lock(&omap_domain->lock);
1067
1068	/* only a single device is supported per domain for now */
1069	if (omap_domain->iommu_dev) {
1070		dev_err(dev, "iommu domain is already attached\n");
1071		ret = -EBUSY;
1072		goto out;
1073	}
1074
1075	/* get a handle to and enable the omap iommu */
1076	oiommu = omap_iommu_attach(arch_data->name, omap_domain->pgtable);
1077	if (IS_ERR(oiommu)) {
1078		ret = PTR_ERR(oiommu);
1079		dev_err(dev, "can't get omap iommu: %d\n", ret);
1080		goto out;
1081	}
1082
1083	omap_domain->iommu_dev = arch_data->iommu_dev = oiommu;
1084	oiommu->domain = domain;
1085
1086out:
1087	spin_unlock(&omap_domain->lock);
1088	return ret;
1089}
1090
1091static void omap_iommu_detach_dev(struct iommu_domain *domain,
1092				 struct device *dev)
1093{
1094	struct omap_iommu_domain *omap_domain = domain->priv;
1095	struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1096	struct omap_iommu *oiommu = dev_to_omap_iommu(dev);
1097
1098	spin_lock(&omap_domain->lock);
1099
1100	/* only a single device is supported per domain for now */
1101	if (omap_domain->iommu_dev != oiommu) {
1102		dev_err(dev, "invalid iommu device\n");
1103		goto out;
1104	}
1105
1106	iopgtable_clear_entry_all(oiommu);
1107
1108	omap_iommu_detach(oiommu);
1109
1110	omap_domain->iommu_dev = arch_data->iommu_dev = NULL;
1111
1112out:
1113	spin_unlock(&omap_domain->lock);
1114}
1115
1116static int omap_iommu_domain_init(struct iommu_domain *domain)
1117{
1118	struct omap_iommu_domain *omap_domain;
1119
1120	omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL);
1121	if (!omap_domain) {
1122		pr_err("kzalloc failed\n");
1123		goto out;
1124	}
1125
1126	omap_domain->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_KERNEL);
1127	if (!omap_domain->pgtable) {
1128		pr_err("kzalloc failed\n");
1129		goto fail_nomem;
1130	}
1131
1132	/*
1133	 * should never fail, but please keep this around to ensure
1134	 * we keep the hardware happy
1135	 */
1136	BUG_ON(!IS_ALIGNED((long)omap_domain->pgtable, IOPGD_TABLE_SIZE));
1137
1138	clean_dcache_area(omap_domain->pgtable, IOPGD_TABLE_SIZE);
1139	spin_lock_init(&omap_domain->lock);
1140
1141	domain->priv = omap_domain;
1142
1143	return 0;
1144
1145fail_nomem:
1146	kfree(omap_domain);
1147out:
1148	return -ENOMEM;
1149}
1150
1151/* assume device was already detached */
1152static void omap_iommu_domain_destroy(struct iommu_domain *domain)
1153{
1154	struct omap_iommu_domain *omap_domain = domain->priv;
1155
1156	domain->priv = NULL;
1157
1158	kfree(omap_domain->pgtable);
1159	kfree(omap_domain);
1160}
1161
1162static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain,
1163					  unsigned long da)
1164{
1165	struct omap_iommu_domain *omap_domain = domain->priv;
1166	struct omap_iommu *oiommu = omap_domain->iommu_dev;
1167	struct device *dev = oiommu->dev;
1168	u32 *pgd, *pte;
1169	phys_addr_t ret = 0;
1170
1171	iopgtable_lookup_entry(oiommu, da, &pgd, &pte);
1172
1173	if (pte) {
1174		if (iopte_is_small(*pte))
1175			ret = omap_iommu_translate(*pte, da, IOPTE_MASK);
1176		else if (iopte_is_large(*pte))
1177			ret = omap_iommu_translate(*pte, da, IOLARGE_MASK);
1178		else
1179			dev_err(dev, "bogus pte 0x%x, da 0x%lx", *pte, da);
1180	} else {
1181		if (iopgd_is_section(*pgd))
1182			ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK);
1183		else if (iopgd_is_super(*pgd))
1184			ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK);
1185		else
1186			dev_err(dev, "bogus pgd 0x%x, da 0x%lx", *pgd, da);
1187	}
1188
1189	return ret;
1190}
1191
1192static int omap_iommu_domain_has_cap(struct iommu_domain *domain,
1193				    unsigned long cap)
1194{
1195	return 0;
1196}
1197
1198static struct iommu_ops omap_iommu_ops = {
1199	.domain_init	= omap_iommu_domain_init,
1200	.domain_destroy	= omap_iommu_domain_destroy,
1201	.attach_dev	= omap_iommu_attach_dev,
1202	.detach_dev	= omap_iommu_detach_dev,
1203	.map		= omap_iommu_map,
1204	.unmap		= omap_iommu_unmap,
1205	.iova_to_phys	= omap_iommu_iova_to_phys,
1206	.domain_has_cap	= omap_iommu_domain_has_cap,
1207	.pgsize_bitmap	= OMAP_IOMMU_PGSIZES,
1208};
1209
1210static int __init omap_iommu_init(void)
1211{
1212	struct kmem_cache *p;
1213	const unsigned long flags = SLAB_HWCACHE_ALIGN;
1214	size_t align = 1 << 10; /* L2 pagetable alignement */
1215
1216	p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags,
1217			      iopte_cachep_ctor);
1218	if (!p)
1219		return -ENOMEM;
1220	iopte_cachep = p;
1221
1222	bus_set_iommu(&platform_bus_type, &omap_iommu_ops);
1223
1224	return platform_driver_register(&omap_iommu_driver);
1225}
1226/* must be ready before omap3isp is probed */
1227subsys_initcall(omap_iommu_init);
1228
1229static void __exit omap_iommu_exit(void)
1230{
1231	kmem_cache_destroy(iopte_cachep);
1232
1233	platform_driver_unregister(&omap_iommu_driver);
1234}
1235module_exit(omap_iommu_exit);
1236
1237MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives");
1238MODULE_ALIAS("platform:omap-iommu");
1239MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
1240MODULE_LICENSE("GPL v2");
1241