/drivers/net/ethernet/amd/ |
H A D | sun3lance.c | 202 #define CSR0 0 /* mode/status */ macro 209 /* CSR0 */ 331 ioaddr_probe[1] = CSR0; 359 REGA(CSR0) = CSR0_STOP; 424 REGA(CSR0) = CSR0_STOP; 428 /* From now on, AREG is kept to point to CSR0 */ 429 REGA(CSR0) = CSR0_INIT; 559 REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT; 581 AREG = CSR0; 589 REGA( CSR0 ) [all...] |
H A D | am79c961a.c | 247 write_rreg (dev->base_addr, CSR0, CSR0_BABL|CSR0_CERR|CSR0_MISS|CSR0_MERR|CSR0_TINT|CSR0_RINT|CSR0_STOP); 299 write_rreg (dev->base_addr, CSR0, CSR0_STOP); 302 write_rreg (dev->base_addr, CSR0, CSR0_IENA|CSR0_STRT); 368 write_rreg (dev->base_addr, CSR0, CSR0_STOP); 389 stopped = read_rreg(dev->base_addr, CSR0) & CSR0_STOP; 464 write_rreg (dev->base_addr, CSR0, CSR0_TDMD|CSR0_IENA); 597 status = read_rreg(dev->base_addr, CSR0); 598 write_rreg(dev->base_addr, CSR0, status & 643 write_rreg (dev->base_addr, CSR0, CSR0_STOP);
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H A D | pcnet32.c | 196 #define CSR0 0 macro 797 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ 893 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ 907 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */ 955 lp->a->write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */ 974 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */ 1347 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN); 1376 csr0 = a->read_csr(ioaddr, CSR0); 1829 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT); 2183 lp->a->write_csr(ioaddr, CSR0, CSR0_INI [all...] |
H A D | ariadne.c | 247 lance->RAP = CSR0; /* PCnet-ISA Controller Status */ 382 lance->RAP = CSR0; /* PCnet-ISA Controller Status */ 403 lance->RAP = CSR0; /* PCnet-ISA Controller Status */ 491 lance->RAP = CSR0; /* PCnet-ISA Controller Status */ 505 lance->RAP = CSR0; /* PCnet-ISA Controller Status */ 526 lance->RAP = CSR0; /* PCnet-ISA Controller Status */ 554 lance->RAP = CSR0; /* PCnet-ISA Controller Status */ 609 lance->RAP = CSR0; /* PCnet-ISA Controller Status */ 653 lance->RAP = CSR0; /* PCnet-ISA Controller Status */ 678 lance->RAP = CSR0; /* PCne [all...] |
H A D | am79c961a.h | 30 #define CSR0 0 macro
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H A D | atarilance.c | 20 optimized register access (keep AREG pointing to CSR0) 303 #define CSR0 0 /* mode/status */ macro 310 /* CSR0 */ 507 PROBE_PRINT(( "lance_probe1: testing CSR0 register function (1)\n" )); 509 ioaddr[1] = CSR0; 516 PROBE_PRINT(( "lance_probe1: testing CSR0 register function (2)\n" )); 538 REGA( CSR0 ) = CSR0_STOP; 658 REGA( CSR0 ) = CSR0_INIT; 659 /* From now on, AREG is kept to point to CSR0 */ 738 AREG = CSR0; [all...] |
H A D | depca.h | 25 #define CSR0 0 macro 46 ** Control and Status Register 0 (CSR0) bit definitions
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H A D | ni65.c | 150 #define CSR0 0x00 macro 166 #define writedatareg(val) { writereg(val,CSR0); } 171 #define writedatareg(val) { writereg(val,CSR0); } 273 writereg(CSR0_STOP | CSR0_CLRALL,CSR0); /* STOP */ 288 outw(CSR0,PORT+L_ADDRREG); /* switch back to CSR0 */ 464 if( (j=readreg(CSR0)) != 0x4) { 516 if(readreg(CSR0) & CSR0_IDON) 538 writereg(CSR0_INIT|CSR0_INEA,CSR0); /* trigger interrupt */ 577 writereg(CSR0_CLRALL|CSR0_STOP,CSR0); [all...] |
H A D | depca.c | 568 outw(CSR0, DEPCA_ADDR);\ 860 outw(CSR0, DEPCA_ADDR); 867 printk("CSR0: 0x%4.4x\n", inw(DEPCA_DATA)); 954 outw(CSR0, DEPCA_ADDR); 993 outw(CSR0, DEPCA_ADDR); 1141 outw(CSR0, DEPCA_ADDR); 1165 outw(CSR0, DEPCA_ADDR); 1205 outw(CSR0, DEPCA_ADDR); /* Point back to CSR0 */ 1217 outw(CSR0, DEPCA_ADD [all...] |
H A D | ariadne.h | 62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */ macro 174 * Bit definitions for CSR0 (PCnet-ISA Controller Status)
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/drivers/net/wan/ |
H A D | sbni.c | 359 outb( 0, ioaddr + CSR0 ); 365 outb( EN_INT | TR_REQ, ioaddr + CSR0 ); 369 outb( 0, ioaddr + CSR0 ); 411 if( inb( ioaddr + CSR0 ) & 0x01 ) 517 if( inb( dev->base_addr + CSR0 ) & (RC_RDY | TR_RDY) ) 521 (inb( nl->second->base_addr+CSR0 ) & (RC_RDY | TR_RDY)) ) 548 outb( (inb( ioaddr + CSR0 ) & ~EN_INT) | TR_REQ, ioaddr + CSR0 ); 552 csr0 = inb( ioaddr + CSR0 ); 565 csr0 = inb( ioaddr + CSR0 ); 574 outb( inb( ioaddr + CSR0 ) & ~TR_REQ, ioaddr + CSR0 ); local 577 outb( inb( ioaddr + CSR0 ) | EN_INT, ioaddr + CSR0 ); local 610 outb( inb( ioaddr + CSR0 ) ^ CT_ZER, ioaddr + CSR0 ); local [all...] |
H A D | sbni.h | 26 CSR0 = 0, enumerator in enum:sbni_reg 31 /* CSR0 mapping */
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/drivers/net/ethernet/dec/tulip/ |
H A D | xircom_cb.c | 47 #define CSR0 0x00 macro 95 CSR0, CSR6, CSR7, CSR9, CSR10, CSR15 487 val = inl(card->io_port + CSR0); 489 outl(val, card->io_port + CSR0); 493 val = inl(card->io_port + CSR0); 495 outl(val, card->io_port + CSR0); 500 outl(val, card->io_port + CSR0);
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H A D | tulip.h | 106 CSR0 = 0, enumerator in enum:tulip_offsets 437 unsigned int csr0; /* CSR0 setting. */
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H A D | tulip_core.c | 319 iowrite32(0x00000001, ioaddr + CSR0); 326 iowrite32(tp->csr0, ioaddr + CSR0); 498 netdev_dbg(dev, "Done tulip_up(), CSR0 %08x, CSR5 %08x CSR6 %08x\n", 499 ioread32(ioaddr + CSR0),
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/drivers/spi/ |
H A D | spi-atmel.c | 112 /* Bitfields in CSR0 */ 254 * AT91RM9200 if we use some other register than CSR0. However, don't 256 * field in CSR0 overrides all other CSRs. 267 * Always use CSR0. This ensures that the clock 271 spi_writel(as, CSR0, asd->csr); 283 csr = spi_readl(as, CSR0 + 4 * i); 285 spi_writel(as, CSR0 + 4 * i, 803 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
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/drivers/net/wireless/rt2x00/ |
H A D | rt2400pci.h | 65 * CSR0: ASIC revision number. 67 #define CSR0 0x0000 macro
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H A D | rt2500pci.h | 76 * CSR0: ASIC revision number. 78 #define CSR0 0x0000 macro
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H A D | rt2400pci.c | 1486 rt2x00pci_register_read(rt2x00dev, CSR0, ®);
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H A D | rt2500pci.c | 1643 rt2x00pci_register_read(rt2x00dev, CSR0, ®);
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