Searched refs:CSR12 (Results 1 - 15 of 15) sorted by relevance

/drivers/net/ethernet/dec/tulip/
H A Dpnic.c33 iowrite32(0x32 | (dev->if_port & 1), ioaddr + CSR12);
71 iowrite32(0x30, ioaddr + CSR12);
109 int csr12 = ioread32(ioaddr + CSR12);
126 netdev_dbg(dev, "%s link beat failed, CSR12 %04x, CSR5 %08x, PHY %03x\n",
137 iowrite32(0x33, ioaddr + CSR12);
142 iowrite32(0x32, ioaddr + CSR12);
H A Dpnic2.c88 ioread32(ioaddr + CSR12));
163 csr12 = (ioread32(ioaddr + CSR12) & 0xffff8fff);
165 iowrite32(csr12, ioaddr + CSR12);
177 int csr12 = ioread32(ioaddr + CSR12);
270 netdev_dbg(dev, "Setting CSR6 %08x/%x CSR12 %08x\n",
273 ioread32(ioaddr + CSR12));
H A Dmedia.c186 iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12);
187 iowrite32(p[1], ioaddr + CSR12);
286 iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12);
288 iowrite32(reset_sequence[i], ioaddr + CSR12);
291 ioread32(ioaddr + CSR12);
303 iowrite32(init_sequence[i], ioaddr + CSR12);
305 ioread32(ioaddr + CSR12); /* flush posted writes */
347 netdev_dbg(dev, "Using media type %s, CSR12 is %02x\n",
349 ioread32(ioaddr + CSR12) & 0xff);
363 iowrite32(0x32, ioaddr + CSR12);
[all...]
H A D21142.c34 int csr12 = ioread32(ioaddr + CSR12);
39 /* CSR12[LS10,LS100] are not reliable during autonegotiation */
98 iowrite32(0x0301, ioaddr + CSR12);
134 iowrite32(0x1301, ioaddr + CSR12); /* Trigger NWAY. */
143 int csr12 = ioread32(ioaddr + CSR12);
146 /* CSR12[LS10,LS100] are not reliable during autonegotiation */
211 netdev_dbg(dev, " Setting CSR6 %08x/%x CSR12 %08x\n",
213 ioread32(ioaddr + CSR12));
252 iowrite32(0x0301, ioaddr + CSR12);
H A Dtimer.c23 u32 csr12 = ioread32(ioaddr + CSR12);
48 netdev_dbg(dev, "network media monitor CSR6 %08x CSR12 0x%02x\n",
62 netdev_dbg(dev, "Transceiver monitor tick CSR12=%#02x, no media sense\n",
71 netdev_dbg(dev, "Transceiver monitor tick: CSR12=%#02x bit %d is %d, expecting %d\n",
149 ioread32(ioaddr + CSR12));
H A Dinterrupt.c487 int csr12 = ioread32(tp->base_addr + CSR12) & 0xff;
491 iowrite32(csr12 | 0x02, tp->base_addr + CSR12);
498 iowrite32(csr12 & ~0x02, tp->base_addr + CSR12);
H A Dtulip_core.c458 iowrite32(0x32, ioaddr + CSR12);
556 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12),
564 "PNIC2 transmit timed out, status %08x, CSR6/7 %08x / %08x CSR12 %08x, resetting...\n",
568 (int)ioread32(ioaddr + CSR12));
571 "Transmit timed out, status %08x, CSR12 %08x, resetting...\n",
572 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12));
932 int csr12 = ioread32 (ioaddr + CSR12);
1747 iowrite32(tp->mtable->csr12dir | 0x100, ioaddr + CSR12);
1768 iowrite32(0x30, ioaddr + CSR12);
1783 iowrite32(0x00001000, ioaddr + CSR12);
[all...]
H A Dtulip.h118 CSR12 = 0x60, enumerator in enum:tulip_offsets
H A Dxircom_cb.c59 #define CSR12 0x60 macro
617 the link status has changed. The new link status has to be read from CSR12.
949 val = inb(card->io_port + CSR12);
/drivers/net/ethernet/amd/
H A Dariadne.h72 #define CSR12 0x0c00 /* - Physical Address Register, PADR[15:0] */ macro
H A Dariadne.c443 lance->RAP = CSR12; /* Physical Address Register, PADR[15:0] */
/drivers/net/wireless/rt2x00/
H A Drt2400pci.h181 * CSR12: Synchronization configuration register 0.
186 #define CSR12 0x0030 macro
H A Drt2500pci.h258 * CSR12: Synchronization configuration register 0.
263 #define CSR12 0x0030 macro
H A Drt2400pci.c390 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
395 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
H A Drt2500pci.c396 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
401 rt2x00pci_register_write(rt2x00dev, CSR12, reg);

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