1/* 2 * OMAP2/3 System Control Module register access 3 * 4 * Copyright (C) 2007 Texas Instruments, Inc. 5 * Copyright (C) 2007 Nokia Corporation 6 * 7 * Written by Paul Walmsley 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13#undef DEBUG 14 15#include <linux/kernel.h> 16#include <linux/io.h> 17 18#include <plat/hardware.h> 19#include <plat/sdrc.h> 20 21#include "iomap.h" 22#include "common.h" 23#include "cm-regbits-34xx.h" 24#include "prm-regbits-34xx.h" 25#include "prm2xxx_3xxx.h" 26#include "cm2xxx_3xxx.h" 27#include "sdrc.h" 28#include "pm.h" 29#include "control.h" 30 31/* Used by omap3_ctrl_save_padconf() */ 32#define START_PADCONF_SAVE 0x2 33#define PADCONF_SAVE_DONE 0x1 34 35static void __iomem *omap2_ctrl_base; 36static void __iomem *omap4_ctrl_pad_base; 37 38#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 39struct omap3_scratchpad { 40 u32 boot_config_ptr; 41 u32 public_restore_ptr; 42 u32 secure_ram_restore_ptr; 43 u32 sdrc_module_semaphore; 44 u32 prcm_block_offset; 45 u32 sdrc_block_offset; 46}; 47 48struct omap3_scratchpad_prcm_block { 49 u32 prm_clksrc_ctrl; 50 u32 prm_clksel; 51 u32 cm_clksel_core; 52 u32 cm_clksel_wkup; 53 u32 cm_clken_pll; 54 u32 cm_autoidle_pll; 55 u32 cm_clksel1_pll; 56 u32 cm_clksel2_pll; 57 u32 cm_clksel3_pll; 58 u32 cm_clken_pll_mpu; 59 u32 cm_autoidle_pll_mpu; 60 u32 cm_clksel1_pll_mpu; 61 u32 cm_clksel2_pll_mpu; 62 u32 prcm_block_size; 63}; 64 65struct omap3_scratchpad_sdrc_block { 66 u16 sysconfig; 67 u16 cs_cfg; 68 u16 sharing; 69 u16 err_type; 70 u32 dll_a_ctrl; 71 u32 dll_b_ctrl; 72 u32 power; 73 u32 cs_0; 74 u32 mcfg_0; 75 u16 mr_0; 76 u16 emr_1_0; 77 u16 emr_2_0; 78 u16 emr_3_0; 79 u32 actim_ctrla_0; 80 u32 actim_ctrlb_0; 81 u32 rfr_ctrl_0; 82 u32 cs_1; 83 u32 mcfg_1; 84 u16 mr_1; 85 u16 emr_1_1; 86 u16 emr_2_1; 87 u16 emr_3_1; 88 u32 actim_ctrla_1; 89 u32 actim_ctrlb_1; 90 u32 rfr_ctrl_1; 91 u16 dcdl_1_ctrl; 92 u16 dcdl_2_ctrl; 93 u32 flags; 94 u32 block_size; 95}; 96 97void *omap3_secure_ram_storage; 98 99/* 100 * This is used to store ARM registers in SDRAM before attempting 101 * an MPU OFF. The save and restore happens from the SRAM sleep code. 102 * The address is stored in scratchpad, so that it can be used 103 * during the restore path. 104 */ 105u32 omap3_arm_context[128]; 106 107struct omap3_control_regs { 108 u32 sysconfig; 109 u32 devconf0; 110 u32 mem_dftrw0; 111 u32 mem_dftrw1; 112 u32 msuspendmux_0; 113 u32 msuspendmux_1; 114 u32 msuspendmux_2; 115 u32 msuspendmux_3; 116 u32 msuspendmux_4; 117 u32 msuspendmux_5; 118 u32 sec_ctrl; 119 u32 devconf1; 120 u32 csirxfe; 121 u32 iva2_bootaddr; 122 u32 iva2_bootmod; 123 u32 debobs_0; 124 u32 debobs_1; 125 u32 debobs_2; 126 u32 debobs_3; 127 u32 debobs_4; 128 u32 debobs_5; 129 u32 debobs_6; 130 u32 debobs_7; 131 u32 debobs_8; 132 u32 prog_io0; 133 u32 prog_io1; 134 u32 dss_dpll_spreading; 135 u32 core_dpll_spreading; 136 u32 per_dpll_spreading; 137 u32 usbhost_dpll_spreading; 138 u32 pbias_lite; 139 u32 temp_sensor; 140 u32 sramldo4; 141 u32 sramldo5; 142 u32 csi; 143 u32 padconf_sys_nirq; 144}; 145 146static struct omap3_control_regs control_context; 147#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 148 149#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg)) 150#define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg)) 151 152void __init omap2_set_globals_control(struct omap_globals *omap2_globals) 153{ 154 if (omap2_globals->ctrl) 155 omap2_ctrl_base = omap2_globals->ctrl; 156 157 if (omap2_globals->ctrl_pad) 158 omap4_ctrl_pad_base = omap2_globals->ctrl_pad; 159} 160 161void __iomem *omap_ctrl_base_get(void) 162{ 163 return omap2_ctrl_base; 164} 165 166u8 omap_ctrl_readb(u16 offset) 167{ 168 return __raw_readb(OMAP_CTRL_REGADDR(offset)); 169} 170 171u16 omap_ctrl_readw(u16 offset) 172{ 173 return __raw_readw(OMAP_CTRL_REGADDR(offset)); 174} 175 176u32 omap_ctrl_readl(u16 offset) 177{ 178 return __raw_readl(OMAP_CTRL_REGADDR(offset)); 179} 180 181void omap_ctrl_writeb(u8 val, u16 offset) 182{ 183 __raw_writeb(val, OMAP_CTRL_REGADDR(offset)); 184} 185 186void omap_ctrl_writew(u16 val, u16 offset) 187{ 188 __raw_writew(val, OMAP_CTRL_REGADDR(offset)); 189} 190 191void omap_ctrl_writel(u32 val, u16 offset) 192{ 193 __raw_writel(val, OMAP_CTRL_REGADDR(offset)); 194} 195 196/* 197 * On OMAP4 control pad are not addressable from control 198 * core base. So the common omap_ctrl_read/write APIs breaks 199 * Hence export separate APIs to manage the omap4 pad control 200 * registers. This APIs will work only for OMAP4 201 */ 202 203u32 omap4_ctrl_pad_readl(u16 offset) 204{ 205 return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset)); 206} 207 208void omap4_ctrl_pad_writel(u32 val, u16 offset) 209{ 210 __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset)); 211} 212 213#ifdef CONFIG_ARCH_OMAP3 214 215/** 216 * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot 217 * @bootmode: 8-bit value to pass to some boot code 218 * 219 * Set the bootmode in the scratchpad RAM. This is used after the 220 * system restarts. Not sure what actually uses this - it may be the 221 * bootloader, rather than the boot ROM - contrary to the preserved 222 * comment below. No return value. 223 */ 224void omap3_ctrl_write_boot_mode(u8 bootmode) 225{ 226 u32 l; 227 228 l = ('B' << 24) | ('M' << 16) | bootmode; 229 230 /* 231 * Reserve the first word in scratchpad for communicating 232 * with the boot ROM. A pointer to a data structure 233 * describing the boot process can be stored there, 234 * cf. OMAP34xx TRM, Initialization / Software Booting 235 * Configuration. 236 * 237 * XXX This should use some omap_ctrl_writel()-type function 238 */ 239 __raw_writel(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4)); 240} 241 242#endif 243 244#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 245/* 246 * Clears the scratchpad contents in case of cold boot- 247 * called during bootup 248 */ 249void omap3_clear_scratchpad_contents(void) 250{ 251 u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET; 252 void __iomem *v_addr; 253 u32 offset = 0; 254 v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); 255 if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & 256 OMAP3430_GLOBAL_COLD_RST_MASK) { 257 for ( ; offset <= max_offset; offset += 0x4) 258 __raw_writel(0x0, (v_addr + offset)); 259 omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK, 260 OMAP3430_GR_MOD, 261 OMAP3_PRM_RSTST_OFFSET); 262 } 263} 264 265/* Populate the scratchpad structure with restore structure */ 266void omap3_save_scratchpad_contents(void) 267{ 268 void __iomem *scratchpad_address; 269 u32 arm_context_addr; 270 struct omap3_scratchpad scratchpad_contents; 271 struct omap3_scratchpad_prcm_block prcm_block_contents; 272 struct omap3_scratchpad_sdrc_block sdrc_block_contents; 273 274 /* 275 * Populate the Scratchpad contents 276 * 277 * The "get_*restore_pointer" functions are used to provide a 278 * physical restore address where the ROM code jumps while waking 279 * up from MPU OFF/OSWR state. 280 * The restore pointer is stored into the scratchpad. 281 */ 282 scratchpad_contents.boot_config_ptr = 0x0; 283 if (cpu_is_omap3630()) 284 scratchpad_contents.public_restore_ptr = 285 virt_to_phys(omap3_restore_3630); 286 else if (omap_rev() != OMAP3430_REV_ES3_0 && 287 omap_rev() != OMAP3430_REV_ES3_1) 288 scratchpad_contents.public_restore_ptr = 289 virt_to_phys(omap3_restore); 290 else 291 scratchpad_contents.public_restore_ptr = 292 virt_to_phys(omap3_restore_es3); 293 294 if (omap_type() == OMAP2_DEVICE_TYPE_GP) 295 scratchpad_contents.secure_ram_restore_ptr = 0x0; 296 else 297 scratchpad_contents.secure_ram_restore_ptr = 298 (u32) __pa(omap3_secure_ram_storage); 299 scratchpad_contents.sdrc_module_semaphore = 0x0; 300 scratchpad_contents.prcm_block_offset = 0x2C; 301 scratchpad_contents.sdrc_block_offset = 0x64; 302 303 /* Populate the PRCM block contents */ 304 prcm_block_contents.prm_clksrc_ctrl = 305 omap2_prm_read_mod_reg(OMAP3430_GR_MOD, 306 OMAP3_PRM_CLKSRC_CTRL_OFFSET); 307 prcm_block_contents.prm_clksel = 308 omap2_prm_read_mod_reg(OMAP3430_CCR_MOD, 309 OMAP3_PRM_CLKSEL_OFFSET); 310 prcm_block_contents.cm_clksel_core = 311 omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL); 312 prcm_block_contents.cm_clksel_wkup = 313 omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); 314 prcm_block_contents.cm_clken_pll = 315 omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); 316 /* 317 * As per erratum i671, ROM code does not respect the PER DPLL 318 * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1. 319 * Then, in anycase, clear these bits to avoid extra latencies. 320 */ 321 prcm_block_contents.cm_autoidle_pll = 322 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) & 323 ~OMAP3430_AUTO_PERIPH_DPLL_MASK; 324 prcm_block_contents.cm_clksel1_pll = 325 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL); 326 prcm_block_contents.cm_clksel2_pll = 327 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL); 328 prcm_block_contents.cm_clksel3_pll = 329 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3); 330 prcm_block_contents.cm_clken_pll_mpu = 331 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL); 332 prcm_block_contents.cm_autoidle_pll_mpu = 333 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL); 334 prcm_block_contents.cm_clksel1_pll_mpu = 335 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL); 336 prcm_block_contents.cm_clksel2_pll_mpu = 337 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL); 338 prcm_block_contents.prcm_block_size = 0x0; 339 340 /* Populate the SDRC block contents */ 341 sdrc_block_contents.sysconfig = 342 (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF); 343 sdrc_block_contents.cs_cfg = 344 (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF); 345 sdrc_block_contents.sharing = 346 (sdrc_read_reg(SDRC_SHARING) & 0xFFFF); 347 sdrc_block_contents.err_type = 348 (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF); 349 sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL); 350 sdrc_block_contents.dll_b_ctrl = 0x0; 351 /* 352 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should 353 * be programed to issue automatic self refresh on timeout 354 * of AUTO_CNT = 1 prior to any transition to OFF mode. 355 */ 356 if ((omap_type() != OMAP2_DEVICE_TYPE_GP) 357 && (omap_rev() >= OMAP3430_REV_ES3_0)) 358 sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) & 359 ~(SDRC_POWER_AUTOCOUNT_MASK| 360 SDRC_POWER_CLKCTRL_MASK)) | 361 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) | 362 SDRC_SELF_REFRESH_ON_AUTOCOUNT; 363 else 364 sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER); 365 366 sdrc_block_contents.cs_0 = 0x0; 367 sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0); 368 sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF); 369 sdrc_block_contents.emr_1_0 = 0x0; 370 sdrc_block_contents.emr_2_0 = 0x0; 371 sdrc_block_contents.emr_3_0 = 0x0; 372 sdrc_block_contents.actim_ctrla_0 = 373 sdrc_read_reg(SDRC_ACTIM_CTRL_A_0); 374 sdrc_block_contents.actim_ctrlb_0 = 375 sdrc_read_reg(SDRC_ACTIM_CTRL_B_0); 376 sdrc_block_contents.rfr_ctrl_0 = 377 sdrc_read_reg(SDRC_RFR_CTRL_0); 378 sdrc_block_contents.cs_1 = 0x0; 379 sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1); 380 sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF; 381 sdrc_block_contents.emr_1_1 = 0x0; 382 sdrc_block_contents.emr_2_1 = 0x0; 383 sdrc_block_contents.emr_3_1 = 0x0; 384 sdrc_block_contents.actim_ctrla_1 = 385 sdrc_read_reg(SDRC_ACTIM_CTRL_A_1); 386 sdrc_block_contents.actim_ctrlb_1 = 387 sdrc_read_reg(SDRC_ACTIM_CTRL_B_1); 388 sdrc_block_contents.rfr_ctrl_1 = 389 sdrc_read_reg(SDRC_RFR_CTRL_1); 390 sdrc_block_contents.dcdl_1_ctrl = 0x0; 391 sdrc_block_contents.dcdl_2_ctrl = 0x0; 392 sdrc_block_contents.flags = 0x0; 393 sdrc_block_contents.block_size = 0x0; 394 395 arm_context_addr = virt_to_phys(omap3_arm_context); 396 397 /* Copy all the contents to the scratchpad location */ 398 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); 399 memcpy_toio(scratchpad_address, &scratchpad_contents, 400 sizeof(scratchpad_contents)); 401 /* Scratchpad contents being 32 bits, a divide by 4 done here */ 402 memcpy_toio(scratchpad_address + 403 scratchpad_contents.prcm_block_offset, 404 &prcm_block_contents, sizeof(prcm_block_contents)); 405 memcpy_toio(scratchpad_address + 406 scratchpad_contents.sdrc_block_offset, 407 &sdrc_block_contents, sizeof(sdrc_block_contents)); 408 /* 409 * Copies the address of the location in SDRAM where ARM 410 * registers get saved during a MPU OFF transition. 411 */ 412 memcpy_toio(scratchpad_address + 413 scratchpad_contents.sdrc_block_offset + 414 sizeof(sdrc_block_contents), &arm_context_addr, 4); 415} 416 417void omap3_control_save_context(void) 418{ 419 control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG); 420 control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); 421 control_context.mem_dftrw0 = 422 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0); 423 control_context.mem_dftrw1 = 424 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1); 425 control_context.msuspendmux_0 = 426 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0); 427 control_context.msuspendmux_1 = 428 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1); 429 control_context.msuspendmux_2 = 430 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2); 431 control_context.msuspendmux_3 = 432 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3); 433 control_context.msuspendmux_4 = 434 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4); 435 control_context.msuspendmux_5 = 436 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5); 437 control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL); 438 control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1); 439 control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE); 440 control_context.iva2_bootaddr = 441 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR); 442 control_context.iva2_bootmod = 443 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD); 444 control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0)); 445 control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1)); 446 control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2)); 447 control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3)); 448 control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4)); 449 control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5)); 450 control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6)); 451 control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7)); 452 control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8)); 453 control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0); 454 control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1); 455 control_context.dss_dpll_spreading = 456 omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING); 457 control_context.core_dpll_spreading = 458 omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING); 459 control_context.per_dpll_spreading = 460 omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING); 461 control_context.usbhost_dpll_spreading = 462 omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); 463 control_context.pbias_lite = 464 omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE); 465 control_context.temp_sensor = 466 omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR); 467 control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4); 468 control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5); 469 control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI); 470 control_context.padconf_sys_nirq = 471 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ); 472 return; 473} 474 475void omap3_control_restore_context(void) 476{ 477 omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG); 478 omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0); 479 omap_ctrl_writel(control_context.mem_dftrw0, 480 OMAP343X_CONTROL_MEM_DFTRW0); 481 omap_ctrl_writel(control_context.mem_dftrw1, 482 OMAP343X_CONTROL_MEM_DFTRW1); 483 omap_ctrl_writel(control_context.msuspendmux_0, 484 OMAP2_CONTROL_MSUSPENDMUX_0); 485 omap_ctrl_writel(control_context.msuspendmux_1, 486 OMAP2_CONTROL_MSUSPENDMUX_1); 487 omap_ctrl_writel(control_context.msuspendmux_2, 488 OMAP2_CONTROL_MSUSPENDMUX_2); 489 omap_ctrl_writel(control_context.msuspendmux_3, 490 OMAP2_CONTROL_MSUSPENDMUX_3); 491 omap_ctrl_writel(control_context.msuspendmux_4, 492 OMAP2_CONTROL_MSUSPENDMUX_4); 493 omap_ctrl_writel(control_context.msuspendmux_5, 494 OMAP2_CONTROL_MSUSPENDMUX_5); 495 omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL); 496 omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1); 497 omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE); 498 omap_ctrl_writel(control_context.iva2_bootaddr, 499 OMAP343X_CONTROL_IVA2_BOOTADDR); 500 omap_ctrl_writel(control_context.iva2_bootmod, 501 OMAP343X_CONTROL_IVA2_BOOTMOD); 502 omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0)); 503 omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1)); 504 omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2)); 505 omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3)); 506 omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4)); 507 omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5)); 508 omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6)); 509 omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7)); 510 omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8)); 511 omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0); 512 omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1); 513 omap_ctrl_writel(control_context.dss_dpll_spreading, 514 OMAP343X_CONTROL_DSS_DPLL_SPREADING); 515 omap_ctrl_writel(control_context.core_dpll_spreading, 516 OMAP343X_CONTROL_CORE_DPLL_SPREADING); 517 omap_ctrl_writel(control_context.per_dpll_spreading, 518 OMAP343X_CONTROL_PER_DPLL_SPREADING); 519 omap_ctrl_writel(control_context.usbhost_dpll_spreading, 520 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); 521 omap_ctrl_writel(control_context.pbias_lite, 522 OMAP343X_CONTROL_PBIAS_LITE); 523 omap_ctrl_writel(control_context.temp_sensor, 524 OMAP343X_CONTROL_TEMP_SENSOR); 525 omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4); 526 omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5); 527 omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI); 528 omap_ctrl_writel(control_context.padconf_sys_nirq, 529 OMAP343X_CONTROL_PADCONF_SYSNIRQ); 530 return; 531} 532 533void omap3630_ctrl_disable_rta(void) 534{ 535 if (!cpu_is_omap3630()) 536 return; 537 omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL); 538} 539 540/** 541 * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM 542 * 543 * Tell the SCM to start saving the padconf registers, then wait for 544 * the process to complete. Returns 0 unconditionally, although it 545 * should also eventually be able to return -ETIMEDOUT, if the save 546 * does not complete. 547 * 548 * XXX This function is missing a timeout. What should it be? 549 */ 550int omap3_ctrl_save_padconf(void) 551{ 552 u32 cpo; 553 554 /* Save the padconf registers */ 555 cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); 556 cpo |= START_PADCONF_SAVE; 557 omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF); 558 559 /* wait for the save to complete */ 560 while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) 561 & PADCONF_SAVE_DONE)) 562 udelay(1); 563 564 return 0; 565} 566 567#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 568