1/* 2 * linux/arch/arm/mach-omap2/hsmmc.c 3 * 4 * Copyright (C) 2007-2008 Texas Instruments 5 * Copyright (C) 2008 Nokia Corporation 6 * Author: Texas Instruments 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12#include <linux/kernel.h> 13#include <linux/slab.h> 14#include <linux/string.h> 15#include <linux/delay.h> 16#include <linux/gpio.h> 17#include <mach/hardware.h> 18#include <plat/mmc.h> 19#include <plat/omap-pm.h> 20#include <plat/mux.h> 21#include <plat/omap_device.h> 22 23#include "mux.h" 24#include "hsmmc.h" 25#include "control.h" 26 27#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) 28 29static u16 control_pbias_offset; 30static u16 control_devconf1_offset; 31static u16 control_mmc1; 32 33#define HSMMC_NAME_LEN 9 34 35#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 36 37static int hsmmc_get_context_loss(struct device *dev) 38{ 39 return omap_pm_get_dev_context_loss_count(dev); 40} 41 42#else 43#define hsmmc_get_context_loss NULL 44#endif 45 46static void omap_hsmmc1_before_set_reg(struct device *dev, int slot, 47 int power_on, int vdd) 48{ 49 u32 reg, prog_io; 50 struct omap_mmc_platform_data *mmc = dev->platform_data; 51 52 if (mmc->slots[0].remux) 53 mmc->slots[0].remux(dev, slot, power_on); 54 55 /* 56 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the 57 * card with Vcc regulator (from twl4030 or whatever). OMAP has both 58 * 1.8V and 3.0V modes, controlled by the PBIAS register. 59 * 60 * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which 61 * is most naturally TWL VSIM; those pins also use PBIAS. 62 * 63 * FIXME handle VMMC1A as needed ... 64 */ 65 if (power_on) { 66 if (cpu_is_omap2430()) { 67 reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1); 68 if ((1 << vdd) >= MMC_VDD_30_31) 69 reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE; 70 else 71 reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE; 72 omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1); 73 } 74 75 if (mmc->slots[0].internal_clock) { 76 reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); 77 reg |= OMAP2_MMCSDIO1ADPCLKISEL; 78 omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0); 79 } 80 81 reg = omap_ctrl_readl(control_pbias_offset); 82 if (cpu_is_omap3630()) { 83 /* Set MMC I/O to 52Mhz */ 84 prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1); 85 prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL; 86 omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1); 87 } else { 88 reg |= OMAP2_PBIASSPEEDCTRL0; 89 } 90 reg &= ~OMAP2_PBIASLITEPWRDNZ0; 91 omap_ctrl_writel(reg, control_pbias_offset); 92 } else { 93 reg = omap_ctrl_readl(control_pbias_offset); 94 reg &= ~OMAP2_PBIASLITEPWRDNZ0; 95 omap_ctrl_writel(reg, control_pbias_offset); 96 } 97} 98 99static void omap_hsmmc1_after_set_reg(struct device *dev, int slot, 100 int power_on, int vdd) 101{ 102 u32 reg; 103 104 /* 100ms delay required for PBIAS configuration */ 105 msleep(100); 106 107 if (power_on) { 108 reg = omap_ctrl_readl(control_pbias_offset); 109 reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0); 110 if ((1 << vdd) <= MMC_VDD_165_195) 111 reg &= ~OMAP2_PBIASLITEVMODE0; 112 else 113 reg |= OMAP2_PBIASLITEVMODE0; 114 omap_ctrl_writel(reg, control_pbias_offset); 115 } else { 116 reg = omap_ctrl_readl(control_pbias_offset); 117 reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 | 118 OMAP2_PBIASLITEVMODE0); 119 omap_ctrl_writel(reg, control_pbias_offset); 120 } 121} 122 123static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot, 124 int power_on, int vdd) 125{ 126 u32 reg; 127 128 /* 129 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the 130 * card with Vcc regulator (from twl4030 or whatever). OMAP has both 131 * 1.8V and 3.0V modes, controlled by the PBIAS register. 132 */ 133 reg = omap4_ctrl_pad_readl(control_pbias_offset); 134 reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | 135 OMAP4_MMC1_PWRDNZ_MASK | 136 OMAP4_MMC1_PBIASLITE_VMODE_MASK); 137 omap4_ctrl_pad_writel(reg, control_pbias_offset); 138} 139 140static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, 141 int power_on, int vdd) 142{ 143 u32 reg; 144 unsigned long timeout; 145 146 if (power_on) { 147 reg = omap4_ctrl_pad_readl(control_pbias_offset); 148 reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK; 149 if ((1 << vdd) <= MMC_VDD_165_195) 150 reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK; 151 else 152 reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK; 153 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | 154 OMAP4_MMC1_PWRDNZ_MASK); 155 omap4_ctrl_pad_writel(reg, control_pbias_offset); 156 157 timeout = jiffies + msecs_to_jiffies(5); 158 do { 159 reg = omap4_ctrl_pad_readl(control_pbias_offset); 160 if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK)) 161 break; 162 usleep_range(100, 200); 163 } while (!time_after(jiffies, timeout)); 164 165 if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) { 166 pr_err("Pbias Voltage is not same as LDO\n"); 167 /* Caution : On VMODE_ERROR Power Down MMC IO */ 168 reg &= ~(OMAP4_MMC1_PWRDNZ_MASK); 169 omap4_ctrl_pad_writel(reg, control_pbias_offset); 170 } 171 } 172} 173 174static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc) 175{ 176 u32 reg; 177 178 reg = omap_ctrl_readl(control_devconf1_offset); 179 if (mmc->slots[0].internal_clock) 180 reg |= OMAP2_MMCSDIO2ADPCLKISEL; 181 else 182 reg &= ~OMAP2_MMCSDIO2ADPCLKISEL; 183 omap_ctrl_writel(reg, control_devconf1_offset); 184} 185 186static void hsmmc2_before_set_reg(struct device *dev, int slot, 187 int power_on, int vdd) 188{ 189 struct omap_mmc_platform_data *mmc = dev->platform_data; 190 191 if (mmc->slots[0].remux) 192 mmc->slots[0].remux(dev, slot, power_on); 193 194 if (power_on) 195 hsmmc2_select_input_clk_src(mmc); 196} 197 198static int am35x_hsmmc2_set_power(struct device *dev, int slot, 199 int power_on, int vdd) 200{ 201 struct omap_mmc_platform_data *mmc = dev->platform_data; 202 203 if (power_on) 204 hsmmc2_select_input_clk_src(mmc); 205 206 return 0; 207} 208 209static int nop_mmc_set_power(struct device *dev, int slot, int power_on, 210 int vdd) 211{ 212 return 0; 213} 214 215static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller, 216 int controller_nr) 217{ 218 if (gpio_is_valid(mmc_controller->slots[0].switch_pin) && 219 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) 220 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin, 221 OMAP_PIN_INPUT_PULLUP); 222 if (gpio_is_valid(mmc_controller->slots[0].gpio_wp) && 223 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES)) 224 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, 225 OMAP_PIN_INPUT_PULLUP); 226 if (cpu_is_omap34xx()) { 227 if (controller_nr == 0) { 228 omap_mux_init_signal("sdmmc1_clk", 229 OMAP_PIN_INPUT_PULLUP); 230 omap_mux_init_signal("sdmmc1_cmd", 231 OMAP_PIN_INPUT_PULLUP); 232 omap_mux_init_signal("sdmmc1_dat0", 233 OMAP_PIN_INPUT_PULLUP); 234 if (mmc_controller->slots[0].caps & 235 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { 236 omap_mux_init_signal("sdmmc1_dat1", 237 OMAP_PIN_INPUT_PULLUP); 238 omap_mux_init_signal("sdmmc1_dat2", 239 OMAP_PIN_INPUT_PULLUP); 240 omap_mux_init_signal("sdmmc1_dat3", 241 OMAP_PIN_INPUT_PULLUP); 242 } 243 if (mmc_controller->slots[0].caps & 244 MMC_CAP_8_BIT_DATA) { 245 omap_mux_init_signal("sdmmc1_dat4", 246 OMAP_PIN_INPUT_PULLUP); 247 omap_mux_init_signal("sdmmc1_dat5", 248 OMAP_PIN_INPUT_PULLUP); 249 omap_mux_init_signal("sdmmc1_dat6", 250 OMAP_PIN_INPUT_PULLUP); 251 omap_mux_init_signal("sdmmc1_dat7", 252 OMAP_PIN_INPUT_PULLUP); 253 } 254 } 255 if (controller_nr == 1) { 256 /* MMC2 */ 257 omap_mux_init_signal("sdmmc2_clk", 258 OMAP_PIN_INPUT_PULLUP); 259 omap_mux_init_signal("sdmmc2_cmd", 260 OMAP_PIN_INPUT_PULLUP); 261 omap_mux_init_signal("sdmmc2_dat0", 262 OMAP_PIN_INPUT_PULLUP); 263 264 /* 265 * For 8 wire configurations, Lines DAT4, 5, 6 and 7 266 * need to be muxed in the board-*.c files 267 */ 268 if (mmc_controller->slots[0].caps & 269 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { 270 omap_mux_init_signal("sdmmc2_dat1", 271 OMAP_PIN_INPUT_PULLUP); 272 omap_mux_init_signal("sdmmc2_dat2", 273 OMAP_PIN_INPUT_PULLUP); 274 omap_mux_init_signal("sdmmc2_dat3", 275 OMAP_PIN_INPUT_PULLUP); 276 } 277 if (mmc_controller->slots[0].caps & 278 MMC_CAP_8_BIT_DATA) { 279 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4", 280 OMAP_PIN_INPUT_PULLUP); 281 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5", 282 OMAP_PIN_INPUT_PULLUP); 283 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6", 284 OMAP_PIN_INPUT_PULLUP); 285 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7", 286 OMAP_PIN_INPUT_PULLUP); 287 } 288 } 289 290 /* 291 * For MMC3 the pins need to be muxed in the board-*.c files 292 */ 293 } 294} 295 296static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, 297 struct omap_mmc_platform_data *mmc) 298{ 299 char *hc_name; 300 301 hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL); 302 if (!hc_name) { 303 pr_err("Cannot allocate memory for controller slot name\n"); 304 kfree(hc_name); 305 return -ENOMEM; 306 } 307 308 if (c->name) 309 strncpy(hc_name, c->name, HSMMC_NAME_LEN); 310 else 311 snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i", 312 c->mmc, 1); 313 mmc->slots[0].name = hc_name; 314 mmc->nr_slots = 1; 315 mmc->slots[0].caps = c->caps; 316 mmc->slots[0].pm_caps = c->pm_caps; 317 mmc->slots[0].internal_clock = !c->ext_clock; 318 mmc->dma_mask = 0xffffffff; 319 mmc->max_freq = c->max_freq; 320 if (cpu_is_omap44xx()) 321 mmc->reg_offset = OMAP4_MMC_REG_OFFSET; 322 else 323 mmc->reg_offset = 0; 324 325 mmc->get_context_loss_count = hsmmc_get_context_loss; 326 327 mmc->slots[0].switch_pin = c->gpio_cd; 328 mmc->slots[0].gpio_wp = c->gpio_wp; 329 330 mmc->slots[0].remux = c->remux; 331 mmc->slots[0].init_card = c->init_card; 332 333 if (c->cover_only) 334 mmc->slots[0].cover = 1; 335 336 if (c->nonremovable) 337 mmc->slots[0].nonremovable = 1; 338 339 if (c->power_saving) 340 mmc->slots[0].power_saving = 1; 341 342 if (c->no_off) 343 mmc->slots[0].no_off = 1; 344 345 if (c->no_off_init) 346 mmc->slots[0].no_regulator_off_init = c->no_off_init; 347 348 if (c->vcc_aux_disable_is_sleep) 349 mmc->slots[0].vcc_aux_disable_is_sleep = 1; 350 351 /* 352 * NOTE: MMC slots should have a Vcc regulator set up. 353 * This may be from a TWL4030-family chip, another 354 * controllable regulator, or a fixed supply. 355 * 356 * temporary HACK: ocr_mask instead of fixed supply 357 */ 358 if (cpu_is_omap3505() || cpu_is_omap3517()) 359 mmc->slots[0].ocr_mask = MMC_VDD_165_195 | 360 MMC_VDD_26_27 | 361 MMC_VDD_27_28 | 362 MMC_VDD_29_30 | 363 MMC_VDD_30_31 | 364 MMC_VDD_31_32; 365 else 366 mmc->slots[0].ocr_mask = c->ocr_mask; 367 368 if (!cpu_is_omap3517() && !cpu_is_omap3505()) 369 mmc->slots[0].features |= HSMMC_HAS_PBIAS; 370 371 if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) 372 mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET; 373 374 switch (c->mmc) { 375 case 1: 376 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { 377 /* on-chip level shifting via PBIAS0/PBIAS1 */ 378 if (cpu_is_omap44xx()) { 379 mmc->slots[0].before_set_reg = 380 omap4_hsmmc1_before_set_reg; 381 mmc->slots[0].after_set_reg = 382 omap4_hsmmc1_after_set_reg; 383 } else { 384 mmc->slots[0].before_set_reg = 385 omap_hsmmc1_before_set_reg; 386 mmc->slots[0].after_set_reg = 387 omap_hsmmc1_after_set_reg; 388 } 389 } 390 391 if (cpu_is_omap3517() || cpu_is_omap3505()) 392 mmc->slots[0].set_power = nop_mmc_set_power; 393 394 /* OMAP3630 HSMMC1 supports only 4-bit */ 395 if (cpu_is_omap3630() && 396 (c->caps & MMC_CAP_8_BIT_DATA)) { 397 c->caps &= ~MMC_CAP_8_BIT_DATA; 398 c->caps |= MMC_CAP_4_BIT_DATA; 399 mmc->slots[0].caps = c->caps; 400 } 401 break; 402 case 2: 403 if (cpu_is_omap3517() || cpu_is_omap3505()) 404 mmc->slots[0].set_power = am35x_hsmmc2_set_power; 405 406 if (c->ext_clock) 407 c->transceiver = 1; 408 if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) { 409 c->caps &= ~MMC_CAP_8_BIT_DATA; 410 c->caps |= MMC_CAP_4_BIT_DATA; 411 } 412 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { 413 /* off-chip level shifting, or none */ 414 mmc->slots[0].before_set_reg = hsmmc2_before_set_reg; 415 mmc->slots[0].after_set_reg = NULL; 416 } 417 break; 418 case 3: 419 case 4: 420 case 5: 421 mmc->slots[0].before_set_reg = NULL; 422 mmc->slots[0].after_set_reg = NULL; 423 break; 424 default: 425 pr_err("MMC%d configuration not supported!\n", c->mmc); 426 kfree(hc_name); 427 return -ENODEV; 428 } 429 return 0; 430} 431 432static int omap_hsmmc_done; 433 434void omap_hsmmc_late_init(struct omap2_hsmmc_info *c) 435{ 436 struct platform_device *pdev; 437 struct omap_mmc_platform_data *mmc_pdata; 438 int res; 439 440 if (omap_hsmmc_done != 1) 441 return; 442 443 omap_hsmmc_done++; 444 445 for (; c->mmc; c++) { 446 if (!c->deferred) 447 continue; 448 449 pdev = c->pdev; 450 if (!pdev) 451 continue; 452 453 mmc_pdata = pdev->dev.platform_data; 454 if (!mmc_pdata) 455 continue; 456 457 mmc_pdata->slots[0].switch_pin = c->gpio_cd; 458 mmc_pdata->slots[0].gpio_wp = c->gpio_wp; 459 460 res = omap_device_register(pdev); 461 if (res) 462 pr_err("Could not late init MMC %s\n", 463 c->name); 464 } 465} 466 467#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16 468 469static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo, 470 int ctrl_nr) 471{ 472 struct omap_hwmod *oh; 473 struct omap_hwmod *ohs[1]; 474 struct omap_device *od; 475 struct platform_device *pdev; 476 char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN]; 477 struct omap_mmc_platform_data *mmc_data; 478 struct omap_mmc_dev_attr *mmc_dev_attr; 479 char *name; 480 int res; 481 482 mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL); 483 if (!mmc_data) { 484 pr_err("Cannot allocate memory for mmc device!\n"); 485 return; 486 } 487 488 res = omap_hsmmc_pdata_init(hsmmcinfo, mmc_data); 489 if (res < 0) 490 goto free_mmc; 491 492 omap_hsmmc_mux(mmc_data, (ctrl_nr - 1)); 493 494 name = "omap_hsmmc"; 495 res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN, 496 "mmc%d", ctrl_nr); 497 WARN(res >= MAX_OMAP_MMC_HWMOD_NAME_LEN, 498 "String buffer overflow in MMC%d device setup\n", ctrl_nr); 499 500 oh = omap_hwmod_lookup(oh_name); 501 if (!oh) { 502 pr_err("Could not look up %s\n", oh_name); 503 goto free_name; 504 } 505 ohs[0] = oh; 506 if (oh->dev_attr != NULL) { 507 mmc_dev_attr = oh->dev_attr; 508 mmc_data->controller_flags = mmc_dev_attr->flags; 509 /* 510 * erratum 2.1.1.128 doesn't apply if board has 511 * a transceiver is attached 512 */ 513 if (hsmmcinfo->transceiver) 514 mmc_data->controller_flags &= 515 ~OMAP_HSMMC_BROKEN_MULTIBLOCK_READ; 516 } 517 518 pdev = platform_device_alloc(name, ctrl_nr - 1); 519 if (!pdev) { 520 pr_err("Could not allocate pdev for %s\n", name); 521 goto free_name; 522 } 523 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id); 524 525 od = omap_device_alloc(pdev, ohs, 1, NULL, 0); 526 if (!od) { 527 pr_err("Could not allocate od for %s\n", name); 528 goto put_pdev; 529 } 530 531 res = platform_device_add_data(pdev, mmc_data, 532 sizeof(struct omap_mmc_platform_data)); 533 if (res) { 534 pr_err("Could not add pdata for %s\n", name); 535 goto put_pdev; 536 } 537 538 hsmmcinfo->pdev = pdev; 539 540 if (hsmmcinfo->deferred) 541 goto free_mmc; 542 543 res = omap_device_register(pdev); 544 if (res) { 545 pr_err("Could not register od for %s\n", name); 546 goto free_od; 547 } 548 549 goto free_mmc; 550 551free_od: 552 omap_device_delete(od); 553 554put_pdev: 555 platform_device_put(pdev); 556 557free_name: 558 kfree(mmc_data->slots[0].name); 559 560free_mmc: 561 kfree(mmc_data); 562} 563 564void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers) 565{ 566 u32 reg; 567 568 if (omap_hsmmc_done) 569 return; 570 571 omap_hsmmc_done = 1; 572 573 if (!cpu_is_omap44xx()) { 574 if (cpu_is_omap2430()) { 575 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; 576 control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; 577 } else { 578 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; 579 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; 580 } 581 } else { 582 control_pbias_offset = 583 OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE; 584 control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1; 585 reg = omap4_ctrl_pad_readl(control_mmc1); 586 reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | 587 OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK); 588 reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | 589 OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK); 590 reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK | 591 OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | 592 OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK); 593 omap4_ctrl_pad_writel(reg, control_mmc1); 594 } 595 596 for (; controllers->mmc; controllers++) 597 omap_hsmmc_init_one(controllers, controllers->mmc); 598 599} 600 601#endif 602