1/* 2 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips 3 * 4 * Copyright (C) 2009-2011 Nokia Corporation 5 * Paul Walmsley 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * XXX handle crossbar/shared link difference for L3? 12 * XXX these should be marked initdata for multi-OMAP kernels 13 */ 14#include <plat/omap_hwmod.h> 15#include <mach/irqs.h> 16#include <plat/cpu.h> 17#include <plat/dma.h> 18#include <plat/serial.h> 19#include <plat/i2c.h> 20#include <plat/gpio.h> 21#include <plat/mcspi.h> 22#include <plat/dmtimer.h> 23#include <plat/l3_2xxx.h> 24#include <plat/l4_2xxx.h> 25 26#include "omap_hwmod_common_data.h" 27 28#include "cm-regbits-24xx.h" 29#include "prm-regbits-24xx.h" 30#include "wd_timer.h" 31 32/* 33 * OMAP2420 hardware module integration data 34 * 35 * ALl of the data in this section should be autogeneratable from the 36 * TI hardware database or other technical documentation. Data that 37 * is driver-specific or driver-kernel integration-specific belongs 38 * elsewhere. 39 */ 40 41static struct omap_hwmod omap2420_mpu_hwmod; 42static struct omap_hwmod omap2420_iva_hwmod; 43static struct omap_hwmod omap2420_l3_main_hwmod; 44static struct omap_hwmod omap2420_l4_core_hwmod; 45static struct omap_hwmod omap2420_dss_core_hwmod; 46static struct omap_hwmod omap2420_dss_dispc_hwmod; 47static struct omap_hwmod omap2420_dss_rfbi_hwmod; 48static struct omap_hwmod omap2420_dss_venc_hwmod; 49static struct omap_hwmod omap2420_wd_timer2_hwmod; 50static struct omap_hwmod omap2420_gpio1_hwmod; 51static struct omap_hwmod omap2420_gpio2_hwmod; 52static struct omap_hwmod omap2420_gpio3_hwmod; 53static struct omap_hwmod omap2420_gpio4_hwmod; 54static struct omap_hwmod omap2420_dma_system_hwmod; 55static struct omap_hwmod omap2420_mcspi1_hwmod; 56static struct omap_hwmod omap2420_mcspi2_hwmod; 57 58/* L3 -> L4_CORE interface */ 59static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { 60 .master = &omap2420_l3_main_hwmod, 61 .slave = &omap2420_l4_core_hwmod, 62 .user = OCP_USER_MPU | OCP_USER_SDMA, 63}; 64 65/* MPU -> L3 interface */ 66static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = { 67 .master = &omap2420_mpu_hwmod, 68 .slave = &omap2420_l3_main_hwmod, 69 .user = OCP_USER_MPU, 70}; 71 72/* Slave interfaces on the L3 interconnect */ 73static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = { 74 &omap2420_mpu__l3_main, 75}; 76 77/* DSS -> l3 */ 78static struct omap_hwmod_ocp_if omap2420_dss__l3 = { 79 .master = &omap2420_dss_core_hwmod, 80 .slave = &omap2420_l3_main_hwmod, 81 .fw = { 82 .omap2 = { 83 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, 84 .flags = OMAP_FIREWALL_L3, 85 } 86 }, 87 .user = OCP_USER_MPU | OCP_USER_SDMA, 88}; 89 90/* Master interfaces on the L3 interconnect */ 91static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = { 92 &omap2420_l3_main__l4_core, 93}; 94 95/* L3 */ 96static struct omap_hwmod omap2420_l3_main_hwmod = { 97 .name = "l3_main", 98 .class = &l3_hwmod_class, 99 .masters = omap2420_l3_main_masters, 100 .masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters), 101 .slaves = omap2420_l3_main_slaves, 102 .slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves), 103 .flags = HWMOD_NO_IDLEST, 104}; 105 106static struct omap_hwmod omap2420_l4_wkup_hwmod; 107static struct omap_hwmod omap2420_uart1_hwmod; 108static struct omap_hwmod omap2420_uart2_hwmod; 109static struct omap_hwmod omap2420_uart3_hwmod; 110static struct omap_hwmod omap2420_i2c1_hwmod; 111static struct omap_hwmod omap2420_i2c2_hwmod; 112static struct omap_hwmod omap2420_mcbsp1_hwmod; 113static struct omap_hwmod omap2420_mcbsp2_hwmod; 114 115/* l4 core -> mcspi1 interface */ 116static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = { 117 .master = &omap2420_l4_core_hwmod, 118 .slave = &omap2420_mcspi1_hwmod, 119 .clk = "mcspi1_ick", 120 .addr = omap2_mcspi1_addr_space, 121 .user = OCP_USER_MPU | OCP_USER_SDMA, 122}; 123 124/* l4 core -> mcspi2 interface */ 125static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = { 126 .master = &omap2420_l4_core_hwmod, 127 .slave = &omap2420_mcspi2_hwmod, 128 .clk = "mcspi2_ick", 129 .addr = omap2_mcspi2_addr_space, 130 .user = OCP_USER_MPU | OCP_USER_SDMA, 131}; 132 133/* L4_CORE -> L4_WKUP interface */ 134static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { 135 .master = &omap2420_l4_core_hwmod, 136 .slave = &omap2420_l4_wkup_hwmod, 137 .user = OCP_USER_MPU | OCP_USER_SDMA, 138}; 139 140/* L4 CORE -> UART1 interface */ 141static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { 142 .master = &omap2420_l4_core_hwmod, 143 .slave = &omap2420_uart1_hwmod, 144 .clk = "uart1_ick", 145 .addr = omap2xxx_uart1_addr_space, 146 .user = OCP_USER_MPU | OCP_USER_SDMA, 147}; 148 149/* L4 CORE -> UART2 interface */ 150static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { 151 .master = &omap2420_l4_core_hwmod, 152 .slave = &omap2420_uart2_hwmod, 153 .clk = "uart2_ick", 154 .addr = omap2xxx_uart2_addr_space, 155 .user = OCP_USER_MPU | OCP_USER_SDMA, 156}; 157 158/* L4 PER -> UART3 interface */ 159static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { 160 .master = &omap2420_l4_core_hwmod, 161 .slave = &omap2420_uart3_hwmod, 162 .clk = "uart3_ick", 163 .addr = omap2xxx_uart3_addr_space, 164 .user = OCP_USER_MPU | OCP_USER_SDMA, 165}; 166 167/* L4 CORE -> I2C1 interface */ 168static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { 169 .master = &omap2420_l4_core_hwmod, 170 .slave = &omap2420_i2c1_hwmod, 171 .clk = "i2c1_ick", 172 .addr = omap2_i2c1_addr_space, 173 .user = OCP_USER_MPU | OCP_USER_SDMA, 174}; 175 176/* L4 CORE -> I2C2 interface */ 177static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { 178 .master = &omap2420_l4_core_hwmod, 179 .slave = &omap2420_i2c2_hwmod, 180 .clk = "i2c2_ick", 181 .addr = omap2_i2c2_addr_space, 182 .user = OCP_USER_MPU | OCP_USER_SDMA, 183}; 184 185/* Slave interfaces on the L4_CORE interconnect */ 186static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { 187 &omap2420_l3_main__l4_core, 188}; 189 190/* Master interfaces on the L4_CORE interconnect */ 191static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { 192 &omap2420_l4_core__l4_wkup, 193 &omap2_l4_core__uart1, 194 &omap2_l4_core__uart2, 195 &omap2_l4_core__uart3, 196 &omap2420_l4_core__i2c1, 197 &omap2420_l4_core__i2c2 198}; 199 200/* L4 CORE */ 201static struct omap_hwmod omap2420_l4_core_hwmod = { 202 .name = "l4_core", 203 .class = &l4_hwmod_class, 204 .masters = omap2420_l4_core_masters, 205 .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters), 206 .slaves = omap2420_l4_core_slaves, 207 .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves), 208 .flags = HWMOD_NO_IDLEST, 209}; 210 211/* Slave interfaces on the L4_WKUP interconnect */ 212static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = { 213 &omap2420_l4_core__l4_wkup, 214}; 215 216/* Master interfaces on the L4_WKUP interconnect */ 217static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = { 218}; 219 220/* L4 WKUP */ 221static struct omap_hwmod omap2420_l4_wkup_hwmod = { 222 .name = "l4_wkup", 223 .class = &l4_hwmod_class, 224 .masters = omap2420_l4_wkup_masters, 225 .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters), 226 .slaves = omap2420_l4_wkup_slaves, 227 .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves), 228 .flags = HWMOD_NO_IDLEST, 229}; 230 231/* Master interfaces on the MPU device */ 232static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = { 233 &omap2420_mpu__l3_main, 234}; 235 236/* MPU */ 237static struct omap_hwmod omap2420_mpu_hwmod = { 238 .name = "mpu", 239 .class = &mpu_hwmod_class, 240 .main_clk = "mpu_ck", 241 .masters = omap2420_mpu_masters, 242 .masters_cnt = ARRAY_SIZE(omap2420_mpu_masters), 243}; 244 245/* 246 * IVA1 interface data 247 */ 248 249/* IVA <- L3 interface */ 250static struct omap_hwmod_ocp_if omap2420_l3__iva = { 251 .master = &omap2420_l3_main_hwmod, 252 .slave = &omap2420_iva_hwmod, 253 .clk = "iva1_ifck", 254 .user = OCP_USER_MPU | OCP_USER_SDMA, 255}; 256 257static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = { 258 &omap2420_l3__iva, 259}; 260 261/* 262 * IVA2 (IVA2) 263 */ 264 265static struct omap_hwmod omap2420_iva_hwmod = { 266 .name = "iva", 267 .class = &iva_hwmod_class, 268 .masters = omap2420_iva_masters, 269 .masters_cnt = ARRAY_SIZE(omap2420_iva_masters), 270}; 271 272/* always-on timers dev attribute */ 273static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { 274 .timer_capability = OMAP_TIMER_ALWON, 275}; 276 277/* pwm timers dev attribute */ 278static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { 279 .timer_capability = OMAP_TIMER_HAS_PWM, 280}; 281 282/* timer1 */ 283static struct omap_hwmod omap2420_timer1_hwmod; 284 285static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { 286 { 287 .pa_start = 0x48028000, 288 .pa_end = 0x48028000 + SZ_1K - 1, 289 .flags = ADDR_TYPE_RT 290 }, 291 { } 292}; 293 294/* l4_wkup -> timer1 */ 295static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { 296 .master = &omap2420_l4_wkup_hwmod, 297 .slave = &omap2420_timer1_hwmod, 298 .clk = "gpt1_ick", 299 .addr = omap2420_timer1_addrs, 300 .user = OCP_USER_MPU | OCP_USER_SDMA, 301}; 302 303/* timer1 slave port */ 304static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = { 305 &omap2420_l4_wkup__timer1, 306}; 307 308/* timer1 hwmod */ 309static struct omap_hwmod omap2420_timer1_hwmod = { 310 .name = "timer1", 311 .mpu_irqs = omap2_timer1_mpu_irqs, 312 .main_clk = "gpt1_fck", 313 .prcm = { 314 .omap2 = { 315 .prcm_reg_id = 1, 316 .module_bit = OMAP24XX_EN_GPT1_SHIFT, 317 .module_offs = WKUP_MOD, 318 .idlest_reg_id = 1, 319 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, 320 }, 321 }, 322 .dev_attr = &capability_alwon_dev_attr, 323 .slaves = omap2420_timer1_slaves, 324 .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves), 325 .class = &omap2xxx_timer_hwmod_class, 326}; 327 328/* timer2 */ 329static struct omap_hwmod omap2420_timer2_hwmod; 330 331/* l4_core -> timer2 */ 332static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = { 333 .master = &omap2420_l4_core_hwmod, 334 .slave = &omap2420_timer2_hwmod, 335 .clk = "gpt2_ick", 336 .addr = omap2xxx_timer2_addrs, 337 .user = OCP_USER_MPU | OCP_USER_SDMA, 338}; 339 340/* timer2 slave port */ 341static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = { 342 &omap2420_l4_core__timer2, 343}; 344 345/* timer2 hwmod */ 346static struct omap_hwmod omap2420_timer2_hwmod = { 347 .name = "timer2", 348 .mpu_irqs = omap2_timer2_mpu_irqs, 349 .main_clk = "gpt2_fck", 350 .prcm = { 351 .omap2 = { 352 .prcm_reg_id = 1, 353 .module_bit = OMAP24XX_EN_GPT2_SHIFT, 354 .module_offs = CORE_MOD, 355 .idlest_reg_id = 1, 356 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, 357 }, 358 }, 359 .dev_attr = &capability_alwon_dev_attr, 360 .slaves = omap2420_timer2_slaves, 361 .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves), 362 .class = &omap2xxx_timer_hwmod_class, 363}; 364 365/* timer3 */ 366static struct omap_hwmod omap2420_timer3_hwmod; 367 368/* l4_core -> timer3 */ 369static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = { 370 .master = &omap2420_l4_core_hwmod, 371 .slave = &omap2420_timer3_hwmod, 372 .clk = "gpt3_ick", 373 .addr = omap2xxx_timer3_addrs, 374 .user = OCP_USER_MPU | OCP_USER_SDMA, 375}; 376 377/* timer3 slave port */ 378static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = { 379 &omap2420_l4_core__timer3, 380}; 381 382/* timer3 hwmod */ 383static struct omap_hwmod omap2420_timer3_hwmod = { 384 .name = "timer3", 385 .mpu_irqs = omap2_timer3_mpu_irqs, 386 .main_clk = "gpt3_fck", 387 .prcm = { 388 .omap2 = { 389 .prcm_reg_id = 1, 390 .module_bit = OMAP24XX_EN_GPT3_SHIFT, 391 .module_offs = CORE_MOD, 392 .idlest_reg_id = 1, 393 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, 394 }, 395 }, 396 .dev_attr = &capability_alwon_dev_attr, 397 .slaves = omap2420_timer3_slaves, 398 .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves), 399 .class = &omap2xxx_timer_hwmod_class, 400}; 401 402/* timer4 */ 403static struct omap_hwmod omap2420_timer4_hwmod; 404 405/* l4_core -> timer4 */ 406static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = { 407 .master = &omap2420_l4_core_hwmod, 408 .slave = &omap2420_timer4_hwmod, 409 .clk = "gpt4_ick", 410 .addr = omap2xxx_timer4_addrs, 411 .user = OCP_USER_MPU | OCP_USER_SDMA, 412}; 413 414/* timer4 slave port */ 415static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = { 416 &omap2420_l4_core__timer4, 417}; 418 419/* timer4 hwmod */ 420static struct omap_hwmod omap2420_timer4_hwmod = { 421 .name = "timer4", 422 .mpu_irqs = omap2_timer4_mpu_irqs, 423 .main_clk = "gpt4_fck", 424 .prcm = { 425 .omap2 = { 426 .prcm_reg_id = 1, 427 .module_bit = OMAP24XX_EN_GPT4_SHIFT, 428 .module_offs = CORE_MOD, 429 .idlest_reg_id = 1, 430 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, 431 }, 432 }, 433 .dev_attr = &capability_alwon_dev_attr, 434 .slaves = omap2420_timer4_slaves, 435 .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves), 436 .class = &omap2xxx_timer_hwmod_class, 437}; 438 439/* timer5 */ 440static struct omap_hwmod omap2420_timer5_hwmod; 441 442/* l4_core -> timer5 */ 443static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = { 444 .master = &omap2420_l4_core_hwmod, 445 .slave = &omap2420_timer5_hwmod, 446 .clk = "gpt5_ick", 447 .addr = omap2xxx_timer5_addrs, 448 .user = OCP_USER_MPU | OCP_USER_SDMA, 449}; 450 451/* timer5 slave port */ 452static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = { 453 &omap2420_l4_core__timer5, 454}; 455 456/* timer5 hwmod */ 457static struct omap_hwmod omap2420_timer5_hwmod = { 458 .name = "timer5", 459 .mpu_irqs = omap2_timer5_mpu_irqs, 460 .main_clk = "gpt5_fck", 461 .prcm = { 462 .omap2 = { 463 .prcm_reg_id = 1, 464 .module_bit = OMAP24XX_EN_GPT5_SHIFT, 465 .module_offs = CORE_MOD, 466 .idlest_reg_id = 1, 467 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, 468 }, 469 }, 470 .dev_attr = &capability_alwon_dev_attr, 471 .slaves = omap2420_timer5_slaves, 472 .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves), 473 .class = &omap2xxx_timer_hwmod_class, 474}; 475 476 477/* timer6 */ 478static struct omap_hwmod omap2420_timer6_hwmod; 479 480/* l4_core -> timer6 */ 481static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = { 482 .master = &omap2420_l4_core_hwmod, 483 .slave = &omap2420_timer6_hwmod, 484 .clk = "gpt6_ick", 485 .addr = omap2xxx_timer6_addrs, 486 .user = OCP_USER_MPU | OCP_USER_SDMA, 487}; 488 489/* timer6 slave port */ 490static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = { 491 &omap2420_l4_core__timer6, 492}; 493 494/* timer6 hwmod */ 495static struct omap_hwmod omap2420_timer6_hwmod = { 496 .name = "timer6", 497 .mpu_irqs = omap2_timer6_mpu_irqs, 498 .main_clk = "gpt6_fck", 499 .prcm = { 500 .omap2 = { 501 .prcm_reg_id = 1, 502 .module_bit = OMAP24XX_EN_GPT6_SHIFT, 503 .module_offs = CORE_MOD, 504 .idlest_reg_id = 1, 505 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, 506 }, 507 }, 508 .dev_attr = &capability_alwon_dev_attr, 509 .slaves = omap2420_timer6_slaves, 510 .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves), 511 .class = &omap2xxx_timer_hwmod_class, 512}; 513 514/* timer7 */ 515static struct omap_hwmod omap2420_timer7_hwmod; 516 517/* l4_core -> timer7 */ 518static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = { 519 .master = &omap2420_l4_core_hwmod, 520 .slave = &omap2420_timer7_hwmod, 521 .clk = "gpt7_ick", 522 .addr = omap2xxx_timer7_addrs, 523 .user = OCP_USER_MPU | OCP_USER_SDMA, 524}; 525 526/* timer7 slave port */ 527static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = { 528 &omap2420_l4_core__timer7, 529}; 530 531/* timer7 hwmod */ 532static struct omap_hwmod omap2420_timer7_hwmod = { 533 .name = "timer7", 534 .mpu_irqs = omap2_timer7_mpu_irqs, 535 .main_clk = "gpt7_fck", 536 .prcm = { 537 .omap2 = { 538 .prcm_reg_id = 1, 539 .module_bit = OMAP24XX_EN_GPT7_SHIFT, 540 .module_offs = CORE_MOD, 541 .idlest_reg_id = 1, 542 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, 543 }, 544 }, 545 .dev_attr = &capability_alwon_dev_attr, 546 .slaves = omap2420_timer7_slaves, 547 .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves), 548 .class = &omap2xxx_timer_hwmod_class, 549}; 550 551/* timer8 */ 552static struct omap_hwmod omap2420_timer8_hwmod; 553 554/* l4_core -> timer8 */ 555static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = { 556 .master = &omap2420_l4_core_hwmod, 557 .slave = &omap2420_timer8_hwmod, 558 .clk = "gpt8_ick", 559 .addr = omap2xxx_timer8_addrs, 560 .user = OCP_USER_MPU | OCP_USER_SDMA, 561}; 562 563/* timer8 slave port */ 564static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = { 565 &omap2420_l4_core__timer8, 566}; 567 568/* timer8 hwmod */ 569static struct omap_hwmod omap2420_timer8_hwmod = { 570 .name = "timer8", 571 .mpu_irqs = omap2_timer8_mpu_irqs, 572 .main_clk = "gpt8_fck", 573 .prcm = { 574 .omap2 = { 575 .prcm_reg_id = 1, 576 .module_bit = OMAP24XX_EN_GPT8_SHIFT, 577 .module_offs = CORE_MOD, 578 .idlest_reg_id = 1, 579 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, 580 }, 581 }, 582 .dev_attr = &capability_alwon_dev_attr, 583 .slaves = omap2420_timer8_slaves, 584 .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves), 585 .class = &omap2xxx_timer_hwmod_class, 586}; 587 588/* timer9 */ 589static struct omap_hwmod omap2420_timer9_hwmod; 590 591/* l4_core -> timer9 */ 592static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = { 593 .master = &omap2420_l4_core_hwmod, 594 .slave = &omap2420_timer9_hwmod, 595 .clk = "gpt9_ick", 596 .addr = omap2xxx_timer9_addrs, 597 .user = OCP_USER_MPU | OCP_USER_SDMA, 598}; 599 600/* timer9 slave port */ 601static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = { 602 &omap2420_l4_core__timer9, 603}; 604 605/* timer9 hwmod */ 606static struct omap_hwmod omap2420_timer9_hwmod = { 607 .name = "timer9", 608 .mpu_irqs = omap2_timer9_mpu_irqs, 609 .main_clk = "gpt9_fck", 610 .prcm = { 611 .omap2 = { 612 .prcm_reg_id = 1, 613 .module_bit = OMAP24XX_EN_GPT9_SHIFT, 614 .module_offs = CORE_MOD, 615 .idlest_reg_id = 1, 616 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, 617 }, 618 }, 619 .dev_attr = &capability_pwm_dev_attr, 620 .slaves = omap2420_timer9_slaves, 621 .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves), 622 .class = &omap2xxx_timer_hwmod_class, 623}; 624 625/* timer10 */ 626static struct omap_hwmod omap2420_timer10_hwmod; 627 628/* l4_core -> timer10 */ 629static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = { 630 .master = &omap2420_l4_core_hwmod, 631 .slave = &omap2420_timer10_hwmod, 632 .clk = "gpt10_ick", 633 .addr = omap2_timer10_addrs, 634 .user = OCP_USER_MPU | OCP_USER_SDMA, 635}; 636 637/* timer10 slave port */ 638static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = { 639 &omap2420_l4_core__timer10, 640}; 641 642/* timer10 hwmod */ 643static struct omap_hwmod omap2420_timer10_hwmod = { 644 .name = "timer10", 645 .mpu_irqs = omap2_timer10_mpu_irqs, 646 .main_clk = "gpt10_fck", 647 .prcm = { 648 .omap2 = { 649 .prcm_reg_id = 1, 650 .module_bit = OMAP24XX_EN_GPT10_SHIFT, 651 .module_offs = CORE_MOD, 652 .idlest_reg_id = 1, 653 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, 654 }, 655 }, 656 .dev_attr = &capability_pwm_dev_attr, 657 .slaves = omap2420_timer10_slaves, 658 .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves), 659 .class = &omap2xxx_timer_hwmod_class, 660}; 661 662/* timer11 */ 663static struct omap_hwmod omap2420_timer11_hwmod; 664 665/* l4_core -> timer11 */ 666static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = { 667 .master = &omap2420_l4_core_hwmod, 668 .slave = &omap2420_timer11_hwmod, 669 .clk = "gpt11_ick", 670 .addr = omap2_timer11_addrs, 671 .user = OCP_USER_MPU | OCP_USER_SDMA, 672}; 673 674/* timer11 slave port */ 675static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = { 676 &omap2420_l4_core__timer11, 677}; 678 679/* timer11 hwmod */ 680static struct omap_hwmod omap2420_timer11_hwmod = { 681 .name = "timer11", 682 .mpu_irqs = omap2_timer11_mpu_irqs, 683 .main_clk = "gpt11_fck", 684 .prcm = { 685 .omap2 = { 686 .prcm_reg_id = 1, 687 .module_bit = OMAP24XX_EN_GPT11_SHIFT, 688 .module_offs = CORE_MOD, 689 .idlest_reg_id = 1, 690 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, 691 }, 692 }, 693 .dev_attr = &capability_pwm_dev_attr, 694 .slaves = omap2420_timer11_slaves, 695 .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves), 696 .class = &omap2xxx_timer_hwmod_class, 697}; 698 699/* timer12 */ 700static struct omap_hwmod omap2420_timer12_hwmod; 701 702/* l4_core -> timer12 */ 703static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = { 704 .master = &omap2420_l4_core_hwmod, 705 .slave = &omap2420_timer12_hwmod, 706 .clk = "gpt12_ick", 707 .addr = omap2xxx_timer12_addrs, 708 .user = OCP_USER_MPU | OCP_USER_SDMA, 709}; 710 711/* timer12 slave port */ 712static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = { 713 &omap2420_l4_core__timer12, 714}; 715 716/* timer12 hwmod */ 717static struct omap_hwmod omap2420_timer12_hwmod = { 718 .name = "timer12", 719 .mpu_irqs = omap2xxx_timer12_mpu_irqs, 720 .main_clk = "gpt12_fck", 721 .prcm = { 722 .omap2 = { 723 .prcm_reg_id = 1, 724 .module_bit = OMAP24XX_EN_GPT12_SHIFT, 725 .module_offs = CORE_MOD, 726 .idlest_reg_id = 1, 727 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, 728 }, 729 }, 730 .dev_attr = &capability_pwm_dev_attr, 731 .slaves = omap2420_timer12_slaves, 732 .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves), 733 .class = &omap2xxx_timer_hwmod_class, 734}; 735 736/* l4_wkup -> wd_timer2 */ 737static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { 738 { 739 .pa_start = 0x48022000, 740 .pa_end = 0x4802207f, 741 .flags = ADDR_TYPE_RT 742 }, 743 { } 744}; 745 746static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { 747 .master = &omap2420_l4_wkup_hwmod, 748 .slave = &omap2420_wd_timer2_hwmod, 749 .clk = "mpu_wdt_ick", 750 .addr = omap2420_wd_timer2_addrs, 751 .user = OCP_USER_MPU | OCP_USER_SDMA, 752}; 753 754/* wd_timer2 */ 755static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = { 756 &omap2420_l4_wkup__wd_timer2, 757}; 758 759static struct omap_hwmod omap2420_wd_timer2_hwmod = { 760 .name = "wd_timer2", 761 .class = &omap2xxx_wd_timer_hwmod_class, 762 .main_clk = "mpu_wdt_fck", 763 .prcm = { 764 .omap2 = { 765 .prcm_reg_id = 1, 766 .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, 767 .module_offs = WKUP_MOD, 768 .idlest_reg_id = 1, 769 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, 770 }, 771 }, 772 .slaves = omap2420_wd_timer2_slaves, 773 .slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves), 774}; 775 776/* UART1 */ 777 778static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = { 779 &omap2_l4_core__uart1, 780}; 781 782static struct omap_hwmod omap2420_uart1_hwmod = { 783 .name = "uart1", 784 .mpu_irqs = omap2_uart1_mpu_irqs, 785 .sdma_reqs = omap2_uart1_sdma_reqs, 786 .main_clk = "uart1_fck", 787 .prcm = { 788 .omap2 = { 789 .module_offs = CORE_MOD, 790 .prcm_reg_id = 1, 791 .module_bit = OMAP24XX_EN_UART1_SHIFT, 792 .idlest_reg_id = 1, 793 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, 794 }, 795 }, 796 .slaves = omap2420_uart1_slaves, 797 .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves), 798 .class = &omap2_uart_class, 799}; 800 801/* UART2 */ 802 803static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = { 804 &omap2_l4_core__uart2, 805}; 806 807static struct omap_hwmod omap2420_uart2_hwmod = { 808 .name = "uart2", 809 .mpu_irqs = omap2_uart2_mpu_irqs, 810 .sdma_reqs = omap2_uart2_sdma_reqs, 811 .main_clk = "uart2_fck", 812 .prcm = { 813 .omap2 = { 814 .module_offs = CORE_MOD, 815 .prcm_reg_id = 1, 816 .module_bit = OMAP24XX_EN_UART2_SHIFT, 817 .idlest_reg_id = 1, 818 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, 819 }, 820 }, 821 .slaves = omap2420_uart2_slaves, 822 .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves), 823 .class = &omap2_uart_class, 824}; 825 826/* UART3 */ 827 828static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = { 829 &omap2_l4_core__uart3, 830}; 831 832static struct omap_hwmod omap2420_uart3_hwmod = { 833 .name = "uart3", 834 .mpu_irqs = omap2_uart3_mpu_irqs, 835 .sdma_reqs = omap2_uart3_sdma_reqs, 836 .main_clk = "uart3_fck", 837 .prcm = { 838 .omap2 = { 839 .module_offs = CORE_MOD, 840 .prcm_reg_id = 2, 841 .module_bit = OMAP24XX_EN_UART3_SHIFT, 842 .idlest_reg_id = 2, 843 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, 844 }, 845 }, 846 .slaves = omap2420_uart3_slaves, 847 .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves), 848 .class = &omap2_uart_class, 849}; 850 851/* dss */ 852/* dss master ports */ 853static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = { 854 &omap2420_dss__l3, 855}; 856 857/* l4_core -> dss */ 858static struct omap_hwmod_ocp_if omap2420_l4_core__dss = { 859 .master = &omap2420_l4_core_hwmod, 860 .slave = &omap2420_dss_core_hwmod, 861 .clk = "dss_ick", 862 .addr = omap2_dss_addrs, 863 .fw = { 864 .omap2 = { 865 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, 866 .flags = OMAP_FIREWALL_L4, 867 } 868 }, 869 .user = OCP_USER_MPU | OCP_USER_SDMA, 870}; 871 872/* dss slave ports */ 873static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = { 874 &omap2420_l4_core__dss, 875}; 876 877static struct omap_hwmod_opt_clk dss_opt_clks[] = { 878 /* 879 * The DSS HW needs all DSS clocks enabled during reset. The dss_core 880 * driver does not use these clocks. 881 */ 882 { .role = "tv_clk", .clk = "dss_54m_fck" }, 883 { .role = "sys_clk", .clk = "dss2_fck" }, 884}; 885 886static struct omap_hwmod omap2420_dss_core_hwmod = { 887 .name = "dss_core", 888 .class = &omap2_dss_hwmod_class, 889 .main_clk = "dss1_fck", /* instead of dss_fck */ 890 .sdma_reqs = omap2xxx_dss_sdma_chs, 891 .prcm = { 892 .omap2 = { 893 .prcm_reg_id = 1, 894 .module_bit = OMAP24XX_EN_DSS1_SHIFT, 895 .module_offs = CORE_MOD, 896 .idlest_reg_id = 1, 897 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, 898 }, 899 }, 900 .opt_clks = dss_opt_clks, 901 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 902 .slaves = omap2420_dss_slaves, 903 .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves), 904 .masters = omap2420_dss_masters, 905 .masters_cnt = ARRAY_SIZE(omap2420_dss_masters), 906 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, 907}; 908 909/* l4_core -> dss_dispc */ 910static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = { 911 .master = &omap2420_l4_core_hwmod, 912 .slave = &omap2420_dss_dispc_hwmod, 913 .clk = "dss_ick", 914 .addr = omap2_dss_dispc_addrs, 915 .fw = { 916 .omap2 = { 917 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, 918 .flags = OMAP_FIREWALL_L4, 919 } 920 }, 921 .user = OCP_USER_MPU | OCP_USER_SDMA, 922}; 923 924/* dss_dispc slave ports */ 925static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = { 926 &omap2420_l4_core__dss_dispc, 927}; 928 929static struct omap_hwmod omap2420_dss_dispc_hwmod = { 930 .name = "dss_dispc", 931 .class = &omap2_dispc_hwmod_class, 932 .mpu_irqs = omap2_dispc_irqs, 933 .main_clk = "dss1_fck", 934 .prcm = { 935 .omap2 = { 936 .prcm_reg_id = 1, 937 .module_bit = OMAP24XX_EN_DSS1_SHIFT, 938 .module_offs = CORE_MOD, 939 .idlest_reg_id = 1, 940 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, 941 }, 942 }, 943 .slaves = omap2420_dss_dispc_slaves, 944 .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves), 945 .flags = HWMOD_NO_IDLEST, 946 .dev_attr = &omap2_3_dss_dispc_dev_attr 947}; 948 949/* l4_core -> dss_rfbi */ 950static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = { 951 .master = &omap2420_l4_core_hwmod, 952 .slave = &omap2420_dss_rfbi_hwmod, 953 .clk = "dss_ick", 954 .addr = omap2_dss_rfbi_addrs, 955 .fw = { 956 .omap2 = { 957 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, 958 .flags = OMAP_FIREWALL_L4, 959 } 960 }, 961 .user = OCP_USER_MPU | OCP_USER_SDMA, 962}; 963 964/* dss_rfbi slave ports */ 965static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = { 966 &omap2420_l4_core__dss_rfbi, 967}; 968 969static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { 970 { .role = "ick", .clk = "dss_ick" }, 971}; 972 973static struct omap_hwmod omap2420_dss_rfbi_hwmod = { 974 .name = "dss_rfbi", 975 .class = &omap2_rfbi_hwmod_class, 976 .main_clk = "dss1_fck", 977 .prcm = { 978 .omap2 = { 979 .prcm_reg_id = 1, 980 .module_bit = OMAP24XX_EN_DSS1_SHIFT, 981 .module_offs = CORE_MOD, 982 }, 983 }, 984 .opt_clks = dss_rfbi_opt_clks, 985 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), 986 .slaves = omap2420_dss_rfbi_slaves, 987 .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves), 988 .flags = HWMOD_NO_IDLEST, 989}; 990 991/* l4_core -> dss_venc */ 992static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { 993 .master = &omap2420_l4_core_hwmod, 994 .slave = &omap2420_dss_venc_hwmod, 995 .clk = "dss_ick", 996 .addr = omap2_dss_venc_addrs, 997 .fw = { 998 .omap2 = { 999 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, 1000 .flags = OMAP_FIREWALL_L4, 1001 } 1002 }, 1003 .user = OCP_USER_MPU | OCP_USER_SDMA, 1004}; 1005 1006/* dss_venc slave ports */ 1007static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = { 1008 &omap2420_l4_core__dss_venc, 1009}; 1010 1011static struct omap_hwmod omap2420_dss_venc_hwmod = { 1012 .name = "dss_venc", 1013 .class = &omap2_venc_hwmod_class, 1014 .main_clk = "dss_54m_fck", 1015 .prcm = { 1016 .omap2 = { 1017 .prcm_reg_id = 1, 1018 .module_bit = OMAP24XX_EN_DSS1_SHIFT, 1019 .module_offs = CORE_MOD, 1020 }, 1021 }, 1022 .slaves = omap2420_dss_venc_slaves, 1023 .slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves), 1024 .flags = HWMOD_NO_IDLEST, 1025}; 1026 1027/* I2C common */ 1028static struct omap_hwmod_class_sysconfig i2c_sysc = { 1029 .rev_offs = 0x00, 1030 .sysc_offs = 0x20, 1031 .syss_offs = 0x10, 1032 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 1033 .sysc_fields = &omap_hwmod_sysc_type1, 1034}; 1035 1036static struct omap_hwmod_class i2c_class = { 1037 .name = "i2c", 1038 .sysc = &i2c_sysc, 1039 .rev = OMAP_I2C_IP_VERSION_1, 1040 .reset = &omap_i2c_reset, 1041}; 1042 1043static struct omap_i2c_dev_attr i2c_dev_attr = { 1044 .flags = OMAP_I2C_FLAG_NO_FIFO | 1045 OMAP_I2C_FLAG_SIMPLE_CLOCK | 1046 OMAP_I2C_FLAG_16BIT_DATA_REG | 1047 OMAP_I2C_FLAG_BUS_SHIFT_2, 1048}; 1049 1050/* I2C1 */ 1051 1052static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = { 1053 &omap2420_l4_core__i2c1, 1054}; 1055 1056static struct omap_hwmod omap2420_i2c1_hwmod = { 1057 .name = "i2c1", 1058 .mpu_irqs = omap2_i2c1_mpu_irqs, 1059 .sdma_reqs = omap2_i2c1_sdma_reqs, 1060 .main_clk = "i2c1_fck", 1061 .prcm = { 1062 .omap2 = { 1063 .module_offs = CORE_MOD, 1064 .prcm_reg_id = 1, 1065 .module_bit = OMAP2420_EN_I2C1_SHIFT, 1066 .idlest_reg_id = 1, 1067 .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, 1068 }, 1069 }, 1070 .slaves = omap2420_i2c1_slaves, 1071 .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves), 1072 .class = &i2c_class, 1073 .dev_attr = &i2c_dev_attr, 1074 .flags = HWMOD_16BIT_REG, 1075}; 1076 1077/* I2C2 */ 1078 1079static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = { 1080 &omap2420_l4_core__i2c2, 1081}; 1082 1083static struct omap_hwmod omap2420_i2c2_hwmod = { 1084 .name = "i2c2", 1085 .mpu_irqs = omap2_i2c2_mpu_irqs, 1086 .sdma_reqs = omap2_i2c2_sdma_reqs, 1087 .main_clk = "i2c2_fck", 1088 .prcm = { 1089 .omap2 = { 1090 .module_offs = CORE_MOD, 1091 .prcm_reg_id = 1, 1092 .module_bit = OMAP2420_EN_I2C2_SHIFT, 1093 .idlest_reg_id = 1, 1094 .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, 1095 }, 1096 }, 1097 .slaves = omap2420_i2c2_slaves, 1098 .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves), 1099 .class = &i2c_class, 1100 .dev_attr = &i2c_dev_attr, 1101 .flags = HWMOD_16BIT_REG, 1102}; 1103 1104/* l4_wkup -> gpio1 */ 1105static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { 1106 { 1107 .pa_start = 0x48018000, 1108 .pa_end = 0x480181ff, 1109 .flags = ADDR_TYPE_RT 1110 }, 1111 { } 1112}; 1113 1114static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { 1115 .master = &omap2420_l4_wkup_hwmod, 1116 .slave = &omap2420_gpio1_hwmod, 1117 .clk = "gpios_ick", 1118 .addr = omap2420_gpio1_addr_space, 1119 .user = OCP_USER_MPU | OCP_USER_SDMA, 1120}; 1121 1122/* l4_wkup -> gpio2 */ 1123static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = { 1124 { 1125 .pa_start = 0x4801a000, 1126 .pa_end = 0x4801a1ff, 1127 .flags = ADDR_TYPE_RT 1128 }, 1129 { } 1130}; 1131 1132static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { 1133 .master = &omap2420_l4_wkup_hwmod, 1134 .slave = &omap2420_gpio2_hwmod, 1135 .clk = "gpios_ick", 1136 .addr = omap2420_gpio2_addr_space, 1137 .user = OCP_USER_MPU | OCP_USER_SDMA, 1138}; 1139 1140/* l4_wkup -> gpio3 */ 1141static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = { 1142 { 1143 .pa_start = 0x4801c000, 1144 .pa_end = 0x4801c1ff, 1145 .flags = ADDR_TYPE_RT 1146 }, 1147 { } 1148}; 1149 1150static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { 1151 .master = &omap2420_l4_wkup_hwmod, 1152 .slave = &omap2420_gpio3_hwmod, 1153 .clk = "gpios_ick", 1154 .addr = omap2420_gpio3_addr_space, 1155 .user = OCP_USER_MPU | OCP_USER_SDMA, 1156}; 1157 1158/* l4_wkup -> gpio4 */ 1159static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = { 1160 { 1161 .pa_start = 0x4801e000, 1162 .pa_end = 0x4801e1ff, 1163 .flags = ADDR_TYPE_RT 1164 }, 1165 { } 1166}; 1167 1168static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { 1169 .master = &omap2420_l4_wkup_hwmod, 1170 .slave = &omap2420_gpio4_hwmod, 1171 .clk = "gpios_ick", 1172 .addr = omap2420_gpio4_addr_space, 1173 .user = OCP_USER_MPU | OCP_USER_SDMA, 1174}; 1175 1176/* gpio dev_attr */ 1177static struct omap_gpio_dev_attr gpio_dev_attr = { 1178 .bank_width = 32, 1179 .dbck_flag = false, 1180}; 1181 1182/* gpio1 */ 1183static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = { 1184 &omap2420_l4_wkup__gpio1, 1185}; 1186 1187static struct omap_hwmod omap2420_gpio1_hwmod = { 1188 .name = "gpio1", 1189 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1190 .mpu_irqs = omap2_gpio1_irqs, 1191 .main_clk = "gpios_fck", 1192 .prcm = { 1193 .omap2 = { 1194 .prcm_reg_id = 1, 1195 .module_bit = OMAP24XX_EN_GPIOS_SHIFT, 1196 .module_offs = WKUP_MOD, 1197 .idlest_reg_id = 1, 1198 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, 1199 }, 1200 }, 1201 .slaves = omap2420_gpio1_slaves, 1202 .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves), 1203 .class = &omap2xxx_gpio_hwmod_class, 1204 .dev_attr = &gpio_dev_attr, 1205}; 1206 1207/* gpio2 */ 1208static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = { 1209 &omap2420_l4_wkup__gpio2, 1210}; 1211 1212static struct omap_hwmod omap2420_gpio2_hwmod = { 1213 .name = "gpio2", 1214 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1215 .mpu_irqs = omap2_gpio2_irqs, 1216 .main_clk = "gpios_fck", 1217 .prcm = { 1218 .omap2 = { 1219 .prcm_reg_id = 1, 1220 .module_bit = OMAP24XX_EN_GPIOS_SHIFT, 1221 .module_offs = WKUP_MOD, 1222 .idlest_reg_id = 1, 1223 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, 1224 }, 1225 }, 1226 .slaves = omap2420_gpio2_slaves, 1227 .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves), 1228 .class = &omap2xxx_gpio_hwmod_class, 1229 .dev_attr = &gpio_dev_attr, 1230}; 1231 1232/* gpio3 */ 1233static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = { 1234 &omap2420_l4_wkup__gpio3, 1235}; 1236 1237static struct omap_hwmod omap2420_gpio3_hwmod = { 1238 .name = "gpio3", 1239 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1240 .mpu_irqs = omap2_gpio3_irqs, 1241 .main_clk = "gpios_fck", 1242 .prcm = { 1243 .omap2 = { 1244 .prcm_reg_id = 1, 1245 .module_bit = OMAP24XX_EN_GPIOS_SHIFT, 1246 .module_offs = WKUP_MOD, 1247 .idlest_reg_id = 1, 1248 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, 1249 }, 1250 }, 1251 .slaves = omap2420_gpio3_slaves, 1252 .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves), 1253 .class = &omap2xxx_gpio_hwmod_class, 1254 .dev_attr = &gpio_dev_attr, 1255}; 1256 1257/* gpio4 */ 1258static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = { 1259 &omap2420_l4_wkup__gpio4, 1260}; 1261 1262static struct omap_hwmod omap2420_gpio4_hwmod = { 1263 .name = "gpio4", 1264 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1265 .mpu_irqs = omap2_gpio4_irqs, 1266 .main_clk = "gpios_fck", 1267 .prcm = { 1268 .omap2 = { 1269 .prcm_reg_id = 1, 1270 .module_bit = OMAP24XX_EN_GPIOS_SHIFT, 1271 .module_offs = WKUP_MOD, 1272 .idlest_reg_id = 1, 1273 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, 1274 }, 1275 }, 1276 .slaves = omap2420_gpio4_slaves, 1277 .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves), 1278 .class = &omap2xxx_gpio_hwmod_class, 1279 .dev_attr = &gpio_dev_attr, 1280}; 1281 1282/* dma attributes */ 1283static struct omap_dma_dev_attr dma_dev_attr = { 1284 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 1285 IS_CSSA_32 | IS_CDSA_32, 1286 .lch_count = 32, 1287}; 1288 1289/* dma_system -> L3 */ 1290static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { 1291 .master = &omap2420_dma_system_hwmod, 1292 .slave = &omap2420_l3_main_hwmod, 1293 .clk = "core_l3_ck", 1294 .user = OCP_USER_MPU | OCP_USER_SDMA, 1295}; 1296 1297/* dma_system master ports */ 1298static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = { 1299 &omap2420_dma_system__l3, 1300}; 1301 1302/* l4_core -> dma_system */ 1303static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { 1304 .master = &omap2420_l4_core_hwmod, 1305 .slave = &omap2420_dma_system_hwmod, 1306 .clk = "sdma_ick", 1307 .addr = omap2_dma_system_addrs, 1308 .user = OCP_USER_MPU | OCP_USER_SDMA, 1309}; 1310 1311/* dma_system slave ports */ 1312static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = { 1313 &omap2420_l4_core__dma_system, 1314}; 1315 1316static struct omap_hwmod omap2420_dma_system_hwmod = { 1317 .name = "dma", 1318 .class = &omap2xxx_dma_hwmod_class, 1319 .mpu_irqs = omap2_dma_system_irqs, 1320 .main_clk = "core_l3_ck", 1321 .slaves = omap2420_dma_system_slaves, 1322 .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves), 1323 .masters = omap2420_dma_system_masters, 1324 .masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters), 1325 .dev_attr = &dma_dev_attr, 1326 .flags = HWMOD_NO_IDLEST, 1327}; 1328 1329/* mailbox */ 1330static struct omap_hwmod omap2420_mailbox_hwmod; 1331static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { 1332 { .name = "dsp", .irq = 26 }, 1333 { .name = "iva", .irq = 34 }, 1334 { .irq = -1 } 1335}; 1336 1337/* l4_core -> mailbox */ 1338static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { 1339 .master = &omap2420_l4_core_hwmod, 1340 .slave = &omap2420_mailbox_hwmod, 1341 .addr = omap2_mailbox_addrs, 1342 .user = OCP_USER_MPU | OCP_USER_SDMA, 1343}; 1344 1345/* mailbox slave ports */ 1346static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = { 1347 &omap2420_l4_core__mailbox, 1348}; 1349 1350static struct omap_hwmod omap2420_mailbox_hwmod = { 1351 .name = "mailbox", 1352 .class = &omap2xxx_mailbox_hwmod_class, 1353 .mpu_irqs = omap2420_mailbox_irqs, 1354 .main_clk = "mailboxes_ick", 1355 .prcm = { 1356 .omap2 = { 1357 .prcm_reg_id = 1, 1358 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, 1359 .module_offs = CORE_MOD, 1360 .idlest_reg_id = 1, 1361 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, 1362 }, 1363 }, 1364 .slaves = omap2420_mailbox_slaves, 1365 .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves), 1366}; 1367 1368/* mcspi1 */ 1369static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = { 1370 &omap2420_l4_core__mcspi1, 1371}; 1372 1373static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { 1374 .num_chipselect = 4, 1375}; 1376 1377static struct omap_hwmod omap2420_mcspi1_hwmod = { 1378 .name = "mcspi1_hwmod", 1379 .mpu_irqs = omap2_mcspi1_mpu_irqs, 1380 .sdma_reqs = omap2_mcspi1_sdma_reqs, 1381 .main_clk = "mcspi1_fck", 1382 .prcm = { 1383 .omap2 = { 1384 .module_offs = CORE_MOD, 1385 .prcm_reg_id = 1, 1386 .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, 1387 .idlest_reg_id = 1, 1388 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, 1389 }, 1390 }, 1391 .slaves = omap2420_mcspi1_slaves, 1392 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves), 1393 .class = &omap2xxx_mcspi_class, 1394 .dev_attr = &omap_mcspi1_dev_attr, 1395}; 1396 1397/* mcspi2 */ 1398static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = { 1399 &omap2420_l4_core__mcspi2, 1400}; 1401 1402static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { 1403 .num_chipselect = 2, 1404}; 1405 1406static struct omap_hwmod omap2420_mcspi2_hwmod = { 1407 .name = "mcspi2_hwmod", 1408 .mpu_irqs = omap2_mcspi2_mpu_irqs, 1409 .sdma_reqs = omap2_mcspi2_sdma_reqs, 1410 .main_clk = "mcspi2_fck", 1411 .prcm = { 1412 .omap2 = { 1413 .module_offs = CORE_MOD, 1414 .prcm_reg_id = 1, 1415 .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, 1416 .idlest_reg_id = 1, 1417 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, 1418 }, 1419 }, 1420 .slaves = omap2420_mcspi2_slaves, 1421 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves), 1422 .class = &omap2xxx_mcspi_class, 1423 .dev_attr = &omap_mcspi2_dev_attr, 1424}; 1425 1426/* 1427 * 'mcbsp' class 1428 * multi channel buffered serial port controller 1429 */ 1430 1431static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = { 1432 .name = "mcbsp", 1433}; 1434 1435/* mcbsp1 */ 1436static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { 1437 { .name = "tx", .irq = 59 }, 1438 { .name = "rx", .irq = 60 }, 1439 { .irq = -1 } 1440}; 1441 1442/* l4_core -> mcbsp1 */ 1443static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = { 1444 .master = &omap2420_l4_core_hwmod, 1445 .slave = &omap2420_mcbsp1_hwmod, 1446 .clk = "mcbsp1_ick", 1447 .addr = omap2_mcbsp1_addrs, 1448 .user = OCP_USER_MPU | OCP_USER_SDMA, 1449}; 1450 1451/* mcbsp1 slave ports */ 1452static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = { 1453 &omap2420_l4_core__mcbsp1, 1454}; 1455 1456static struct omap_hwmod omap2420_mcbsp1_hwmod = { 1457 .name = "mcbsp1", 1458 .class = &omap2420_mcbsp_hwmod_class, 1459 .mpu_irqs = omap2420_mcbsp1_irqs, 1460 .sdma_reqs = omap2_mcbsp1_sdma_reqs, 1461 .main_clk = "mcbsp1_fck", 1462 .prcm = { 1463 .omap2 = { 1464 .prcm_reg_id = 1, 1465 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, 1466 .module_offs = CORE_MOD, 1467 .idlest_reg_id = 1, 1468 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, 1469 }, 1470 }, 1471 .slaves = omap2420_mcbsp1_slaves, 1472 .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp1_slaves), 1473}; 1474 1475/* mcbsp2 */ 1476static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { 1477 { .name = "tx", .irq = 62 }, 1478 { .name = "rx", .irq = 63 }, 1479 { .irq = -1 } 1480}; 1481 1482/* l4_core -> mcbsp2 */ 1483static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { 1484 .master = &omap2420_l4_core_hwmod, 1485 .slave = &omap2420_mcbsp2_hwmod, 1486 .clk = "mcbsp2_ick", 1487 .addr = omap2xxx_mcbsp2_addrs, 1488 .user = OCP_USER_MPU | OCP_USER_SDMA, 1489}; 1490 1491/* mcbsp2 slave ports */ 1492static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = { 1493 &omap2420_l4_core__mcbsp2, 1494}; 1495 1496static struct omap_hwmod omap2420_mcbsp2_hwmod = { 1497 .name = "mcbsp2", 1498 .class = &omap2420_mcbsp_hwmod_class, 1499 .mpu_irqs = omap2420_mcbsp2_irqs, 1500 .sdma_reqs = omap2_mcbsp2_sdma_reqs, 1501 .main_clk = "mcbsp2_fck", 1502 .prcm = { 1503 .omap2 = { 1504 .prcm_reg_id = 1, 1505 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, 1506 .module_offs = CORE_MOD, 1507 .idlest_reg_id = 1, 1508 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, 1509 }, 1510 }, 1511 .slaves = omap2420_mcbsp2_slaves, 1512 .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp2_slaves), 1513}; 1514 1515static __initdata struct omap_hwmod *omap2420_hwmods[] = { 1516 &omap2420_l3_main_hwmod, 1517 &omap2420_l4_core_hwmod, 1518 &omap2420_l4_wkup_hwmod, 1519 &omap2420_mpu_hwmod, 1520 &omap2420_iva_hwmod, 1521 1522 &omap2420_timer1_hwmod, 1523 &omap2420_timer2_hwmod, 1524 &omap2420_timer3_hwmod, 1525 &omap2420_timer4_hwmod, 1526 &omap2420_timer5_hwmod, 1527 &omap2420_timer6_hwmod, 1528 &omap2420_timer7_hwmod, 1529 &omap2420_timer8_hwmod, 1530 &omap2420_timer9_hwmod, 1531 &omap2420_timer10_hwmod, 1532 &omap2420_timer11_hwmod, 1533 &omap2420_timer12_hwmod, 1534 1535 &omap2420_wd_timer2_hwmod, 1536 &omap2420_uart1_hwmod, 1537 &omap2420_uart2_hwmod, 1538 &omap2420_uart3_hwmod, 1539 /* dss class */ 1540 &omap2420_dss_core_hwmod, 1541 &omap2420_dss_dispc_hwmod, 1542 &omap2420_dss_rfbi_hwmod, 1543 &omap2420_dss_venc_hwmod, 1544 /* i2c class */ 1545 &omap2420_i2c1_hwmod, 1546 &omap2420_i2c2_hwmod, 1547 1548 /* gpio class */ 1549 &omap2420_gpio1_hwmod, 1550 &omap2420_gpio2_hwmod, 1551 &omap2420_gpio3_hwmod, 1552 &omap2420_gpio4_hwmod, 1553 1554 /* dma_system class*/ 1555 &omap2420_dma_system_hwmod, 1556 1557 /* mailbox class */ 1558 &omap2420_mailbox_hwmod, 1559 1560 /* mcbsp class */ 1561 &omap2420_mcbsp1_hwmod, 1562 &omap2420_mcbsp2_hwmod, 1563 1564 /* mcspi class */ 1565 &omap2420_mcspi1_hwmod, 1566 &omap2420_mcspi2_hwmod, 1567 NULL, 1568}; 1569 1570int __init omap2420_hwmod_init(void) 1571{ 1572 return omap_hwmod_register(omap2420_hwmods); 1573} 1574