1/* 2 * Hardware modules present on the OMAP44xx chips 3 * 4 * Copyright (C) 2009-2011 Texas Instruments, Inc. 5 * Copyright (C) 2009-2010 Nokia Corporation 6 * 7 * Paul Walmsley 8 * Benoit Cousson 9 * 10 * This file is automatically generated from the OMAP hardware databases. 11 * We respectfully ask that any modifications to this file be coordinated 12 * with the public linux-omap@vger.kernel.org mailing list and the 13 * authors above to ensure that the autogeneration scripts are kept 14 * up-to-date with the file contents. 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License version 2 as 18 * published by the Free Software Foundation. 19 */ 20 21#include <linux/io.h> 22 23#include <plat/omap_hwmod.h> 24#include <plat/cpu.h> 25#include <plat/i2c.h> 26#include <plat/gpio.h> 27#include <plat/dma.h> 28#include <plat/mcspi.h> 29#include <plat/mcbsp.h> 30#include <plat/mmc.h> 31#include <plat/dmtimer.h> 32#include <plat/common.h> 33 34#include "omap_hwmod_common_data.h" 35 36#include "smartreflex.h" 37#include "cm1_44xx.h" 38#include "cm2_44xx.h" 39#include "prm44xx.h" 40#include "prm-regbits-44xx.h" 41#include "wd_timer.h" 42 43/* Base offset for all OMAP4 interrupts external to MPUSS */ 44#define OMAP44XX_IRQ_GIC_START 32 45 46/* Base offset for all OMAP4 dma requests */ 47#define OMAP44XX_DMA_REQ_START 1 48 49/* Backward references (IPs with Bus Master capability) */ 50static struct omap_hwmod omap44xx_aess_hwmod; 51static struct omap_hwmod omap44xx_dma_system_hwmod; 52static struct omap_hwmod omap44xx_dmm_hwmod; 53static struct omap_hwmod omap44xx_dsp_hwmod; 54static struct omap_hwmod omap44xx_dss_hwmod; 55static struct omap_hwmod omap44xx_emif_fw_hwmod; 56static struct omap_hwmod omap44xx_hsi_hwmod; 57static struct omap_hwmod omap44xx_ipu_hwmod; 58static struct omap_hwmod omap44xx_iss_hwmod; 59static struct omap_hwmod omap44xx_iva_hwmod; 60static struct omap_hwmod omap44xx_l3_instr_hwmod; 61static struct omap_hwmod omap44xx_l3_main_1_hwmod; 62static struct omap_hwmod omap44xx_l3_main_2_hwmod; 63static struct omap_hwmod omap44xx_l3_main_3_hwmod; 64static struct omap_hwmod omap44xx_l4_abe_hwmod; 65static struct omap_hwmod omap44xx_l4_cfg_hwmod; 66static struct omap_hwmod omap44xx_l4_per_hwmod; 67static struct omap_hwmod omap44xx_l4_wkup_hwmod; 68static struct omap_hwmod omap44xx_mmc1_hwmod; 69static struct omap_hwmod omap44xx_mmc2_hwmod; 70static struct omap_hwmod omap44xx_mpu_hwmod; 71static struct omap_hwmod omap44xx_mpu_private_hwmod; 72static struct omap_hwmod omap44xx_usb_otg_hs_hwmod; 73static struct omap_hwmod omap44xx_usb_host_hs_hwmod; 74static struct omap_hwmod omap44xx_usb_tll_hs_hwmod; 75 76/* 77 * Interconnects omap_hwmod structures 78 * hwmods that compose the global OMAP interconnect 79 */ 80 81/* 82 * 'dmm' class 83 * instance(s): dmm 84 */ 85static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { 86 .name = "dmm", 87}; 88 89/* dmm */ 90static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { 91 { .irq = 113 + OMAP44XX_IRQ_GIC_START }, 92 { .irq = -1 } 93}; 94 95/* l3_main_1 -> dmm */ 96static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { 97 .master = &omap44xx_l3_main_1_hwmod, 98 .slave = &omap44xx_dmm_hwmod, 99 .clk = "l3_div_ck", 100 .user = OCP_USER_SDMA, 101}; 102 103static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { 104 { 105 .pa_start = 0x4e000000, 106 .pa_end = 0x4e0007ff, 107 .flags = ADDR_TYPE_RT 108 }, 109 { } 110}; 111 112/* mpu -> dmm */ 113static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { 114 .master = &omap44xx_mpu_hwmod, 115 .slave = &omap44xx_dmm_hwmod, 116 .clk = "l3_div_ck", 117 .addr = omap44xx_dmm_addrs, 118 .user = OCP_USER_MPU, 119}; 120 121/* dmm slave ports */ 122static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = { 123 &omap44xx_l3_main_1__dmm, 124 &omap44xx_mpu__dmm, 125}; 126 127static struct omap_hwmod omap44xx_dmm_hwmod = { 128 .name = "dmm", 129 .class = &omap44xx_dmm_hwmod_class, 130 .clkdm_name = "l3_emif_clkdm", 131 .prcm = { 132 .omap4 = { 133 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, 134 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, 135 }, 136 }, 137 .slaves = omap44xx_dmm_slaves, 138 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves), 139 .mpu_irqs = omap44xx_dmm_irqs, 140}; 141 142/* 143 * 'emif_fw' class 144 * instance(s): emif_fw 145 */ 146static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { 147 .name = "emif_fw", 148}; 149 150/* emif_fw */ 151/* dmm -> emif_fw */ 152static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { 153 .master = &omap44xx_dmm_hwmod, 154 .slave = &omap44xx_emif_fw_hwmod, 155 .clk = "l3_div_ck", 156 .user = OCP_USER_MPU | OCP_USER_SDMA, 157}; 158 159static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { 160 { 161 .pa_start = 0x4a20c000, 162 .pa_end = 0x4a20c0ff, 163 .flags = ADDR_TYPE_RT 164 }, 165 { } 166}; 167 168/* l4_cfg -> emif_fw */ 169static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { 170 .master = &omap44xx_l4_cfg_hwmod, 171 .slave = &omap44xx_emif_fw_hwmod, 172 .clk = "l4_div_ck", 173 .addr = omap44xx_emif_fw_addrs, 174 .user = OCP_USER_MPU, 175}; 176 177/* emif_fw slave ports */ 178static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = { 179 &omap44xx_dmm__emif_fw, 180 &omap44xx_l4_cfg__emif_fw, 181}; 182 183static struct omap_hwmod omap44xx_emif_fw_hwmod = { 184 .name = "emif_fw", 185 .class = &omap44xx_emif_fw_hwmod_class, 186 .clkdm_name = "l3_emif_clkdm", 187 .prcm = { 188 .omap4 = { 189 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET, 190 .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET, 191 }, 192 }, 193 .slaves = omap44xx_emif_fw_slaves, 194 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves), 195}; 196 197/* 198 * 'l3' class 199 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 200 */ 201static struct omap_hwmod_class omap44xx_l3_hwmod_class = { 202 .name = "l3", 203}; 204 205/* l3_instr */ 206/* iva -> l3_instr */ 207static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { 208 .master = &omap44xx_iva_hwmod, 209 .slave = &omap44xx_l3_instr_hwmod, 210 .clk = "l3_div_ck", 211 .user = OCP_USER_MPU | OCP_USER_SDMA, 212}; 213 214/* l3_main_3 -> l3_instr */ 215static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { 216 .master = &omap44xx_l3_main_3_hwmod, 217 .slave = &omap44xx_l3_instr_hwmod, 218 .clk = "l3_div_ck", 219 .user = OCP_USER_MPU | OCP_USER_SDMA, 220}; 221 222/* l3_instr slave ports */ 223static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = { 224 &omap44xx_iva__l3_instr, 225 &omap44xx_l3_main_3__l3_instr, 226}; 227 228static struct omap_hwmod omap44xx_l3_instr_hwmod = { 229 .name = "l3_instr", 230 .class = &omap44xx_l3_hwmod_class, 231 .clkdm_name = "l3_instr_clkdm", 232 .prcm = { 233 .omap4 = { 234 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, 235 .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, 236 .modulemode = MODULEMODE_HWCTRL, 237 }, 238 }, 239 .slaves = omap44xx_l3_instr_slaves, 240 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves), 241}; 242 243/* l3_main_1 */ 244static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = { 245 { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START }, 246 { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START }, 247 { .irq = -1 } 248}; 249 250/* dsp -> l3_main_1 */ 251static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { 252 .master = &omap44xx_dsp_hwmod, 253 .slave = &omap44xx_l3_main_1_hwmod, 254 .clk = "l3_div_ck", 255 .user = OCP_USER_MPU | OCP_USER_SDMA, 256}; 257 258/* dss -> l3_main_1 */ 259static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { 260 .master = &omap44xx_dss_hwmod, 261 .slave = &omap44xx_l3_main_1_hwmod, 262 .clk = "l3_div_ck", 263 .user = OCP_USER_MPU | OCP_USER_SDMA, 264}; 265 266/* l3_main_2 -> l3_main_1 */ 267static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { 268 .master = &omap44xx_l3_main_2_hwmod, 269 .slave = &omap44xx_l3_main_1_hwmod, 270 .clk = "l3_div_ck", 271 .user = OCP_USER_MPU | OCP_USER_SDMA, 272}; 273 274/* l4_cfg -> l3_main_1 */ 275static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { 276 .master = &omap44xx_l4_cfg_hwmod, 277 .slave = &omap44xx_l3_main_1_hwmod, 278 .clk = "l4_div_ck", 279 .user = OCP_USER_MPU | OCP_USER_SDMA, 280}; 281 282/* mmc1 -> l3_main_1 */ 283static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { 284 .master = &omap44xx_mmc1_hwmod, 285 .slave = &omap44xx_l3_main_1_hwmod, 286 .clk = "l3_div_ck", 287 .user = OCP_USER_MPU | OCP_USER_SDMA, 288}; 289 290/* mmc2 -> l3_main_1 */ 291static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { 292 .master = &omap44xx_mmc2_hwmod, 293 .slave = &omap44xx_l3_main_1_hwmod, 294 .clk = "l3_div_ck", 295 .user = OCP_USER_MPU | OCP_USER_SDMA, 296}; 297 298static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { 299 { 300 .pa_start = 0x44000000, 301 .pa_end = 0x44000fff, 302 .flags = ADDR_TYPE_RT 303 }, 304 { } 305}; 306 307/* mpu -> l3_main_1 */ 308static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { 309 .master = &omap44xx_mpu_hwmod, 310 .slave = &omap44xx_l3_main_1_hwmod, 311 .clk = "l3_div_ck", 312 .addr = omap44xx_l3_main_1_addrs, 313 .user = OCP_USER_MPU, 314}; 315 316/* l3_main_1 slave ports */ 317static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { 318 &omap44xx_dsp__l3_main_1, 319 &omap44xx_dss__l3_main_1, 320 &omap44xx_l3_main_2__l3_main_1, 321 &omap44xx_l4_cfg__l3_main_1, 322 &omap44xx_mmc1__l3_main_1, 323 &omap44xx_mmc2__l3_main_1, 324 &omap44xx_mpu__l3_main_1, 325}; 326 327static struct omap_hwmod omap44xx_l3_main_1_hwmod = { 328 .name = "l3_main_1", 329 .class = &omap44xx_l3_hwmod_class, 330 .clkdm_name = "l3_1_clkdm", 331 .mpu_irqs = omap44xx_l3_main_1_irqs, 332 .prcm = { 333 .omap4 = { 334 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET, 335 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET, 336 }, 337 }, 338 .slaves = omap44xx_l3_main_1_slaves, 339 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), 340}; 341 342/* l3_main_2 */ 343/* dma_system -> l3_main_2 */ 344static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { 345 .master = &omap44xx_dma_system_hwmod, 346 .slave = &omap44xx_l3_main_2_hwmod, 347 .clk = "l3_div_ck", 348 .user = OCP_USER_MPU | OCP_USER_SDMA, 349}; 350 351/* hsi -> l3_main_2 */ 352static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { 353 .master = &omap44xx_hsi_hwmod, 354 .slave = &omap44xx_l3_main_2_hwmod, 355 .clk = "l3_div_ck", 356 .user = OCP_USER_MPU | OCP_USER_SDMA, 357}; 358 359/* ipu -> l3_main_2 */ 360static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { 361 .master = &omap44xx_ipu_hwmod, 362 .slave = &omap44xx_l3_main_2_hwmod, 363 .clk = "l3_div_ck", 364 .user = OCP_USER_MPU | OCP_USER_SDMA, 365}; 366 367/* iss -> l3_main_2 */ 368static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { 369 .master = &omap44xx_iss_hwmod, 370 .slave = &omap44xx_l3_main_2_hwmod, 371 .clk = "l3_div_ck", 372 .user = OCP_USER_MPU | OCP_USER_SDMA, 373}; 374 375/* iva -> l3_main_2 */ 376static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { 377 .master = &omap44xx_iva_hwmod, 378 .slave = &omap44xx_l3_main_2_hwmod, 379 .clk = "l3_div_ck", 380 .user = OCP_USER_MPU | OCP_USER_SDMA, 381}; 382 383static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = { 384 { 385 .pa_start = 0x44800000, 386 .pa_end = 0x44801fff, 387 .flags = ADDR_TYPE_RT 388 }, 389 { } 390}; 391 392/* l3_main_1 -> l3_main_2 */ 393static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { 394 .master = &omap44xx_l3_main_1_hwmod, 395 .slave = &omap44xx_l3_main_2_hwmod, 396 .clk = "l3_div_ck", 397 .addr = omap44xx_l3_main_2_addrs, 398 .user = OCP_USER_MPU, 399}; 400 401/* l4_cfg -> l3_main_2 */ 402static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { 403 .master = &omap44xx_l4_cfg_hwmod, 404 .slave = &omap44xx_l3_main_2_hwmod, 405 .clk = "l4_div_ck", 406 .user = OCP_USER_MPU | OCP_USER_SDMA, 407}; 408 409/* usb_otg_hs -> l3_main_2 */ 410static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { 411 .master = &omap44xx_usb_otg_hs_hwmod, 412 .slave = &omap44xx_l3_main_2_hwmod, 413 .clk = "l3_div_ck", 414 .user = OCP_USER_MPU | OCP_USER_SDMA, 415}; 416 417/* l3_main_2 slave ports */ 418static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { 419 &omap44xx_dma_system__l3_main_2, 420 &omap44xx_hsi__l3_main_2, 421 &omap44xx_ipu__l3_main_2, 422 &omap44xx_iss__l3_main_2, 423 &omap44xx_iva__l3_main_2, 424 &omap44xx_l3_main_1__l3_main_2, 425 &omap44xx_l4_cfg__l3_main_2, 426 &omap44xx_usb_otg_hs__l3_main_2, 427}; 428 429static struct omap_hwmod omap44xx_l3_main_2_hwmod = { 430 .name = "l3_main_2", 431 .class = &omap44xx_l3_hwmod_class, 432 .clkdm_name = "l3_2_clkdm", 433 .prcm = { 434 .omap4 = { 435 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET, 436 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET, 437 }, 438 }, 439 .slaves = omap44xx_l3_main_2_slaves, 440 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves), 441}; 442 443/* l3_main_3 */ 444static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { 445 { 446 .pa_start = 0x45000000, 447 .pa_end = 0x45000fff, 448 .flags = ADDR_TYPE_RT 449 }, 450 { } 451}; 452 453/* l3_main_1 -> l3_main_3 */ 454static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { 455 .master = &omap44xx_l3_main_1_hwmod, 456 .slave = &omap44xx_l3_main_3_hwmod, 457 .clk = "l3_div_ck", 458 .addr = omap44xx_l3_main_3_addrs, 459 .user = OCP_USER_MPU, 460}; 461 462/* l3_main_2 -> l3_main_3 */ 463static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { 464 .master = &omap44xx_l3_main_2_hwmod, 465 .slave = &omap44xx_l3_main_3_hwmod, 466 .clk = "l3_div_ck", 467 .user = OCP_USER_MPU | OCP_USER_SDMA, 468}; 469 470/* l4_cfg -> l3_main_3 */ 471static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { 472 .master = &omap44xx_l4_cfg_hwmod, 473 .slave = &omap44xx_l3_main_3_hwmod, 474 .clk = "l4_div_ck", 475 .user = OCP_USER_MPU | OCP_USER_SDMA, 476}; 477 478/* l3_main_3 slave ports */ 479static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = { 480 &omap44xx_l3_main_1__l3_main_3, 481 &omap44xx_l3_main_2__l3_main_3, 482 &omap44xx_l4_cfg__l3_main_3, 483}; 484 485static struct omap_hwmod omap44xx_l3_main_3_hwmod = { 486 .name = "l3_main_3", 487 .class = &omap44xx_l3_hwmod_class, 488 .clkdm_name = "l3_instr_clkdm", 489 .prcm = { 490 .omap4 = { 491 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET, 492 .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET, 493 .modulemode = MODULEMODE_HWCTRL, 494 }, 495 }, 496 .slaves = omap44xx_l3_main_3_slaves, 497 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves), 498}; 499 500/* 501 * 'l4' class 502 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup 503 */ 504static struct omap_hwmod_class omap44xx_l4_hwmod_class = { 505 .name = "l4", 506}; 507 508/* l4_abe */ 509/* aess -> l4_abe */ 510static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = { 511 .master = &omap44xx_aess_hwmod, 512 .slave = &omap44xx_l4_abe_hwmod, 513 .clk = "ocp_abe_iclk", 514 .user = OCP_USER_MPU | OCP_USER_SDMA, 515}; 516 517/* dsp -> l4_abe */ 518static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { 519 .master = &omap44xx_dsp_hwmod, 520 .slave = &omap44xx_l4_abe_hwmod, 521 .clk = "ocp_abe_iclk", 522 .user = OCP_USER_MPU | OCP_USER_SDMA, 523}; 524 525/* l3_main_1 -> l4_abe */ 526static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { 527 .master = &omap44xx_l3_main_1_hwmod, 528 .slave = &omap44xx_l4_abe_hwmod, 529 .clk = "l3_div_ck", 530 .user = OCP_USER_MPU | OCP_USER_SDMA, 531}; 532 533/* mpu -> l4_abe */ 534static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { 535 .master = &omap44xx_mpu_hwmod, 536 .slave = &omap44xx_l4_abe_hwmod, 537 .clk = "ocp_abe_iclk", 538 .user = OCP_USER_MPU | OCP_USER_SDMA, 539}; 540 541/* l4_abe slave ports */ 542static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = { 543 &omap44xx_aess__l4_abe, 544 &omap44xx_dsp__l4_abe, 545 &omap44xx_l3_main_1__l4_abe, 546 &omap44xx_mpu__l4_abe, 547}; 548 549static struct omap_hwmod omap44xx_l4_abe_hwmod = { 550 .name = "l4_abe", 551 .class = &omap44xx_l4_hwmod_class, 552 .clkdm_name = "abe_clkdm", 553 .prcm = { 554 .omap4 = { 555 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, 556 }, 557 }, 558 .slaves = omap44xx_l4_abe_slaves, 559 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves), 560}; 561 562/* l4_cfg */ 563/* l3_main_1 -> l4_cfg */ 564static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { 565 .master = &omap44xx_l3_main_1_hwmod, 566 .slave = &omap44xx_l4_cfg_hwmod, 567 .clk = "l3_div_ck", 568 .user = OCP_USER_MPU | OCP_USER_SDMA, 569}; 570 571/* l4_cfg slave ports */ 572static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = { 573 &omap44xx_l3_main_1__l4_cfg, 574}; 575 576static struct omap_hwmod omap44xx_l4_cfg_hwmod = { 577 .name = "l4_cfg", 578 .class = &omap44xx_l4_hwmod_class, 579 .clkdm_name = "l4_cfg_clkdm", 580 .prcm = { 581 .omap4 = { 582 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, 583 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, 584 }, 585 }, 586 .slaves = omap44xx_l4_cfg_slaves, 587 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves), 588}; 589 590/* l4_per */ 591/* l3_main_2 -> l4_per */ 592static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { 593 .master = &omap44xx_l3_main_2_hwmod, 594 .slave = &omap44xx_l4_per_hwmod, 595 .clk = "l3_div_ck", 596 .user = OCP_USER_MPU | OCP_USER_SDMA, 597}; 598 599/* l4_per slave ports */ 600static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = { 601 &omap44xx_l3_main_2__l4_per, 602}; 603 604static struct omap_hwmod omap44xx_l4_per_hwmod = { 605 .name = "l4_per", 606 .class = &omap44xx_l4_hwmod_class, 607 .clkdm_name = "l4_per_clkdm", 608 .prcm = { 609 .omap4 = { 610 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET, 611 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET, 612 }, 613 }, 614 .slaves = omap44xx_l4_per_slaves, 615 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves), 616}; 617 618/* l4_wkup */ 619/* l4_cfg -> l4_wkup */ 620static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { 621 .master = &omap44xx_l4_cfg_hwmod, 622 .slave = &omap44xx_l4_wkup_hwmod, 623 .clk = "l4_div_ck", 624 .user = OCP_USER_MPU | OCP_USER_SDMA, 625}; 626 627/* l4_wkup slave ports */ 628static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = { 629 &omap44xx_l4_cfg__l4_wkup, 630}; 631 632static struct omap_hwmod omap44xx_l4_wkup_hwmod = { 633 .name = "l4_wkup", 634 .class = &omap44xx_l4_hwmod_class, 635 .clkdm_name = "l4_wkup_clkdm", 636 .prcm = { 637 .omap4 = { 638 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, 639 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET, 640 }, 641 }, 642 .slaves = omap44xx_l4_wkup_slaves, 643 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves), 644}; 645 646/* 647 * 'mpu_bus' class 648 * instance(s): mpu_private 649 */ 650static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { 651 .name = "mpu_bus", 652}; 653 654/* mpu_private */ 655/* mpu -> mpu_private */ 656static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { 657 .master = &omap44xx_mpu_hwmod, 658 .slave = &omap44xx_mpu_private_hwmod, 659 .clk = "l3_div_ck", 660 .user = OCP_USER_MPU | OCP_USER_SDMA, 661}; 662 663/* mpu_private slave ports */ 664static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = { 665 &omap44xx_mpu__mpu_private, 666}; 667 668static struct omap_hwmod omap44xx_mpu_private_hwmod = { 669 .name = "mpu_private", 670 .class = &omap44xx_mpu_bus_hwmod_class, 671 .clkdm_name = "mpuss_clkdm", 672 .slaves = omap44xx_mpu_private_slaves, 673 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves), 674}; 675 676/* 677 * Modules omap_hwmod structures 678 * 679 * The following IPs are excluded for the moment because: 680 * - They do not need an explicit SW control using omap_hwmod API. 681 * - They still need to be validated with the driver 682 * properly adapted to omap_hwmod / omap_device 683 * 684 * c2c 685 * c2c_target_fw 686 * cm_core 687 * cm_core_aon 688 * ctrl_module_core 689 * ctrl_module_pad_core 690 * ctrl_module_pad_wkup 691 * ctrl_module_wkup 692 * debugss 693 * efuse_ctrl_cust 694 * efuse_ctrl_std 695 * elm 696 * emif1 697 * emif2 698 * fdif 699 * gpmc 700 * gpu 701 * hdq1w 702 * mcasp 703 * mpu_c0 704 * mpu_c1 705 * ocmc_ram 706 * ocp2scp_usb_phy 707 * ocp_wp_noc 708 * prcm_mpu 709 * prm 710 * scrm 711 * sl2if 712 * slimbus1 713 * slimbus2 714 * usb_host_fs 715 * usb_host_hs 716 * usb_phy_cm 717 * usb_tll_hs 718 * usim 719 */ 720 721/* 722 * 'aess' class 723 * audio engine sub system 724 */ 725 726static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = { 727 .rev_offs = 0x0000, 728 .sysc_offs = 0x0010, 729 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), 730 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 731 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART | 732 MSTANDBY_SMART_WKUP), 733 .sysc_fields = &omap_hwmod_sysc_type2, 734}; 735 736static struct omap_hwmod_class omap44xx_aess_hwmod_class = { 737 .name = "aess", 738 .sysc = &omap44xx_aess_sysc, 739}; 740 741/* aess */ 742static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = { 743 { .irq = 99 + OMAP44XX_IRQ_GIC_START }, 744 { .irq = -1 } 745}; 746 747static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { 748 { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START }, 749 { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START }, 750 { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START }, 751 { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START }, 752 { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START }, 753 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START }, 754 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START }, 755 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START }, 756 { .dma_req = -1 } 757}; 758 759/* aess master ports */ 760static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = { 761 &omap44xx_aess__l4_abe, 762}; 763 764static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { 765 { 766 .pa_start = 0x401f1000, 767 .pa_end = 0x401f13ff, 768 .flags = ADDR_TYPE_RT 769 }, 770 { } 771}; 772 773/* l4_abe -> aess */ 774static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = { 775 .master = &omap44xx_l4_abe_hwmod, 776 .slave = &omap44xx_aess_hwmod, 777 .clk = "ocp_abe_iclk", 778 .addr = omap44xx_aess_addrs, 779 .user = OCP_USER_MPU, 780}; 781 782static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { 783 { 784 .pa_start = 0x490f1000, 785 .pa_end = 0x490f13ff, 786 .flags = ADDR_TYPE_RT 787 }, 788 { } 789}; 790 791/* l4_abe -> aess (dma) */ 792static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = { 793 .master = &omap44xx_l4_abe_hwmod, 794 .slave = &omap44xx_aess_hwmod, 795 .clk = "ocp_abe_iclk", 796 .addr = omap44xx_aess_dma_addrs, 797 .user = OCP_USER_SDMA, 798}; 799 800/* aess slave ports */ 801static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = { 802 &omap44xx_l4_abe__aess, 803 &omap44xx_l4_abe__aess_dma, 804}; 805 806static struct omap_hwmod omap44xx_aess_hwmod = { 807 .name = "aess", 808 .class = &omap44xx_aess_hwmod_class, 809 .clkdm_name = "abe_clkdm", 810 .mpu_irqs = omap44xx_aess_irqs, 811 .sdma_reqs = omap44xx_aess_sdma_reqs, 812 .main_clk = "aess_fck", 813 .prcm = { 814 .omap4 = { 815 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, 816 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, 817 .modulemode = MODULEMODE_SWCTRL, 818 }, 819 }, 820 .slaves = omap44xx_aess_slaves, 821 .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves), 822 .masters = omap44xx_aess_masters, 823 .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters), 824}; 825 826/* 827 * 'bandgap' class 828 * bangap reference for ldo regulators 829 */ 830 831static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = { 832 .name = "bandgap", 833}; 834 835/* bandgap */ 836static struct omap_hwmod_opt_clk bandgap_opt_clks[] = { 837 { .role = "fclk", .clk = "bandgap_fclk" }, 838}; 839 840static struct omap_hwmod omap44xx_bandgap_hwmod = { 841 .name = "bandgap", 842 .class = &omap44xx_bandgap_hwmod_class, 843 .clkdm_name = "l4_wkup_clkdm", 844 .prcm = { 845 .omap4 = { 846 .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET, 847 }, 848 }, 849 .opt_clks = bandgap_opt_clks, 850 .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks), 851}; 852 853/* 854 * 'counter' class 855 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock 856 */ 857 858static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = { 859 .rev_offs = 0x0000, 860 .sysc_offs = 0x0004, 861 .sysc_flags = SYSC_HAS_SIDLEMODE, 862 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 863 SIDLE_SMART_WKUP), 864 .sysc_fields = &omap_hwmod_sysc_type1, 865}; 866 867static struct omap_hwmod_class omap44xx_counter_hwmod_class = { 868 .name = "counter", 869 .sysc = &omap44xx_counter_sysc, 870}; 871 872/* counter_32k */ 873static struct omap_hwmod omap44xx_counter_32k_hwmod; 874static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { 875 { 876 .pa_start = 0x4a304000, 877 .pa_end = 0x4a30401f, 878 .flags = ADDR_TYPE_RT 879 }, 880 { } 881}; 882 883/* l4_wkup -> counter_32k */ 884static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { 885 .master = &omap44xx_l4_wkup_hwmod, 886 .slave = &omap44xx_counter_32k_hwmod, 887 .clk = "l4_wkup_clk_mux_ck", 888 .addr = omap44xx_counter_32k_addrs, 889 .user = OCP_USER_MPU | OCP_USER_SDMA, 890}; 891 892/* counter_32k slave ports */ 893static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = { 894 &omap44xx_l4_wkup__counter_32k, 895}; 896 897static struct omap_hwmod omap44xx_counter_32k_hwmod = { 898 .name = "counter_32k", 899 .class = &omap44xx_counter_hwmod_class, 900 .clkdm_name = "l4_wkup_clkdm", 901 .flags = HWMOD_SWSUP_SIDLE, 902 .main_clk = "sys_32k_ck", 903 .prcm = { 904 .omap4 = { 905 .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, 906 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, 907 }, 908 }, 909 .slaves = omap44xx_counter_32k_slaves, 910 .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves), 911}; 912 913/* 914 * 'dma' class 915 * dma controller for data exchange between memory to memory (i.e. internal or 916 * external memory) and gp peripherals to memory or memory to gp peripherals 917 */ 918 919static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = { 920 .rev_offs = 0x0000, 921 .sysc_offs = 0x002c, 922 .syss_offs = 0x0028, 923 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 924 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | 925 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 926 SYSS_HAS_RESET_STATUS), 927 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 928 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 929 .sysc_fields = &omap_hwmod_sysc_type1, 930}; 931 932static struct omap_hwmod_class omap44xx_dma_hwmod_class = { 933 .name = "dma", 934 .sysc = &omap44xx_dma_sysc, 935}; 936 937/* dma dev_attr */ 938static struct omap_dma_dev_attr dma_dev_attr = { 939 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 940 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, 941 .lch_count = 32, 942}; 943 944/* dma_system */ 945static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { 946 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START }, 947 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, 948 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, 949 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, 950 { .irq = -1 } 951}; 952 953/* dma_system master ports */ 954static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = { 955 &omap44xx_dma_system__l3_main_2, 956}; 957 958static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { 959 { 960 .pa_start = 0x4a056000, 961 .pa_end = 0x4a056fff, 962 .flags = ADDR_TYPE_RT 963 }, 964 { } 965}; 966 967/* l4_cfg -> dma_system */ 968static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { 969 .master = &omap44xx_l4_cfg_hwmod, 970 .slave = &omap44xx_dma_system_hwmod, 971 .clk = "l4_div_ck", 972 .addr = omap44xx_dma_system_addrs, 973 .user = OCP_USER_MPU | OCP_USER_SDMA, 974}; 975 976/* dma_system slave ports */ 977static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = { 978 &omap44xx_l4_cfg__dma_system, 979}; 980 981static struct omap_hwmod omap44xx_dma_system_hwmod = { 982 .name = "dma_system", 983 .class = &omap44xx_dma_hwmod_class, 984 .clkdm_name = "l3_dma_clkdm", 985 .mpu_irqs = omap44xx_dma_system_irqs, 986 .main_clk = "l3_div_ck", 987 .prcm = { 988 .omap4 = { 989 .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET, 990 .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET, 991 }, 992 }, 993 .dev_attr = &dma_dev_attr, 994 .slaves = omap44xx_dma_system_slaves, 995 .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves), 996 .masters = omap44xx_dma_system_masters, 997 .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters), 998}; 999 1000/* 1001 * 'dmic' class 1002 * digital microphone controller 1003 */ 1004 1005static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = { 1006 .rev_offs = 0x0000, 1007 .sysc_offs = 0x0010, 1008 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | 1009 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 1010 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1011 SIDLE_SMART_WKUP), 1012 .sysc_fields = &omap_hwmod_sysc_type2, 1013}; 1014 1015static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { 1016 .name = "dmic", 1017 .sysc = &omap44xx_dmic_sysc, 1018}; 1019 1020/* dmic */ 1021static struct omap_hwmod omap44xx_dmic_hwmod; 1022static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { 1023 { .irq = 114 + OMAP44XX_IRQ_GIC_START }, 1024 { .irq = -1 } 1025}; 1026 1027static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { 1028 { .dma_req = 66 + OMAP44XX_DMA_REQ_START }, 1029 { .dma_req = -1 } 1030}; 1031 1032static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { 1033 { 1034 .name = "mpu", 1035 .pa_start = 0x4012e000, 1036 .pa_end = 0x4012e07f, 1037 .flags = ADDR_TYPE_RT 1038 }, 1039 { } 1040}; 1041 1042/* l4_abe -> dmic */ 1043static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { 1044 .master = &omap44xx_l4_abe_hwmod, 1045 .slave = &omap44xx_dmic_hwmod, 1046 .clk = "ocp_abe_iclk", 1047 .addr = omap44xx_dmic_addrs, 1048 .user = OCP_USER_MPU, 1049}; 1050 1051static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { 1052 { 1053 .name = "dma", 1054 .pa_start = 0x4902e000, 1055 .pa_end = 0x4902e07f, 1056 .flags = ADDR_TYPE_RT 1057 }, 1058 { } 1059}; 1060 1061/* l4_abe -> dmic (dma) */ 1062static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { 1063 .master = &omap44xx_l4_abe_hwmod, 1064 .slave = &omap44xx_dmic_hwmod, 1065 .clk = "ocp_abe_iclk", 1066 .addr = omap44xx_dmic_dma_addrs, 1067 .user = OCP_USER_SDMA, 1068}; 1069 1070/* dmic slave ports */ 1071static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = { 1072 &omap44xx_l4_abe__dmic, 1073 &omap44xx_l4_abe__dmic_dma, 1074}; 1075 1076static struct omap_hwmod omap44xx_dmic_hwmod = { 1077 .name = "dmic", 1078 .class = &omap44xx_dmic_hwmod_class, 1079 .clkdm_name = "abe_clkdm", 1080 .mpu_irqs = omap44xx_dmic_irqs, 1081 .sdma_reqs = omap44xx_dmic_sdma_reqs, 1082 .main_clk = "dmic_fck", 1083 .prcm = { 1084 .omap4 = { 1085 .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET, 1086 .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET, 1087 .modulemode = MODULEMODE_SWCTRL, 1088 }, 1089 }, 1090 .slaves = omap44xx_dmic_slaves, 1091 .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves), 1092}; 1093 1094/* 1095 * 'dsp' class 1096 * dsp sub-system 1097 */ 1098 1099static struct omap_hwmod_class omap44xx_dsp_hwmod_class = { 1100 .name = "dsp", 1101}; 1102 1103/* dsp */ 1104static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { 1105 { .irq = 28 + OMAP44XX_IRQ_GIC_START }, 1106 { .irq = -1 } 1107}; 1108 1109static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { 1110 { .name = "mmu_cache", .rst_shift = 1 }, 1111}; 1112 1113static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = { 1114 { .name = "dsp", .rst_shift = 0 }, 1115}; 1116 1117/* dsp -> iva */ 1118static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { 1119 .master = &omap44xx_dsp_hwmod, 1120 .slave = &omap44xx_iva_hwmod, 1121 .clk = "dpll_iva_m5x2_ck", 1122}; 1123 1124/* dsp master ports */ 1125static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = { 1126 &omap44xx_dsp__l3_main_1, 1127 &omap44xx_dsp__l4_abe, 1128 &omap44xx_dsp__iva, 1129}; 1130 1131/* l4_cfg -> dsp */ 1132static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { 1133 .master = &omap44xx_l4_cfg_hwmod, 1134 .slave = &omap44xx_dsp_hwmod, 1135 .clk = "l4_div_ck", 1136 .user = OCP_USER_MPU | OCP_USER_SDMA, 1137}; 1138 1139/* dsp slave ports */ 1140static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = { 1141 &omap44xx_l4_cfg__dsp, 1142}; 1143 1144/* Pseudo hwmod for reset control purpose only */ 1145static struct omap_hwmod omap44xx_dsp_c0_hwmod = { 1146 .name = "dsp_c0", 1147 .class = &omap44xx_dsp_hwmod_class, 1148 .clkdm_name = "tesla_clkdm", 1149 .flags = HWMOD_INIT_NO_RESET, 1150 .rst_lines = omap44xx_dsp_c0_resets, 1151 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets), 1152 .prcm = { 1153 .omap4 = { 1154 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, 1155 }, 1156 }, 1157}; 1158 1159static struct omap_hwmod omap44xx_dsp_hwmod = { 1160 .name = "dsp", 1161 .class = &omap44xx_dsp_hwmod_class, 1162 .clkdm_name = "tesla_clkdm", 1163 .mpu_irqs = omap44xx_dsp_irqs, 1164 .rst_lines = omap44xx_dsp_resets, 1165 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), 1166 .main_clk = "dsp_fck", 1167 .prcm = { 1168 .omap4 = { 1169 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, 1170 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, 1171 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, 1172 .modulemode = MODULEMODE_HWCTRL, 1173 }, 1174 }, 1175 .slaves = omap44xx_dsp_slaves, 1176 .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves), 1177 .masters = omap44xx_dsp_masters, 1178 .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters), 1179}; 1180 1181/* 1182 * 'dss' class 1183 * display sub-system 1184 */ 1185 1186static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = { 1187 .rev_offs = 0x0000, 1188 .syss_offs = 0x0014, 1189 .sysc_flags = SYSS_HAS_RESET_STATUS, 1190}; 1191 1192static struct omap_hwmod_class omap44xx_dss_hwmod_class = { 1193 .name = "dss", 1194 .sysc = &omap44xx_dss_sysc, 1195 .reset = omap_dss_reset, 1196}; 1197 1198/* dss */ 1199/* dss master ports */ 1200static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = { 1201 &omap44xx_dss__l3_main_1, 1202}; 1203 1204static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { 1205 { 1206 .pa_start = 0x58000000, 1207 .pa_end = 0x5800007f, 1208 .flags = ADDR_TYPE_RT 1209 }, 1210 { } 1211}; 1212 1213/* l3_main_2 -> dss */ 1214static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { 1215 .master = &omap44xx_l3_main_2_hwmod, 1216 .slave = &omap44xx_dss_hwmod, 1217 .clk = "dss_fck", 1218 .addr = omap44xx_dss_dma_addrs, 1219 .user = OCP_USER_SDMA, 1220}; 1221 1222static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { 1223 { 1224 .pa_start = 0x48040000, 1225 .pa_end = 0x4804007f, 1226 .flags = ADDR_TYPE_RT 1227 }, 1228 { } 1229}; 1230 1231/* l4_per -> dss */ 1232static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { 1233 .master = &omap44xx_l4_per_hwmod, 1234 .slave = &omap44xx_dss_hwmod, 1235 .clk = "l4_div_ck", 1236 .addr = omap44xx_dss_addrs, 1237 .user = OCP_USER_MPU, 1238}; 1239 1240/* dss slave ports */ 1241static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = { 1242 &omap44xx_l3_main_2__dss, 1243 &omap44xx_l4_per__dss, 1244}; 1245 1246static struct omap_hwmod_opt_clk dss_opt_clks[] = { 1247 { .role = "sys_clk", .clk = "dss_sys_clk" }, 1248 { .role = "tv_clk", .clk = "dss_tv_clk" }, 1249 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, 1250}; 1251 1252static struct omap_hwmod omap44xx_dss_hwmod = { 1253 .name = "dss_core", 1254 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1255 .class = &omap44xx_dss_hwmod_class, 1256 .clkdm_name = "l3_dss_clkdm", 1257 .main_clk = "dss_dss_clk", 1258 .prcm = { 1259 .omap4 = { 1260 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, 1261 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, 1262 }, 1263 }, 1264 .opt_clks = dss_opt_clks, 1265 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 1266 .slaves = omap44xx_dss_slaves, 1267 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves), 1268 .masters = omap44xx_dss_masters, 1269 .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters), 1270}; 1271 1272/* 1273 * 'dispc' class 1274 * display controller 1275 */ 1276 1277static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = { 1278 .rev_offs = 0x0000, 1279 .sysc_offs = 0x0010, 1280 .syss_offs = 0x0014, 1281 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 1282 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE | 1283 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 1284 SYSS_HAS_RESET_STATUS), 1285 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1286 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 1287 .sysc_fields = &omap_hwmod_sysc_type1, 1288}; 1289 1290static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { 1291 .name = "dispc", 1292 .sysc = &omap44xx_dispc_sysc, 1293}; 1294 1295/* dss_dispc */ 1296static struct omap_hwmod omap44xx_dss_dispc_hwmod; 1297static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { 1298 { .irq = 25 + OMAP44XX_IRQ_GIC_START }, 1299 { .irq = -1 } 1300}; 1301 1302static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { 1303 { .dma_req = 5 + OMAP44XX_DMA_REQ_START }, 1304 { .dma_req = -1 } 1305}; 1306 1307static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { 1308 { 1309 .pa_start = 0x58001000, 1310 .pa_end = 0x58001fff, 1311 .flags = ADDR_TYPE_RT 1312 }, 1313 { } 1314}; 1315 1316/* l3_main_2 -> dss_dispc */ 1317static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { 1318 .master = &omap44xx_l3_main_2_hwmod, 1319 .slave = &omap44xx_dss_dispc_hwmod, 1320 .clk = "dss_fck", 1321 .addr = omap44xx_dss_dispc_dma_addrs, 1322 .user = OCP_USER_SDMA, 1323}; 1324 1325static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { 1326 { 1327 .pa_start = 0x48041000, 1328 .pa_end = 0x48041fff, 1329 .flags = ADDR_TYPE_RT 1330 }, 1331 { } 1332}; 1333 1334static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = { 1335 .manager_count = 3, 1336 .has_framedonetv_irq = 1 1337}; 1338 1339/* l4_per -> dss_dispc */ 1340static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { 1341 .master = &omap44xx_l4_per_hwmod, 1342 .slave = &omap44xx_dss_dispc_hwmod, 1343 .clk = "l4_div_ck", 1344 .addr = omap44xx_dss_dispc_addrs, 1345 .user = OCP_USER_MPU, 1346}; 1347 1348/* dss_dispc slave ports */ 1349static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = { 1350 &omap44xx_l3_main_2__dss_dispc, 1351 &omap44xx_l4_per__dss_dispc, 1352}; 1353 1354static struct omap_hwmod omap44xx_dss_dispc_hwmod = { 1355 .name = "dss_dispc", 1356 .class = &omap44xx_dispc_hwmod_class, 1357 .clkdm_name = "l3_dss_clkdm", 1358 .mpu_irqs = omap44xx_dss_dispc_irqs, 1359 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, 1360 .main_clk = "dss_dss_clk", 1361 .prcm = { 1362 .omap4 = { 1363 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, 1364 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, 1365 }, 1366 }, 1367 .slaves = omap44xx_dss_dispc_slaves, 1368 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves), 1369 .dev_attr = &omap44xx_dss_dispc_dev_attr 1370}; 1371 1372/* 1373 * 'dsi' class 1374 * display serial interface controller 1375 */ 1376 1377static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = { 1378 .rev_offs = 0x0000, 1379 .sysc_offs = 0x0010, 1380 .syss_offs = 0x0014, 1381 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 1382 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 1383 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 1384 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1385 .sysc_fields = &omap_hwmod_sysc_type1, 1386}; 1387 1388static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { 1389 .name = "dsi", 1390 .sysc = &omap44xx_dsi_sysc, 1391}; 1392 1393/* dss_dsi1 */ 1394static struct omap_hwmod omap44xx_dss_dsi1_hwmod; 1395static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { 1396 { .irq = 53 + OMAP44XX_IRQ_GIC_START }, 1397 { .irq = -1 } 1398}; 1399 1400static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { 1401 { .dma_req = 74 + OMAP44XX_DMA_REQ_START }, 1402 { .dma_req = -1 } 1403}; 1404 1405static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { 1406 { 1407 .pa_start = 0x58004000, 1408 .pa_end = 0x580041ff, 1409 .flags = ADDR_TYPE_RT 1410 }, 1411 { } 1412}; 1413 1414/* l3_main_2 -> dss_dsi1 */ 1415static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { 1416 .master = &omap44xx_l3_main_2_hwmod, 1417 .slave = &omap44xx_dss_dsi1_hwmod, 1418 .clk = "dss_fck", 1419 .addr = omap44xx_dss_dsi1_dma_addrs, 1420 .user = OCP_USER_SDMA, 1421}; 1422 1423static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { 1424 { 1425 .pa_start = 0x48044000, 1426 .pa_end = 0x480441ff, 1427 .flags = ADDR_TYPE_RT 1428 }, 1429 { } 1430}; 1431 1432/* l4_per -> dss_dsi1 */ 1433static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { 1434 .master = &omap44xx_l4_per_hwmod, 1435 .slave = &omap44xx_dss_dsi1_hwmod, 1436 .clk = "l4_div_ck", 1437 .addr = omap44xx_dss_dsi1_addrs, 1438 .user = OCP_USER_MPU, 1439}; 1440 1441/* dss_dsi1 slave ports */ 1442static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = { 1443 &omap44xx_l3_main_2__dss_dsi1, 1444 &omap44xx_l4_per__dss_dsi1, 1445}; 1446 1447static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { 1448 { .role = "sys_clk", .clk = "dss_sys_clk" }, 1449}; 1450 1451static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { 1452 .name = "dss_dsi1", 1453 .class = &omap44xx_dsi_hwmod_class, 1454 .clkdm_name = "l3_dss_clkdm", 1455 .mpu_irqs = omap44xx_dss_dsi1_irqs, 1456 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, 1457 .main_clk = "dss_dss_clk", 1458 .prcm = { 1459 .omap4 = { 1460 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, 1461 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, 1462 }, 1463 }, 1464 .opt_clks = dss_dsi1_opt_clks, 1465 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), 1466 .slaves = omap44xx_dss_dsi1_slaves, 1467 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves), 1468}; 1469 1470/* dss_dsi2 */ 1471static struct omap_hwmod omap44xx_dss_dsi2_hwmod; 1472static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { 1473 { .irq = 84 + OMAP44XX_IRQ_GIC_START }, 1474 { .irq = -1 } 1475}; 1476 1477static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { 1478 { .dma_req = 83 + OMAP44XX_DMA_REQ_START }, 1479 { .dma_req = -1 } 1480}; 1481 1482static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { 1483 { 1484 .pa_start = 0x58005000, 1485 .pa_end = 0x580051ff, 1486 .flags = ADDR_TYPE_RT 1487 }, 1488 { } 1489}; 1490 1491/* l3_main_2 -> dss_dsi2 */ 1492static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { 1493 .master = &omap44xx_l3_main_2_hwmod, 1494 .slave = &omap44xx_dss_dsi2_hwmod, 1495 .clk = "dss_fck", 1496 .addr = omap44xx_dss_dsi2_dma_addrs, 1497 .user = OCP_USER_SDMA, 1498}; 1499 1500static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { 1501 { 1502 .pa_start = 0x48045000, 1503 .pa_end = 0x480451ff, 1504 .flags = ADDR_TYPE_RT 1505 }, 1506 { } 1507}; 1508 1509/* l4_per -> dss_dsi2 */ 1510static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { 1511 .master = &omap44xx_l4_per_hwmod, 1512 .slave = &omap44xx_dss_dsi2_hwmod, 1513 .clk = "l4_div_ck", 1514 .addr = omap44xx_dss_dsi2_addrs, 1515 .user = OCP_USER_MPU, 1516}; 1517 1518/* dss_dsi2 slave ports */ 1519static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = { 1520 &omap44xx_l3_main_2__dss_dsi2, 1521 &omap44xx_l4_per__dss_dsi2, 1522}; 1523 1524static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { 1525 { .role = "sys_clk", .clk = "dss_sys_clk" }, 1526}; 1527 1528static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { 1529 .name = "dss_dsi2", 1530 .class = &omap44xx_dsi_hwmod_class, 1531 .clkdm_name = "l3_dss_clkdm", 1532 .mpu_irqs = omap44xx_dss_dsi2_irqs, 1533 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, 1534 .main_clk = "dss_dss_clk", 1535 .prcm = { 1536 .omap4 = { 1537 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, 1538 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, 1539 }, 1540 }, 1541 .opt_clks = dss_dsi2_opt_clks, 1542 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), 1543 .slaves = omap44xx_dss_dsi2_slaves, 1544 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves), 1545}; 1546 1547/* 1548 * 'hdmi' class 1549 * hdmi controller 1550 */ 1551 1552static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = { 1553 .rev_offs = 0x0000, 1554 .sysc_offs = 0x0010, 1555 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | 1556 SYSC_HAS_SOFTRESET), 1557 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1558 SIDLE_SMART_WKUP), 1559 .sysc_fields = &omap_hwmod_sysc_type2, 1560}; 1561 1562static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { 1563 .name = "hdmi", 1564 .sysc = &omap44xx_hdmi_sysc, 1565}; 1566 1567/* dss_hdmi */ 1568static struct omap_hwmod omap44xx_dss_hdmi_hwmod; 1569static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { 1570 { .irq = 101 + OMAP44XX_IRQ_GIC_START }, 1571 { .irq = -1 } 1572}; 1573 1574static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { 1575 { .dma_req = 75 + OMAP44XX_DMA_REQ_START }, 1576 { .dma_req = -1 } 1577}; 1578 1579static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { 1580 { 1581 .pa_start = 0x58006000, 1582 .pa_end = 0x58006fff, 1583 .flags = ADDR_TYPE_RT 1584 }, 1585 { } 1586}; 1587 1588/* l3_main_2 -> dss_hdmi */ 1589static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { 1590 .master = &omap44xx_l3_main_2_hwmod, 1591 .slave = &omap44xx_dss_hdmi_hwmod, 1592 .clk = "dss_fck", 1593 .addr = omap44xx_dss_hdmi_dma_addrs, 1594 .user = OCP_USER_SDMA, 1595}; 1596 1597static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { 1598 { 1599 .pa_start = 0x48046000, 1600 .pa_end = 0x48046fff, 1601 .flags = ADDR_TYPE_RT 1602 }, 1603 { } 1604}; 1605 1606/* l4_per -> dss_hdmi */ 1607static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { 1608 .master = &omap44xx_l4_per_hwmod, 1609 .slave = &omap44xx_dss_hdmi_hwmod, 1610 .clk = "l4_div_ck", 1611 .addr = omap44xx_dss_hdmi_addrs, 1612 .user = OCP_USER_MPU, 1613}; 1614 1615/* dss_hdmi slave ports */ 1616static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = { 1617 &omap44xx_l3_main_2__dss_hdmi, 1618 &omap44xx_l4_per__dss_hdmi, 1619}; 1620 1621static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { 1622 { .role = "sys_clk", .clk = "dss_sys_clk" }, 1623}; 1624 1625static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { 1626 .name = "dss_hdmi", 1627 .class = &omap44xx_hdmi_hwmod_class, 1628 .clkdm_name = "l3_dss_clkdm", 1629 .mpu_irqs = omap44xx_dss_hdmi_irqs, 1630 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, 1631 .main_clk = "dss_48mhz_clk", 1632 .prcm = { 1633 .omap4 = { 1634 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, 1635 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, 1636 }, 1637 }, 1638 .opt_clks = dss_hdmi_opt_clks, 1639 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), 1640 .slaves = omap44xx_dss_hdmi_slaves, 1641 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves), 1642}; 1643 1644/* 1645 * 'rfbi' class 1646 * remote frame buffer interface 1647 */ 1648 1649static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = { 1650 .rev_offs = 0x0000, 1651 .sysc_offs = 0x0010, 1652 .syss_offs = 0x0014, 1653 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | 1654 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 1655 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1656 .sysc_fields = &omap_hwmod_sysc_type1, 1657}; 1658 1659static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { 1660 .name = "rfbi", 1661 .sysc = &omap44xx_rfbi_sysc, 1662}; 1663 1664/* dss_rfbi */ 1665static struct omap_hwmod omap44xx_dss_rfbi_hwmod; 1666static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { 1667 { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, 1668 { .dma_req = -1 } 1669}; 1670 1671static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { 1672 { 1673 .pa_start = 0x58002000, 1674 .pa_end = 0x580020ff, 1675 .flags = ADDR_TYPE_RT 1676 }, 1677 { } 1678}; 1679 1680/* l3_main_2 -> dss_rfbi */ 1681static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { 1682 .master = &omap44xx_l3_main_2_hwmod, 1683 .slave = &omap44xx_dss_rfbi_hwmod, 1684 .clk = "dss_fck", 1685 .addr = omap44xx_dss_rfbi_dma_addrs, 1686 .user = OCP_USER_SDMA, 1687}; 1688 1689static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { 1690 { 1691 .pa_start = 0x48042000, 1692 .pa_end = 0x480420ff, 1693 .flags = ADDR_TYPE_RT 1694 }, 1695 { } 1696}; 1697 1698/* l4_per -> dss_rfbi */ 1699static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { 1700 .master = &omap44xx_l4_per_hwmod, 1701 .slave = &omap44xx_dss_rfbi_hwmod, 1702 .clk = "l4_div_ck", 1703 .addr = omap44xx_dss_rfbi_addrs, 1704 .user = OCP_USER_MPU, 1705}; 1706 1707/* dss_rfbi slave ports */ 1708static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = { 1709 &omap44xx_l3_main_2__dss_rfbi, 1710 &omap44xx_l4_per__dss_rfbi, 1711}; 1712 1713static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { 1714 { .role = "ick", .clk = "dss_fck" }, 1715}; 1716 1717static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { 1718 .name = "dss_rfbi", 1719 .class = &omap44xx_rfbi_hwmod_class, 1720 .clkdm_name = "l3_dss_clkdm", 1721 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, 1722 .main_clk = "dss_dss_clk", 1723 .prcm = { 1724 .omap4 = { 1725 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, 1726 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, 1727 }, 1728 }, 1729 .opt_clks = dss_rfbi_opt_clks, 1730 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), 1731 .slaves = omap44xx_dss_rfbi_slaves, 1732 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves), 1733}; 1734 1735/* 1736 * 'venc' class 1737 * video encoder 1738 */ 1739 1740static struct omap_hwmod_class omap44xx_venc_hwmod_class = { 1741 .name = "venc", 1742}; 1743 1744/* dss_venc */ 1745static struct omap_hwmod omap44xx_dss_venc_hwmod; 1746static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { 1747 { 1748 .pa_start = 0x58003000, 1749 .pa_end = 0x580030ff, 1750 .flags = ADDR_TYPE_RT 1751 }, 1752 { } 1753}; 1754 1755/* l3_main_2 -> dss_venc */ 1756static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { 1757 .master = &omap44xx_l3_main_2_hwmod, 1758 .slave = &omap44xx_dss_venc_hwmod, 1759 .clk = "dss_fck", 1760 .addr = omap44xx_dss_venc_dma_addrs, 1761 .user = OCP_USER_SDMA, 1762}; 1763 1764static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { 1765 { 1766 .pa_start = 0x48043000, 1767 .pa_end = 0x480430ff, 1768 .flags = ADDR_TYPE_RT 1769 }, 1770 { } 1771}; 1772 1773/* l4_per -> dss_venc */ 1774static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { 1775 .master = &omap44xx_l4_per_hwmod, 1776 .slave = &omap44xx_dss_venc_hwmod, 1777 .clk = "l4_div_ck", 1778 .addr = omap44xx_dss_venc_addrs, 1779 .user = OCP_USER_MPU, 1780}; 1781 1782/* dss_venc slave ports */ 1783static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = { 1784 &omap44xx_l3_main_2__dss_venc, 1785 &omap44xx_l4_per__dss_venc, 1786}; 1787 1788static struct omap_hwmod omap44xx_dss_venc_hwmod = { 1789 .name = "dss_venc", 1790 .class = &omap44xx_venc_hwmod_class, 1791 .clkdm_name = "l3_dss_clkdm", 1792 .main_clk = "dss_tv_clk", 1793 .prcm = { 1794 .omap4 = { 1795 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, 1796 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, 1797 }, 1798 }, 1799 .slaves = omap44xx_dss_venc_slaves, 1800 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves), 1801}; 1802 1803/* 1804 * 'gpio' class 1805 * general purpose io module 1806 */ 1807 1808static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { 1809 .rev_offs = 0x0000, 1810 .sysc_offs = 0x0010, 1811 .syss_offs = 0x0114, 1812 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | 1813 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 1814 SYSS_HAS_RESET_STATUS), 1815 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1816 SIDLE_SMART_WKUP), 1817 .sysc_fields = &omap_hwmod_sysc_type1, 1818}; 1819 1820static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { 1821 .name = "gpio", 1822 .sysc = &omap44xx_gpio_sysc, 1823 .rev = 2, 1824}; 1825 1826/* gpio dev_attr */ 1827static struct omap_gpio_dev_attr gpio_dev_attr = { 1828 .bank_width = 32, 1829 .dbck_flag = true, 1830}; 1831 1832/* gpio1 */ 1833static struct omap_hwmod omap44xx_gpio1_hwmod; 1834static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { 1835 { .irq = 29 + OMAP44XX_IRQ_GIC_START }, 1836 { .irq = -1 } 1837}; 1838 1839static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { 1840 { 1841 .pa_start = 0x4a310000, 1842 .pa_end = 0x4a3101ff, 1843 .flags = ADDR_TYPE_RT 1844 }, 1845 { } 1846}; 1847 1848/* l4_wkup -> gpio1 */ 1849static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { 1850 .master = &omap44xx_l4_wkup_hwmod, 1851 .slave = &omap44xx_gpio1_hwmod, 1852 .clk = "l4_wkup_clk_mux_ck", 1853 .addr = omap44xx_gpio1_addrs, 1854 .user = OCP_USER_MPU | OCP_USER_SDMA, 1855}; 1856 1857/* gpio1 slave ports */ 1858static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = { 1859 &omap44xx_l4_wkup__gpio1, 1860}; 1861 1862static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { 1863 { .role = "dbclk", .clk = "gpio1_dbclk" }, 1864}; 1865 1866static struct omap_hwmod omap44xx_gpio1_hwmod = { 1867 .name = "gpio1", 1868 .class = &omap44xx_gpio_hwmod_class, 1869 .clkdm_name = "l4_wkup_clkdm", 1870 .mpu_irqs = omap44xx_gpio1_irqs, 1871 .main_clk = "gpio1_ick", 1872 .prcm = { 1873 .omap4 = { 1874 .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET, 1875 .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET, 1876 .modulemode = MODULEMODE_HWCTRL, 1877 }, 1878 }, 1879 .opt_clks = gpio1_opt_clks, 1880 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), 1881 .dev_attr = &gpio_dev_attr, 1882 .slaves = omap44xx_gpio1_slaves, 1883 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves), 1884}; 1885 1886/* gpio2 */ 1887static struct omap_hwmod omap44xx_gpio2_hwmod; 1888static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { 1889 { .irq = 30 + OMAP44XX_IRQ_GIC_START }, 1890 { .irq = -1 } 1891}; 1892 1893static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { 1894 { 1895 .pa_start = 0x48055000, 1896 .pa_end = 0x480551ff, 1897 .flags = ADDR_TYPE_RT 1898 }, 1899 { } 1900}; 1901 1902/* l4_per -> gpio2 */ 1903static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { 1904 .master = &omap44xx_l4_per_hwmod, 1905 .slave = &omap44xx_gpio2_hwmod, 1906 .clk = "l4_div_ck", 1907 .addr = omap44xx_gpio2_addrs, 1908 .user = OCP_USER_MPU | OCP_USER_SDMA, 1909}; 1910 1911/* gpio2 slave ports */ 1912static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = { 1913 &omap44xx_l4_per__gpio2, 1914}; 1915 1916static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { 1917 { .role = "dbclk", .clk = "gpio2_dbclk" }, 1918}; 1919 1920static struct omap_hwmod omap44xx_gpio2_hwmod = { 1921 .name = "gpio2", 1922 .class = &omap44xx_gpio_hwmod_class, 1923 .clkdm_name = "l4_per_clkdm", 1924 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1925 .mpu_irqs = omap44xx_gpio2_irqs, 1926 .main_clk = "gpio2_ick", 1927 .prcm = { 1928 .omap4 = { 1929 .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET, 1930 .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET, 1931 .modulemode = MODULEMODE_HWCTRL, 1932 }, 1933 }, 1934 .opt_clks = gpio2_opt_clks, 1935 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), 1936 .dev_attr = &gpio_dev_attr, 1937 .slaves = omap44xx_gpio2_slaves, 1938 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves), 1939}; 1940 1941/* gpio3 */ 1942static struct omap_hwmod omap44xx_gpio3_hwmod; 1943static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { 1944 { .irq = 31 + OMAP44XX_IRQ_GIC_START }, 1945 { .irq = -1 } 1946}; 1947 1948static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { 1949 { 1950 .pa_start = 0x48057000, 1951 .pa_end = 0x480571ff, 1952 .flags = ADDR_TYPE_RT 1953 }, 1954 { } 1955}; 1956 1957/* l4_per -> gpio3 */ 1958static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { 1959 .master = &omap44xx_l4_per_hwmod, 1960 .slave = &omap44xx_gpio3_hwmod, 1961 .clk = "l4_div_ck", 1962 .addr = omap44xx_gpio3_addrs, 1963 .user = OCP_USER_MPU | OCP_USER_SDMA, 1964}; 1965 1966/* gpio3 slave ports */ 1967static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = { 1968 &omap44xx_l4_per__gpio3, 1969}; 1970 1971static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { 1972 { .role = "dbclk", .clk = "gpio3_dbclk" }, 1973}; 1974 1975static struct omap_hwmod omap44xx_gpio3_hwmod = { 1976 .name = "gpio3", 1977 .class = &omap44xx_gpio_hwmod_class, 1978 .clkdm_name = "l4_per_clkdm", 1979 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1980 .mpu_irqs = omap44xx_gpio3_irqs, 1981 .main_clk = "gpio3_ick", 1982 .prcm = { 1983 .omap4 = { 1984 .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET, 1985 .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET, 1986 .modulemode = MODULEMODE_HWCTRL, 1987 }, 1988 }, 1989 .opt_clks = gpio3_opt_clks, 1990 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), 1991 .dev_attr = &gpio_dev_attr, 1992 .slaves = omap44xx_gpio3_slaves, 1993 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves), 1994}; 1995 1996/* gpio4 */ 1997static struct omap_hwmod omap44xx_gpio4_hwmod; 1998static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { 1999 { .irq = 32 + OMAP44XX_IRQ_GIC_START }, 2000 { .irq = -1 } 2001}; 2002 2003static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { 2004 { 2005 .pa_start = 0x48059000, 2006 .pa_end = 0x480591ff, 2007 .flags = ADDR_TYPE_RT 2008 }, 2009 { } 2010}; 2011 2012/* l4_per -> gpio4 */ 2013static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { 2014 .master = &omap44xx_l4_per_hwmod, 2015 .slave = &omap44xx_gpio4_hwmod, 2016 .clk = "l4_div_ck", 2017 .addr = omap44xx_gpio4_addrs, 2018 .user = OCP_USER_MPU | OCP_USER_SDMA, 2019}; 2020 2021/* gpio4 slave ports */ 2022static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = { 2023 &omap44xx_l4_per__gpio4, 2024}; 2025 2026static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { 2027 { .role = "dbclk", .clk = "gpio4_dbclk" }, 2028}; 2029 2030static struct omap_hwmod omap44xx_gpio4_hwmod = { 2031 .name = "gpio4", 2032 .class = &omap44xx_gpio_hwmod_class, 2033 .clkdm_name = "l4_per_clkdm", 2034 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 2035 .mpu_irqs = omap44xx_gpio4_irqs, 2036 .main_clk = "gpio4_ick", 2037 .prcm = { 2038 .omap4 = { 2039 .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET, 2040 .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET, 2041 .modulemode = MODULEMODE_HWCTRL, 2042 }, 2043 }, 2044 .opt_clks = gpio4_opt_clks, 2045 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), 2046 .dev_attr = &gpio_dev_attr, 2047 .slaves = omap44xx_gpio4_slaves, 2048 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves), 2049}; 2050 2051/* gpio5 */ 2052static struct omap_hwmod omap44xx_gpio5_hwmod; 2053static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { 2054 { .irq = 33 + OMAP44XX_IRQ_GIC_START }, 2055 { .irq = -1 } 2056}; 2057 2058static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { 2059 { 2060 .pa_start = 0x4805b000, 2061 .pa_end = 0x4805b1ff, 2062 .flags = ADDR_TYPE_RT 2063 }, 2064 { } 2065}; 2066 2067/* l4_per -> gpio5 */ 2068static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { 2069 .master = &omap44xx_l4_per_hwmod, 2070 .slave = &omap44xx_gpio5_hwmod, 2071 .clk = "l4_div_ck", 2072 .addr = omap44xx_gpio5_addrs, 2073 .user = OCP_USER_MPU | OCP_USER_SDMA, 2074}; 2075 2076/* gpio5 slave ports */ 2077static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = { 2078 &omap44xx_l4_per__gpio5, 2079}; 2080 2081static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { 2082 { .role = "dbclk", .clk = "gpio5_dbclk" }, 2083}; 2084 2085static struct omap_hwmod omap44xx_gpio5_hwmod = { 2086 .name = "gpio5", 2087 .class = &omap44xx_gpio_hwmod_class, 2088 .clkdm_name = "l4_per_clkdm", 2089 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 2090 .mpu_irqs = omap44xx_gpio5_irqs, 2091 .main_clk = "gpio5_ick", 2092 .prcm = { 2093 .omap4 = { 2094 .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET, 2095 .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET, 2096 .modulemode = MODULEMODE_HWCTRL, 2097 }, 2098 }, 2099 .opt_clks = gpio5_opt_clks, 2100 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), 2101 .dev_attr = &gpio_dev_attr, 2102 .slaves = omap44xx_gpio5_slaves, 2103 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves), 2104}; 2105 2106/* gpio6 */ 2107static struct omap_hwmod omap44xx_gpio6_hwmod; 2108static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { 2109 { .irq = 34 + OMAP44XX_IRQ_GIC_START }, 2110 { .irq = -1 } 2111}; 2112 2113static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { 2114 { 2115 .pa_start = 0x4805d000, 2116 .pa_end = 0x4805d1ff, 2117 .flags = ADDR_TYPE_RT 2118 }, 2119 { } 2120}; 2121 2122/* l4_per -> gpio6 */ 2123static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { 2124 .master = &omap44xx_l4_per_hwmod, 2125 .slave = &omap44xx_gpio6_hwmod, 2126 .clk = "l4_div_ck", 2127 .addr = omap44xx_gpio6_addrs, 2128 .user = OCP_USER_MPU | OCP_USER_SDMA, 2129}; 2130 2131/* gpio6 slave ports */ 2132static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = { 2133 &omap44xx_l4_per__gpio6, 2134}; 2135 2136static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { 2137 { .role = "dbclk", .clk = "gpio6_dbclk" }, 2138}; 2139 2140static struct omap_hwmod omap44xx_gpio6_hwmod = { 2141 .name = "gpio6", 2142 .class = &omap44xx_gpio_hwmod_class, 2143 .clkdm_name = "l4_per_clkdm", 2144 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 2145 .mpu_irqs = omap44xx_gpio6_irqs, 2146 .main_clk = "gpio6_ick", 2147 .prcm = { 2148 .omap4 = { 2149 .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET, 2150 .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET, 2151 .modulemode = MODULEMODE_HWCTRL, 2152 }, 2153 }, 2154 .opt_clks = gpio6_opt_clks, 2155 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), 2156 .dev_attr = &gpio_dev_attr, 2157 .slaves = omap44xx_gpio6_slaves, 2158 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves), 2159}; 2160 2161/* 2162 * 'hsi' class 2163 * mipi high-speed synchronous serial interface (multichannel and full-duplex 2164 * serial if) 2165 */ 2166 2167static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = { 2168 .rev_offs = 0x0000, 2169 .sysc_offs = 0x0010, 2170 .syss_offs = 0x0014, 2171 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE | 2172 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | 2173 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 2174 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 2175 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | 2176 MSTANDBY_SMART | MSTANDBY_SMART_WKUP), 2177 .sysc_fields = &omap_hwmod_sysc_type1, 2178}; 2179 2180static struct omap_hwmod_class omap44xx_hsi_hwmod_class = { 2181 .name = "hsi", 2182 .sysc = &omap44xx_hsi_sysc, 2183}; 2184 2185/* hsi */ 2186static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = { 2187 { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START }, 2188 { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START }, 2189 { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START }, 2190 { .irq = -1 } 2191}; 2192 2193/* hsi master ports */ 2194static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = { 2195 &omap44xx_hsi__l3_main_2, 2196}; 2197 2198static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { 2199 { 2200 .pa_start = 0x4a058000, 2201 .pa_end = 0x4a05bfff, 2202 .flags = ADDR_TYPE_RT 2203 }, 2204 { } 2205}; 2206 2207/* l4_cfg -> hsi */ 2208static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { 2209 .master = &omap44xx_l4_cfg_hwmod, 2210 .slave = &omap44xx_hsi_hwmod, 2211 .clk = "l4_div_ck", 2212 .addr = omap44xx_hsi_addrs, 2213 .user = OCP_USER_MPU | OCP_USER_SDMA, 2214}; 2215 2216/* hsi slave ports */ 2217static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = { 2218 &omap44xx_l4_cfg__hsi, 2219}; 2220 2221static struct omap_hwmod omap44xx_hsi_hwmod = { 2222 .name = "hsi", 2223 .class = &omap44xx_hsi_hwmod_class, 2224 .clkdm_name = "l3_init_clkdm", 2225 .mpu_irqs = omap44xx_hsi_irqs, 2226 .main_clk = "hsi_fck", 2227 .prcm = { 2228 .omap4 = { 2229 .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET, 2230 .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET, 2231 .modulemode = MODULEMODE_HWCTRL, 2232 }, 2233 }, 2234 .slaves = omap44xx_hsi_slaves, 2235 .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves), 2236 .masters = omap44xx_hsi_masters, 2237 .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters), 2238}; 2239 2240/* 2241 * 'i2c' class 2242 * multimaster high-speed i2c controller 2243 */ 2244 2245static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { 2246 .sysc_offs = 0x0010, 2247 .syss_offs = 0x0090, 2248 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 2249 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 2250 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 2251 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 2252 SIDLE_SMART_WKUP), 2253 .clockact = CLOCKACT_TEST_ICLK, 2254 .sysc_fields = &omap_hwmod_sysc_type1, 2255}; 2256 2257static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { 2258 .name = "i2c", 2259 .sysc = &omap44xx_i2c_sysc, 2260 .rev = OMAP_I2C_IP_VERSION_2, 2261 .reset = &omap_i2c_reset, 2262}; 2263 2264static struct omap_i2c_dev_attr i2c_dev_attr = { 2265 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, 2266}; 2267 2268/* i2c1 */ 2269static struct omap_hwmod omap44xx_i2c1_hwmod; 2270static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { 2271 { .irq = 56 + OMAP44XX_IRQ_GIC_START }, 2272 { .irq = -1 } 2273}; 2274 2275static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { 2276 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, 2277 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, 2278 { .dma_req = -1 } 2279}; 2280 2281static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { 2282 { 2283 .pa_start = 0x48070000, 2284 .pa_end = 0x480700ff, 2285 .flags = ADDR_TYPE_RT 2286 }, 2287 { } 2288}; 2289 2290/* l4_per -> i2c1 */ 2291static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { 2292 .master = &omap44xx_l4_per_hwmod, 2293 .slave = &omap44xx_i2c1_hwmod, 2294 .clk = "l4_div_ck", 2295 .addr = omap44xx_i2c1_addrs, 2296 .user = OCP_USER_MPU | OCP_USER_SDMA, 2297}; 2298 2299/* i2c1 slave ports */ 2300static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = { 2301 &omap44xx_l4_per__i2c1, 2302}; 2303 2304static struct omap_hwmod omap44xx_i2c1_hwmod = { 2305 .name = "i2c1", 2306 .class = &omap44xx_i2c_hwmod_class, 2307 .clkdm_name = "l4_per_clkdm", 2308 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 2309 .mpu_irqs = omap44xx_i2c1_irqs, 2310 .sdma_reqs = omap44xx_i2c1_sdma_reqs, 2311 .main_clk = "i2c1_fck", 2312 .prcm = { 2313 .omap4 = { 2314 .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET, 2315 .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET, 2316 .modulemode = MODULEMODE_SWCTRL, 2317 }, 2318 }, 2319 .slaves = omap44xx_i2c1_slaves, 2320 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves), 2321 .dev_attr = &i2c_dev_attr, 2322}; 2323 2324/* i2c2 */ 2325static struct omap_hwmod omap44xx_i2c2_hwmod; 2326static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { 2327 { .irq = 57 + OMAP44XX_IRQ_GIC_START }, 2328 { .irq = -1 } 2329}; 2330 2331static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { 2332 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, 2333 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, 2334 { .dma_req = -1 } 2335}; 2336 2337static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { 2338 { 2339 .pa_start = 0x48072000, 2340 .pa_end = 0x480720ff, 2341 .flags = ADDR_TYPE_RT 2342 }, 2343 { } 2344}; 2345 2346/* l4_per -> i2c2 */ 2347static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { 2348 .master = &omap44xx_l4_per_hwmod, 2349 .slave = &omap44xx_i2c2_hwmod, 2350 .clk = "l4_div_ck", 2351 .addr = omap44xx_i2c2_addrs, 2352 .user = OCP_USER_MPU | OCP_USER_SDMA, 2353}; 2354 2355/* i2c2 slave ports */ 2356static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = { 2357 &omap44xx_l4_per__i2c2, 2358}; 2359 2360static struct omap_hwmod omap44xx_i2c2_hwmod = { 2361 .name = "i2c2", 2362 .class = &omap44xx_i2c_hwmod_class, 2363 .clkdm_name = "l4_per_clkdm", 2364 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 2365 .mpu_irqs = omap44xx_i2c2_irqs, 2366 .sdma_reqs = omap44xx_i2c2_sdma_reqs, 2367 .main_clk = "i2c2_fck", 2368 .prcm = { 2369 .omap4 = { 2370 .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET, 2371 .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET, 2372 .modulemode = MODULEMODE_SWCTRL, 2373 }, 2374 }, 2375 .slaves = omap44xx_i2c2_slaves, 2376 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves), 2377 .dev_attr = &i2c_dev_attr, 2378}; 2379 2380/* i2c3 */ 2381static struct omap_hwmod omap44xx_i2c3_hwmod; 2382static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { 2383 { .irq = 61 + OMAP44XX_IRQ_GIC_START }, 2384 { .irq = -1 } 2385}; 2386 2387static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { 2388 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, 2389 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, 2390 { .dma_req = -1 } 2391}; 2392 2393static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { 2394 { 2395 .pa_start = 0x48060000, 2396 .pa_end = 0x480600ff, 2397 .flags = ADDR_TYPE_RT 2398 }, 2399 { } 2400}; 2401 2402/* l4_per -> i2c3 */ 2403static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { 2404 .master = &omap44xx_l4_per_hwmod, 2405 .slave = &omap44xx_i2c3_hwmod, 2406 .clk = "l4_div_ck", 2407 .addr = omap44xx_i2c3_addrs, 2408 .user = OCP_USER_MPU | OCP_USER_SDMA, 2409}; 2410 2411/* i2c3 slave ports */ 2412static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = { 2413 &omap44xx_l4_per__i2c3, 2414}; 2415 2416static struct omap_hwmod omap44xx_i2c3_hwmod = { 2417 .name = "i2c3", 2418 .class = &omap44xx_i2c_hwmod_class, 2419 .clkdm_name = "l4_per_clkdm", 2420 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 2421 .mpu_irqs = omap44xx_i2c3_irqs, 2422 .sdma_reqs = omap44xx_i2c3_sdma_reqs, 2423 .main_clk = "i2c3_fck", 2424 .prcm = { 2425 .omap4 = { 2426 .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET, 2427 .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET, 2428 .modulemode = MODULEMODE_SWCTRL, 2429 }, 2430 }, 2431 .slaves = omap44xx_i2c3_slaves, 2432 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves), 2433 .dev_attr = &i2c_dev_attr, 2434}; 2435 2436/* i2c4 */ 2437static struct omap_hwmod omap44xx_i2c4_hwmod; 2438static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { 2439 { .irq = 62 + OMAP44XX_IRQ_GIC_START }, 2440 { .irq = -1 } 2441}; 2442 2443static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { 2444 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, 2445 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, 2446 { .dma_req = -1 } 2447}; 2448 2449static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { 2450 { 2451 .pa_start = 0x48350000, 2452 .pa_end = 0x483500ff, 2453 .flags = ADDR_TYPE_RT 2454 }, 2455 { } 2456}; 2457 2458/* l4_per -> i2c4 */ 2459static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { 2460 .master = &omap44xx_l4_per_hwmod, 2461 .slave = &omap44xx_i2c4_hwmod, 2462 .clk = "l4_div_ck", 2463 .addr = omap44xx_i2c4_addrs, 2464 .user = OCP_USER_MPU | OCP_USER_SDMA, 2465}; 2466 2467/* i2c4 slave ports */ 2468static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = { 2469 &omap44xx_l4_per__i2c4, 2470}; 2471 2472static struct omap_hwmod omap44xx_i2c4_hwmod = { 2473 .name = "i2c4", 2474 .class = &omap44xx_i2c_hwmod_class, 2475 .clkdm_name = "l4_per_clkdm", 2476 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 2477 .mpu_irqs = omap44xx_i2c4_irqs, 2478 .sdma_reqs = omap44xx_i2c4_sdma_reqs, 2479 .main_clk = "i2c4_fck", 2480 .prcm = { 2481 .omap4 = { 2482 .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET, 2483 .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET, 2484 .modulemode = MODULEMODE_SWCTRL, 2485 }, 2486 }, 2487 .slaves = omap44xx_i2c4_slaves, 2488 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves), 2489 .dev_attr = &i2c_dev_attr, 2490}; 2491 2492/* 2493 * 'ipu' class 2494 * imaging processor unit 2495 */ 2496 2497static struct omap_hwmod_class omap44xx_ipu_hwmod_class = { 2498 .name = "ipu", 2499}; 2500 2501/* ipu */ 2502static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { 2503 { .irq = 100 + OMAP44XX_IRQ_GIC_START }, 2504 { .irq = -1 } 2505}; 2506 2507static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = { 2508 { .name = "cpu0", .rst_shift = 0 }, 2509}; 2510 2511static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = { 2512 { .name = "cpu1", .rst_shift = 1 }, 2513}; 2514 2515static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { 2516 { .name = "mmu_cache", .rst_shift = 2 }, 2517}; 2518 2519/* ipu master ports */ 2520static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = { 2521 &omap44xx_ipu__l3_main_2, 2522}; 2523 2524/* l3_main_2 -> ipu */ 2525static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { 2526 .master = &omap44xx_l3_main_2_hwmod, 2527 .slave = &omap44xx_ipu_hwmod, 2528 .clk = "l3_div_ck", 2529 .user = OCP_USER_MPU | OCP_USER_SDMA, 2530}; 2531 2532/* ipu slave ports */ 2533static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = { 2534 &omap44xx_l3_main_2__ipu, 2535}; 2536 2537/* Pseudo hwmod for reset control purpose only */ 2538static struct omap_hwmod omap44xx_ipu_c0_hwmod = { 2539 .name = "ipu_c0", 2540 .class = &omap44xx_ipu_hwmod_class, 2541 .clkdm_name = "ducati_clkdm", 2542 .flags = HWMOD_INIT_NO_RESET, 2543 .rst_lines = omap44xx_ipu_c0_resets, 2544 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets), 2545 .prcm = { 2546 .omap4 = { 2547 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, 2548 }, 2549 }, 2550}; 2551 2552/* Pseudo hwmod for reset control purpose only */ 2553static struct omap_hwmod omap44xx_ipu_c1_hwmod = { 2554 .name = "ipu_c1", 2555 .class = &omap44xx_ipu_hwmod_class, 2556 .clkdm_name = "ducati_clkdm", 2557 .flags = HWMOD_INIT_NO_RESET, 2558 .rst_lines = omap44xx_ipu_c1_resets, 2559 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets), 2560 .prcm = { 2561 .omap4 = { 2562 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, 2563 }, 2564 }, 2565}; 2566 2567static struct omap_hwmod omap44xx_ipu_hwmod = { 2568 .name = "ipu", 2569 .class = &omap44xx_ipu_hwmod_class, 2570 .clkdm_name = "ducati_clkdm", 2571 .mpu_irqs = omap44xx_ipu_irqs, 2572 .rst_lines = omap44xx_ipu_resets, 2573 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), 2574 .main_clk = "ipu_fck", 2575 .prcm = { 2576 .omap4 = { 2577 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, 2578 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, 2579 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, 2580 .modulemode = MODULEMODE_HWCTRL, 2581 }, 2582 }, 2583 .slaves = omap44xx_ipu_slaves, 2584 .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves), 2585 .masters = omap44xx_ipu_masters, 2586 .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters), 2587}; 2588 2589/* 2590 * 'iss' class 2591 * external images sensor pixel data processor 2592 */ 2593 2594static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { 2595 .rev_offs = 0x0000, 2596 .sysc_offs = 0x0010, 2597 /* 2598 * ISS needs 100 OCP clk cycles delay after a softreset before 2599 * accessing sysconfig again. 2600 * The lowest frequency at the moment for L3 bus is 100 MHz, so 2601 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). 2602 * 2603 * TODO: Indicate errata when available. 2604 */ 2605 .srst_udelay = 2, 2606 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | 2607 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 2608 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 2609 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | 2610 MSTANDBY_SMART | MSTANDBY_SMART_WKUP), 2611 .sysc_fields = &omap_hwmod_sysc_type2, 2612}; 2613 2614static struct omap_hwmod_class omap44xx_iss_hwmod_class = { 2615 .name = "iss", 2616 .sysc = &omap44xx_iss_sysc, 2617}; 2618 2619/* iss */ 2620static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = { 2621 { .irq = 24 + OMAP44XX_IRQ_GIC_START }, 2622 { .irq = -1 } 2623}; 2624 2625static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { 2626 { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START }, 2627 { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START }, 2628 { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START }, 2629 { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START }, 2630 { .dma_req = -1 } 2631}; 2632 2633/* iss master ports */ 2634static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = { 2635 &omap44xx_iss__l3_main_2, 2636}; 2637 2638static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { 2639 { 2640 .pa_start = 0x52000000, 2641 .pa_end = 0x520000ff, 2642 .flags = ADDR_TYPE_RT 2643 }, 2644 { } 2645}; 2646 2647/* l3_main_2 -> iss */ 2648static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { 2649 .master = &omap44xx_l3_main_2_hwmod, 2650 .slave = &omap44xx_iss_hwmod, 2651 .clk = "l3_div_ck", 2652 .addr = omap44xx_iss_addrs, 2653 .user = OCP_USER_MPU | OCP_USER_SDMA, 2654}; 2655 2656/* iss slave ports */ 2657static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = { 2658 &omap44xx_l3_main_2__iss, 2659}; 2660 2661static struct omap_hwmod_opt_clk iss_opt_clks[] = { 2662 { .role = "ctrlclk", .clk = "iss_ctrlclk" }, 2663}; 2664 2665static struct omap_hwmod omap44xx_iss_hwmod = { 2666 .name = "iss", 2667 .class = &omap44xx_iss_hwmod_class, 2668 .clkdm_name = "iss_clkdm", 2669 .mpu_irqs = omap44xx_iss_irqs, 2670 .sdma_reqs = omap44xx_iss_sdma_reqs, 2671 .main_clk = "iss_fck", 2672 .prcm = { 2673 .omap4 = { 2674 .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET, 2675 .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET, 2676 .modulemode = MODULEMODE_SWCTRL, 2677 }, 2678 }, 2679 .opt_clks = iss_opt_clks, 2680 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), 2681 .slaves = omap44xx_iss_slaves, 2682 .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves), 2683 .masters = omap44xx_iss_masters, 2684 .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters), 2685}; 2686 2687/* 2688 * 'iva' class 2689 * multi-standard video encoder/decoder hardware accelerator 2690 */ 2691 2692static struct omap_hwmod_class omap44xx_iva_hwmod_class = { 2693 .name = "iva", 2694}; 2695 2696/* iva */ 2697static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { 2698 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, 2699 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, 2700 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, 2701 { .irq = -1 } 2702}; 2703 2704static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { 2705 { .name = "logic", .rst_shift = 2 }, 2706}; 2707 2708static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = { 2709 { .name = "seq0", .rst_shift = 0 }, 2710}; 2711 2712static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = { 2713 { .name = "seq1", .rst_shift = 1 }, 2714}; 2715 2716/* iva master ports */ 2717static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = { 2718 &omap44xx_iva__l3_main_2, 2719 &omap44xx_iva__l3_instr, 2720}; 2721 2722static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { 2723 { 2724 .pa_start = 0x5a000000, 2725 .pa_end = 0x5a07ffff, 2726 .flags = ADDR_TYPE_RT 2727 }, 2728 { } 2729}; 2730 2731/* l3_main_2 -> iva */ 2732static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { 2733 .master = &omap44xx_l3_main_2_hwmod, 2734 .slave = &omap44xx_iva_hwmod, 2735 .clk = "l3_div_ck", 2736 .addr = omap44xx_iva_addrs, 2737 .user = OCP_USER_MPU, 2738}; 2739 2740/* iva slave ports */ 2741static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = { 2742 &omap44xx_dsp__iva, 2743 &omap44xx_l3_main_2__iva, 2744}; 2745 2746/* Pseudo hwmod for reset control purpose only */ 2747static struct omap_hwmod omap44xx_iva_seq0_hwmod = { 2748 .name = "iva_seq0", 2749 .class = &omap44xx_iva_hwmod_class, 2750 .clkdm_name = "ivahd_clkdm", 2751 .flags = HWMOD_INIT_NO_RESET, 2752 .rst_lines = omap44xx_iva_seq0_resets, 2753 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets), 2754 .prcm = { 2755 .omap4 = { 2756 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, 2757 }, 2758 }, 2759}; 2760 2761/* Pseudo hwmod for reset control purpose only */ 2762static struct omap_hwmod omap44xx_iva_seq1_hwmod = { 2763 .name = "iva_seq1", 2764 .class = &omap44xx_iva_hwmod_class, 2765 .clkdm_name = "ivahd_clkdm", 2766 .flags = HWMOD_INIT_NO_RESET, 2767 .rst_lines = omap44xx_iva_seq1_resets, 2768 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets), 2769 .prcm = { 2770 .omap4 = { 2771 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, 2772 }, 2773 }, 2774}; 2775 2776static struct omap_hwmod omap44xx_iva_hwmod = { 2777 .name = "iva", 2778 .class = &omap44xx_iva_hwmod_class, 2779 .clkdm_name = "ivahd_clkdm", 2780 .mpu_irqs = omap44xx_iva_irqs, 2781 .rst_lines = omap44xx_iva_resets, 2782 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), 2783 .main_clk = "iva_fck", 2784 .prcm = { 2785 .omap4 = { 2786 .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET, 2787 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, 2788 .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET, 2789 .modulemode = MODULEMODE_HWCTRL, 2790 }, 2791 }, 2792 .slaves = omap44xx_iva_slaves, 2793 .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves), 2794 .masters = omap44xx_iva_masters, 2795 .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters), 2796}; 2797 2798/* 2799 * 'kbd' class 2800 * keyboard controller 2801 */ 2802 2803static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = { 2804 .rev_offs = 0x0000, 2805 .sysc_offs = 0x0010, 2806 .syss_offs = 0x0014, 2807 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 2808 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | 2809 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 2810 SYSS_HAS_RESET_STATUS), 2811 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 2812 .sysc_fields = &omap_hwmod_sysc_type1, 2813}; 2814 2815static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { 2816 .name = "kbd", 2817 .sysc = &omap44xx_kbd_sysc, 2818}; 2819 2820/* kbd */ 2821static struct omap_hwmod omap44xx_kbd_hwmod; 2822static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { 2823 { .irq = 120 + OMAP44XX_IRQ_GIC_START }, 2824 { .irq = -1 } 2825}; 2826 2827static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { 2828 { 2829 .pa_start = 0x4a31c000, 2830 .pa_end = 0x4a31c07f, 2831 .flags = ADDR_TYPE_RT 2832 }, 2833 { } 2834}; 2835 2836/* l4_wkup -> kbd */ 2837static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { 2838 .master = &omap44xx_l4_wkup_hwmod, 2839 .slave = &omap44xx_kbd_hwmod, 2840 .clk = "l4_wkup_clk_mux_ck", 2841 .addr = omap44xx_kbd_addrs, 2842 .user = OCP_USER_MPU | OCP_USER_SDMA, 2843}; 2844 2845/* kbd slave ports */ 2846static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = { 2847 &omap44xx_l4_wkup__kbd, 2848}; 2849 2850static struct omap_hwmod omap44xx_kbd_hwmod = { 2851 .name = "kbd", 2852 .class = &omap44xx_kbd_hwmod_class, 2853 .clkdm_name = "l4_wkup_clkdm", 2854 .mpu_irqs = omap44xx_kbd_irqs, 2855 .main_clk = "kbd_fck", 2856 .prcm = { 2857 .omap4 = { 2858 .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET, 2859 .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET, 2860 .modulemode = MODULEMODE_SWCTRL, 2861 }, 2862 }, 2863 .slaves = omap44xx_kbd_slaves, 2864 .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves), 2865}; 2866 2867/* 2868 * 'mailbox' class 2869 * mailbox module allowing communication between the on-chip processors using a 2870 * queued mailbox-interrupt mechanism. 2871 */ 2872 2873static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = { 2874 .rev_offs = 0x0000, 2875 .sysc_offs = 0x0010, 2876 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | 2877 SYSC_HAS_SOFTRESET), 2878 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 2879 .sysc_fields = &omap_hwmod_sysc_type2, 2880}; 2881 2882static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { 2883 .name = "mailbox", 2884 .sysc = &omap44xx_mailbox_sysc, 2885}; 2886 2887/* mailbox */ 2888static struct omap_hwmod omap44xx_mailbox_hwmod; 2889static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { 2890 { .irq = 26 + OMAP44XX_IRQ_GIC_START }, 2891 { .irq = -1 } 2892}; 2893 2894static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { 2895 { 2896 .pa_start = 0x4a0f4000, 2897 .pa_end = 0x4a0f41ff, 2898 .flags = ADDR_TYPE_RT 2899 }, 2900 { } 2901}; 2902 2903/* l4_cfg -> mailbox */ 2904static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { 2905 .master = &omap44xx_l4_cfg_hwmod, 2906 .slave = &omap44xx_mailbox_hwmod, 2907 .clk = "l4_div_ck", 2908 .addr = omap44xx_mailbox_addrs, 2909 .user = OCP_USER_MPU | OCP_USER_SDMA, 2910}; 2911 2912/* mailbox slave ports */ 2913static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = { 2914 &omap44xx_l4_cfg__mailbox, 2915}; 2916 2917static struct omap_hwmod omap44xx_mailbox_hwmod = { 2918 .name = "mailbox", 2919 .class = &omap44xx_mailbox_hwmod_class, 2920 .clkdm_name = "l4_cfg_clkdm", 2921 .mpu_irqs = omap44xx_mailbox_irqs, 2922 .prcm = { 2923 .omap4 = { 2924 .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET, 2925 .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET, 2926 }, 2927 }, 2928 .slaves = omap44xx_mailbox_slaves, 2929 .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves), 2930}; 2931 2932/* 2933 * 'mcbsp' class 2934 * multi channel buffered serial port controller 2935 */ 2936 2937static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { 2938 .sysc_offs = 0x008c, 2939 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | 2940 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 2941 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 2942 .sysc_fields = &omap_hwmod_sysc_type1, 2943}; 2944 2945static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { 2946 .name = "mcbsp", 2947 .sysc = &omap44xx_mcbsp_sysc, 2948 .rev = MCBSP_CONFIG_TYPE4, 2949}; 2950 2951/* mcbsp1 */ 2952static struct omap_hwmod omap44xx_mcbsp1_hwmod; 2953static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { 2954 { .irq = 17 + OMAP44XX_IRQ_GIC_START }, 2955 { .irq = -1 } 2956}; 2957 2958static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { 2959 { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START }, 2960 { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START }, 2961 { .dma_req = -1 } 2962}; 2963 2964static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { 2965 { 2966 .name = "mpu", 2967 .pa_start = 0x40122000, 2968 .pa_end = 0x401220ff, 2969 .flags = ADDR_TYPE_RT 2970 }, 2971 { } 2972}; 2973 2974/* l4_abe -> mcbsp1 */ 2975static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { 2976 .master = &omap44xx_l4_abe_hwmod, 2977 .slave = &omap44xx_mcbsp1_hwmod, 2978 .clk = "ocp_abe_iclk", 2979 .addr = omap44xx_mcbsp1_addrs, 2980 .user = OCP_USER_MPU, 2981}; 2982 2983static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { 2984 { 2985 .name = "dma", 2986 .pa_start = 0x49022000, 2987 .pa_end = 0x490220ff, 2988 .flags = ADDR_TYPE_RT 2989 }, 2990 { } 2991}; 2992 2993/* l4_abe -> mcbsp1 (dma) */ 2994static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { 2995 .master = &omap44xx_l4_abe_hwmod, 2996 .slave = &omap44xx_mcbsp1_hwmod, 2997 .clk = "ocp_abe_iclk", 2998 .addr = omap44xx_mcbsp1_dma_addrs, 2999 .user = OCP_USER_SDMA, 3000}; 3001 3002/* mcbsp1 slave ports */ 3003static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = { 3004 &omap44xx_l4_abe__mcbsp1, 3005 &omap44xx_l4_abe__mcbsp1_dma, 3006}; 3007 3008static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { 3009 { .role = "pad_fck", .clk = "pad_clks_ck" }, 3010 { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" }, 3011}; 3012 3013static struct omap_hwmod omap44xx_mcbsp1_hwmod = { 3014 .name = "mcbsp1", 3015 .class = &omap44xx_mcbsp_hwmod_class, 3016 .clkdm_name = "abe_clkdm", 3017 .mpu_irqs = omap44xx_mcbsp1_irqs, 3018 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, 3019 .main_clk = "mcbsp1_fck", 3020 .prcm = { 3021 .omap4 = { 3022 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET, 3023 .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET, 3024 .modulemode = MODULEMODE_SWCTRL, 3025 }, 3026 }, 3027 .slaves = omap44xx_mcbsp1_slaves, 3028 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves), 3029 .opt_clks = mcbsp1_opt_clks, 3030 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks), 3031}; 3032 3033/* mcbsp2 */ 3034static struct omap_hwmod omap44xx_mcbsp2_hwmod; 3035static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { 3036 { .irq = 22 + OMAP44XX_IRQ_GIC_START }, 3037 { .irq = -1 } 3038}; 3039 3040static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { 3041 { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START }, 3042 { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START }, 3043 { .dma_req = -1 } 3044}; 3045 3046static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { 3047 { 3048 .name = "mpu", 3049 .pa_start = 0x40124000, 3050 .pa_end = 0x401240ff, 3051 .flags = ADDR_TYPE_RT 3052 }, 3053 { } 3054}; 3055 3056/* l4_abe -> mcbsp2 */ 3057static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { 3058 .master = &omap44xx_l4_abe_hwmod, 3059 .slave = &omap44xx_mcbsp2_hwmod, 3060 .clk = "ocp_abe_iclk", 3061 .addr = omap44xx_mcbsp2_addrs, 3062 .user = OCP_USER_MPU, 3063}; 3064 3065static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { 3066 { 3067 .name = "dma", 3068 .pa_start = 0x49024000, 3069 .pa_end = 0x490240ff, 3070 .flags = ADDR_TYPE_RT 3071 }, 3072 { } 3073}; 3074 3075/* l4_abe -> mcbsp2 (dma) */ 3076static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { 3077 .master = &omap44xx_l4_abe_hwmod, 3078 .slave = &omap44xx_mcbsp2_hwmod, 3079 .clk = "ocp_abe_iclk", 3080 .addr = omap44xx_mcbsp2_dma_addrs, 3081 .user = OCP_USER_SDMA, 3082}; 3083 3084/* mcbsp2 slave ports */ 3085static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = { 3086 &omap44xx_l4_abe__mcbsp2, 3087 &omap44xx_l4_abe__mcbsp2_dma, 3088}; 3089 3090static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { 3091 { .role = "pad_fck", .clk = "pad_clks_ck" }, 3092 { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" }, 3093}; 3094 3095static struct omap_hwmod omap44xx_mcbsp2_hwmod = { 3096 .name = "mcbsp2", 3097 .class = &omap44xx_mcbsp_hwmod_class, 3098 .clkdm_name = "abe_clkdm", 3099 .mpu_irqs = omap44xx_mcbsp2_irqs, 3100 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, 3101 .main_clk = "mcbsp2_fck", 3102 .prcm = { 3103 .omap4 = { 3104 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET, 3105 .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET, 3106 .modulemode = MODULEMODE_SWCTRL, 3107 }, 3108 }, 3109 .slaves = omap44xx_mcbsp2_slaves, 3110 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves), 3111 .opt_clks = mcbsp2_opt_clks, 3112 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks), 3113}; 3114 3115/* mcbsp3 */ 3116static struct omap_hwmod omap44xx_mcbsp3_hwmod; 3117static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { 3118 { .irq = 23 + OMAP44XX_IRQ_GIC_START }, 3119 { .irq = -1 } 3120}; 3121 3122static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { 3123 { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START }, 3124 { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START }, 3125 { .dma_req = -1 } 3126}; 3127 3128static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { 3129 { 3130 .name = "mpu", 3131 .pa_start = 0x40126000, 3132 .pa_end = 0x401260ff, 3133 .flags = ADDR_TYPE_RT 3134 }, 3135 { } 3136}; 3137 3138/* l4_abe -> mcbsp3 */ 3139static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { 3140 .master = &omap44xx_l4_abe_hwmod, 3141 .slave = &omap44xx_mcbsp3_hwmod, 3142 .clk = "ocp_abe_iclk", 3143 .addr = omap44xx_mcbsp3_addrs, 3144 .user = OCP_USER_MPU, 3145}; 3146 3147static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { 3148 { 3149 .name = "dma", 3150 .pa_start = 0x49026000, 3151 .pa_end = 0x490260ff, 3152 .flags = ADDR_TYPE_RT 3153 }, 3154 { } 3155}; 3156 3157/* l4_abe -> mcbsp3 (dma) */ 3158static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { 3159 .master = &omap44xx_l4_abe_hwmod, 3160 .slave = &omap44xx_mcbsp3_hwmod, 3161 .clk = "ocp_abe_iclk", 3162 .addr = omap44xx_mcbsp3_dma_addrs, 3163 .user = OCP_USER_SDMA, 3164}; 3165 3166/* mcbsp3 slave ports */ 3167static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = { 3168 &omap44xx_l4_abe__mcbsp3, 3169 &omap44xx_l4_abe__mcbsp3_dma, 3170}; 3171 3172static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { 3173 { .role = "pad_fck", .clk = "pad_clks_ck" }, 3174 { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" }, 3175}; 3176 3177static struct omap_hwmod omap44xx_mcbsp3_hwmod = { 3178 .name = "mcbsp3", 3179 .class = &omap44xx_mcbsp_hwmod_class, 3180 .clkdm_name = "abe_clkdm", 3181 .mpu_irqs = omap44xx_mcbsp3_irqs, 3182 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, 3183 .main_clk = "mcbsp3_fck", 3184 .prcm = { 3185 .omap4 = { 3186 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET, 3187 .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET, 3188 .modulemode = MODULEMODE_SWCTRL, 3189 }, 3190 }, 3191 .slaves = omap44xx_mcbsp3_slaves, 3192 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves), 3193 .opt_clks = mcbsp3_opt_clks, 3194 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks), 3195}; 3196 3197/* mcbsp4 */ 3198static struct omap_hwmod omap44xx_mcbsp4_hwmod; 3199static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { 3200 { .irq = 16 + OMAP44XX_IRQ_GIC_START }, 3201 { .irq = -1 } 3202}; 3203 3204static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { 3205 { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START }, 3206 { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START }, 3207 { .dma_req = -1 } 3208}; 3209 3210static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { 3211 { 3212 .pa_start = 0x48096000, 3213 .pa_end = 0x480960ff, 3214 .flags = ADDR_TYPE_RT 3215 }, 3216 { } 3217}; 3218 3219/* l4_per -> mcbsp4 */ 3220static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { 3221 .master = &omap44xx_l4_per_hwmod, 3222 .slave = &omap44xx_mcbsp4_hwmod, 3223 .clk = "l4_div_ck", 3224 .addr = omap44xx_mcbsp4_addrs, 3225 .user = OCP_USER_MPU | OCP_USER_SDMA, 3226}; 3227 3228/* mcbsp4 slave ports */ 3229static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = { 3230 &omap44xx_l4_per__mcbsp4, 3231}; 3232 3233static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = { 3234 { .role = "pad_fck", .clk = "pad_clks_ck" }, 3235 { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" }, 3236}; 3237 3238static struct omap_hwmod omap44xx_mcbsp4_hwmod = { 3239 .name = "mcbsp4", 3240 .class = &omap44xx_mcbsp_hwmod_class, 3241 .clkdm_name = "l4_per_clkdm", 3242 .mpu_irqs = omap44xx_mcbsp4_irqs, 3243 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, 3244 .main_clk = "mcbsp4_fck", 3245 .prcm = { 3246 .omap4 = { 3247 .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET, 3248 .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET, 3249 .modulemode = MODULEMODE_SWCTRL, 3250 }, 3251 }, 3252 .slaves = omap44xx_mcbsp4_slaves, 3253 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves), 3254 .opt_clks = mcbsp4_opt_clks, 3255 .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks), 3256}; 3257 3258/* 3259 * 'mcpdm' class 3260 * multi channel pdm controller (proprietary interface with phoenix power 3261 * ic) 3262 */ 3263 3264static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = { 3265 .rev_offs = 0x0000, 3266 .sysc_offs = 0x0010, 3267 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | 3268 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 3269 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 3270 SIDLE_SMART_WKUP), 3271 .sysc_fields = &omap_hwmod_sysc_type2, 3272}; 3273 3274static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { 3275 .name = "mcpdm", 3276 .sysc = &omap44xx_mcpdm_sysc, 3277}; 3278 3279/* mcpdm */ 3280static struct omap_hwmod omap44xx_mcpdm_hwmod; 3281static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { 3282 { .irq = 112 + OMAP44XX_IRQ_GIC_START }, 3283 { .irq = -1 } 3284}; 3285 3286static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { 3287 { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START }, 3288 { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START }, 3289 { .dma_req = -1 } 3290}; 3291 3292static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { 3293 { 3294 .pa_start = 0x40132000, 3295 .pa_end = 0x4013207f, 3296 .flags = ADDR_TYPE_RT 3297 }, 3298 { } 3299}; 3300 3301/* l4_abe -> mcpdm */ 3302static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { 3303 .master = &omap44xx_l4_abe_hwmod, 3304 .slave = &omap44xx_mcpdm_hwmod, 3305 .clk = "ocp_abe_iclk", 3306 .addr = omap44xx_mcpdm_addrs, 3307 .user = OCP_USER_MPU, 3308}; 3309 3310static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { 3311 { 3312 .pa_start = 0x49032000, 3313 .pa_end = 0x4903207f, 3314 .flags = ADDR_TYPE_RT 3315 }, 3316 { } 3317}; 3318 3319/* l4_abe -> mcpdm (dma) */ 3320static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { 3321 .master = &omap44xx_l4_abe_hwmod, 3322 .slave = &omap44xx_mcpdm_hwmod, 3323 .clk = "ocp_abe_iclk", 3324 .addr = omap44xx_mcpdm_dma_addrs, 3325 .user = OCP_USER_SDMA, 3326}; 3327 3328/* mcpdm slave ports */ 3329static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = { 3330 &omap44xx_l4_abe__mcpdm, 3331 &omap44xx_l4_abe__mcpdm_dma, 3332}; 3333 3334static struct omap_hwmod omap44xx_mcpdm_hwmod = { 3335 .name = "mcpdm", 3336 .class = &omap44xx_mcpdm_hwmod_class, 3337 .clkdm_name = "abe_clkdm", 3338 .mpu_irqs = omap44xx_mcpdm_irqs, 3339 .sdma_reqs = omap44xx_mcpdm_sdma_reqs, 3340 .main_clk = "mcpdm_fck", 3341 .prcm = { 3342 .omap4 = { 3343 .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET, 3344 .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET, 3345 .modulemode = MODULEMODE_SWCTRL, 3346 }, 3347 }, 3348 .slaves = omap44xx_mcpdm_slaves, 3349 .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves), 3350}; 3351 3352/* 3353 * 'mcspi' class 3354 * multichannel serial port interface (mcspi) / master/slave synchronous serial 3355 * bus 3356 */ 3357 3358static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = { 3359 .rev_offs = 0x0000, 3360 .sysc_offs = 0x0010, 3361 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | 3362 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 3363 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 3364 SIDLE_SMART_WKUP), 3365 .sysc_fields = &omap_hwmod_sysc_type2, 3366}; 3367 3368static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { 3369 .name = "mcspi", 3370 .sysc = &omap44xx_mcspi_sysc, 3371 .rev = OMAP4_MCSPI_REV, 3372}; 3373 3374/* mcspi1 */ 3375static struct omap_hwmod omap44xx_mcspi1_hwmod; 3376static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { 3377 { .irq = 65 + OMAP44XX_IRQ_GIC_START }, 3378 { .irq = -1 } 3379}; 3380 3381static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { 3382 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START }, 3383 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START }, 3384 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START }, 3385 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START }, 3386 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START }, 3387 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START }, 3388 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START }, 3389 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START }, 3390 { .dma_req = -1 } 3391}; 3392 3393static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { 3394 { 3395 .pa_start = 0x48098000, 3396 .pa_end = 0x480981ff, 3397 .flags = ADDR_TYPE_RT 3398 }, 3399 { } 3400}; 3401 3402/* l4_per -> mcspi1 */ 3403static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { 3404 .master = &omap44xx_l4_per_hwmod, 3405 .slave = &omap44xx_mcspi1_hwmod, 3406 .clk = "l4_div_ck", 3407 .addr = omap44xx_mcspi1_addrs, 3408 .user = OCP_USER_MPU | OCP_USER_SDMA, 3409}; 3410 3411/* mcspi1 slave ports */ 3412static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = { 3413 &omap44xx_l4_per__mcspi1, 3414}; 3415 3416/* mcspi1 dev_attr */ 3417static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { 3418 .num_chipselect = 4, 3419}; 3420 3421static struct omap_hwmod omap44xx_mcspi1_hwmod = { 3422 .name = "mcspi1", 3423 .class = &omap44xx_mcspi_hwmod_class, 3424 .clkdm_name = "l4_per_clkdm", 3425 .mpu_irqs = omap44xx_mcspi1_irqs, 3426 .sdma_reqs = omap44xx_mcspi1_sdma_reqs, 3427 .main_clk = "mcspi1_fck", 3428 .prcm = { 3429 .omap4 = { 3430 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, 3431 .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET, 3432 .modulemode = MODULEMODE_SWCTRL, 3433 }, 3434 }, 3435 .dev_attr = &mcspi1_dev_attr, 3436 .slaves = omap44xx_mcspi1_slaves, 3437 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves), 3438}; 3439 3440/* mcspi2 */ 3441static struct omap_hwmod omap44xx_mcspi2_hwmod; 3442static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { 3443 { .irq = 66 + OMAP44XX_IRQ_GIC_START }, 3444 { .irq = -1 } 3445}; 3446 3447static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { 3448 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START }, 3449 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, 3450 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START }, 3451 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START }, 3452 { .dma_req = -1 } 3453}; 3454 3455static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { 3456 { 3457 .pa_start = 0x4809a000, 3458 .pa_end = 0x4809a1ff, 3459 .flags = ADDR_TYPE_RT 3460 }, 3461 { } 3462}; 3463 3464/* l4_per -> mcspi2 */ 3465static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { 3466 .master = &omap44xx_l4_per_hwmod, 3467 .slave = &omap44xx_mcspi2_hwmod, 3468 .clk = "l4_div_ck", 3469 .addr = omap44xx_mcspi2_addrs, 3470 .user = OCP_USER_MPU | OCP_USER_SDMA, 3471}; 3472 3473/* mcspi2 slave ports */ 3474static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = { 3475 &omap44xx_l4_per__mcspi2, 3476}; 3477 3478/* mcspi2 dev_attr */ 3479static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { 3480 .num_chipselect = 2, 3481}; 3482 3483static struct omap_hwmod omap44xx_mcspi2_hwmod = { 3484 .name = "mcspi2", 3485 .class = &omap44xx_mcspi_hwmod_class, 3486 .clkdm_name = "l4_per_clkdm", 3487 .mpu_irqs = omap44xx_mcspi2_irqs, 3488 .sdma_reqs = omap44xx_mcspi2_sdma_reqs, 3489 .main_clk = "mcspi2_fck", 3490 .prcm = { 3491 .omap4 = { 3492 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, 3493 .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET, 3494 .modulemode = MODULEMODE_SWCTRL, 3495 }, 3496 }, 3497 .dev_attr = &mcspi2_dev_attr, 3498 .slaves = omap44xx_mcspi2_slaves, 3499 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves), 3500}; 3501 3502/* mcspi3 */ 3503static struct omap_hwmod omap44xx_mcspi3_hwmod; 3504static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { 3505 { .irq = 91 + OMAP44XX_IRQ_GIC_START }, 3506 { .irq = -1 } 3507}; 3508 3509static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { 3510 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START }, 3511 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, 3512 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START }, 3513 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START }, 3514 { .dma_req = -1 } 3515}; 3516 3517static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { 3518 { 3519 .pa_start = 0x480b8000, 3520 .pa_end = 0x480b81ff, 3521 .flags = ADDR_TYPE_RT 3522 }, 3523 { } 3524}; 3525 3526/* l4_per -> mcspi3 */ 3527static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { 3528 .master = &omap44xx_l4_per_hwmod, 3529 .slave = &omap44xx_mcspi3_hwmod, 3530 .clk = "l4_div_ck", 3531 .addr = omap44xx_mcspi3_addrs, 3532 .user = OCP_USER_MPU | OCP_USER_SDMA, 3533}; 3534 3535/* mcspi3 slave ports */ 3536static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = { 3537 &omap44xx_l4_per__mcspi3, 3538}; 3539 3540/* mcspi3 dev_attr */ 3541static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { 3542 .num_chipselect = 2, 3543}; 3544 3545static struct omap_hwmod omap44xx_mcspi3_hwmod = { 3546 .name = "mcspi3", 3547 .class = &omap44xx_mcspi_hwmod_class, 3548 .clkdm_name = "l4_per_clkdm", 3549 .mpu_irqs = omap44xx_mcspi3_irqs, 3550 .sdma_reqs = omap44xx_mcspi3_sdma_reqs, 3551 .main_clk = "mcspi3_fck", 3552 .prcm = { 3553 .omap4 = { 3554 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, 3555 .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET, 3556 .modulemode = MODULEMODE_SWCTRL, 3557 }, 3558 }, 3559 .dev_attr = &mcspi3_dev_attr, 3560 .slaves = omap44xx_mcspi3_slaves, 3561 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves), 3562}; 3563 3564/* mcspi4 */ 3565static struct omap_hwmod omap44xx_mcspi4_hwmod; 3566static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { 3567 { .irq = 48 + OMAP44XX_IRQ_GIC_START }, 3568 { .irq = -1 } 3569}; 3570 3571static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { 3572 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, 3573 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, 3574 { .dma_req = -1 } 3575}; 3576 3577static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { 3578 { 3579 .pa_start = 0x480ba000, 3580 .pa_end = 0x480ba1ff, 3581 .flags = ADDR_TYPE_RT 3582 }, 3583 { } 3584}; 3585 3586/* l4_per -> mcspi4 */ 3587static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { 3588 .master = &omap44xx_l4_per_hwmod, 3589 .slave = &omap44xx_mcspi4_hwmod, 3590 .clk = "l4_div_ck", 3591 .addr = omap44xx_mcspi4_addrs, 3592 .user = OCP_USER_MPU | OCP_USER_SDMA, 3593}; 3594 3595/* mcspi4 slave ports */ 3596static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = { 3597 &omap44xx_l4_per__mcspi4, 3598}; 3599 3600/* mcspi4 dev_attr */ 3601static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { 3602 .num_chipselect = 1, 3603}; 3604 3605static struct omap_hwmod omap44xx_mcspi4_hwmod = { 3606 .name = "mcspi4", 3607 .class = &omap44xx_mcspi_hwmod_class, 3608 .clkdm_name = "l4_per_clkdm", 3609 .mpu_irqs = omap44xx_mcspi4_irqs, 3610 .sdma_reqs = omap44xx_mcspi4_sdma_reqs, 3611 .main_clk = "mcspi4_fck", 3612 .prcm = { 3613 .omap4 = { 3614 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, 3615 .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET, 3616 .modulemode = MODULEMODE_SWCTRL, 3617 }, 3618 }, 3619 .dev_attr = &mcspi4_dev_attr, 3620 .slaves = omap44xx_mcspi4_slaves, 3621 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves), 3622}; 3623 3624/* 3625 * 'mmc' class 3626 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller 3627 */ 3628 3629static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = { 3630 .rev_offs = 0x0000, 3631 .sysc_offs = 0x0010, 3632 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | 3633 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | 3634 SYSC_HAS_SOFTRESET), 3635 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 3636 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | 3637 MSTANDBY_SMART | MSTANDBY_SMART_WKUP), 3638 .sysc_fields = &omap_hwmod_sysc_type2, 3639}; 3640 3641static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { 3642 .name = "mmc", 3643 .sysc = &omap44xx_mmc_sysc, 3644}; 3645 3646/* mmc1 */ 3647static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { 3648 { .irq = 83 + OMAP44XX_IRQ_GIC_START }, 3649 { .irq = -1 } 3650}; 3651 3652static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { 3653 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, 3654 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, 3655 { .dma_req = -1 } 3656}; 3657 3658/* mmc1 master ports */ 3659static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = { 3660 &omap44xx_mmc1__l3_main_1, 3661}; 3662 3663static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { 3664 { 3665 .pa_start = 0x4809c000, 3666 .pa_end = 0x4809c3ff, 3667 .flags = ADDR_TYPE_RT 3668 }, 3669 { } 3670}; 3671 3672/* l4_per -> mmc1 */ 3673static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { 3674 .master = &omap44xx_l4_per_hwmod, 3675 .slave = &omap44xx_mmc1_hwmod, 3676 .clk = "l4_div_ck", 3677 .addr = omap44xx_mmc1_addrs, 3678 .user = OCP_USER_MPU | OCP_USER_SDMA, 3679}; 3680 3681/* mmc1 slave ports */ 3682static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = { 3683 &omap44xx_l4_per__mmc1, 3684}; 3685 3686/* mmc1 dev_attr */ 3687static struct omap_mmc_dev_attr mmc1_dev_attr = { 3688 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 3689}; 3690 3691static struct omap_hwmod omap44xx_mmc1_hwmod = { 3692 .name = "mmc1", 3693 .class = &omap44xx_mmc_hwmod_class, 3694 .clkdm_name = "l3_init_clkdm", 3695 .mpu_irqs = omap44xx_mmc1_irqs, 3696 .sdma_reqs = omap44xx_mmc1_sdma_reqs, 3697 .main_clk = "mmc1_fck", 3698 .prcm = { 3699 .omap4 = { 3700 .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET, 3701 .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET, 3702 .modulemode = MODULEMODE_SWCTRL, 3703 }, 3704 }, 3705 .dev_attr = &mmc1_dev_attr, 3706 .slaves = omap44xx_mmc1_slaves, 3707 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves), 3708 .masters = omap44xx_mmc1_masters, 3709 .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters), 3710}; 3711 3712/* mmc2 */ 3713static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = { 3714 { .irq = 86 + OMAP44XX_IRQ_GIC_START }, 3715 { .irq = -1 } 3716}; 3717 3718static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { 3719 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, 3720 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, 3721 { .dma_req = -1 } 3722}; 3723 3724/* mmc2 master ports */ 3725static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = { 3726 &omap44xx_mmc2__l3_main_1, 3727}; 3728 3729static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { 3730 { 3731 .pa_start = 0x480b4000, 3732 .pa_end = 0x480b43ff, 3733 .flags = ADDR_TYPE_RT 3734 }, 3735 { } 3736}; 3737 3738/* l4_per -> mmc2 */ 3739static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { 3740 .master = &omap44xx_l4_per_hwmod, 3741 .slave = &omap44xx_mmc2_hwmod, 3742 .clk = "l4_div_ck", 3743 .addr = omap44xx_mmc2_addrs, 3744 .user = OCP_USER_MPU | OCP_USER_SDMA, 3745}; 3746 3747/* mmc2 slave ports */ 3748static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = { 3749 &omap44xx_l4_per__mmc2, 3750}; 3751 3752static struct omap_hwmod omap44xx_mmc2_hwmod = { 3753 .name = "mmc2", 3754 .class = &omap44xx_mmc_hwmod_class, 3755 .clkdm_name = "l3_init_clkdm", 3756 .mpu_irqs = omap44xx_mmc2_irqs, 3757 .sdma_reqs = omap44xx_mmc2_sdma_reqs, 3758 .main_clk = "mmc2_fck", 3759 .prcm = { 3760 .omap4 = { 3761 .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET, 3762 .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET, 3763 .modulemode = MODULEMODE_SWCTRL, 3764 }, 3765 }, 3766 .slaves = omap44xx_mmc2_slaves, 3767 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves), 3768 .masters = omap44xx_mmc2_masters, 3769 .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters), 3770}; 3771 3772/* mmc3 */ 3773static struct omap_hwmod omap44xx_mmc3_hwmod; 3774static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { 3775 { .irq = 94 + OMAP44XX_IRQ_GIC_START }, 3776 { .irq = -1 } 3777}; 3778 3779static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { 3780 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, 3781 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, 3782 { .dma_req = -1 } 3783}; 3784 3785static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { 3786 { 3787 .pa_start = 0x480ad000, 3788 .pa_end = 0x480ad3ff, 3789 .flags = ADDR_TYPE_RT 3790 }, 3791 { } 3792}; 3793 3794/* l4_per -> mmc3 */ 3795static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { 3796 .master = &omap44xx_l4_per_hwmod, 3797 .slave = &omap44xx_mmc3_hwmod, 3798 .clk = "l4_div_ck", 3799 .addr = omap44xx_mmc3_addrs, 3800 .user = OCP_USER_MPU | OCP_USER_SDMA, 3801}; 3802 3803/* mmc3 slave ports */ 3804static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = { 3805 &omap44xx_l4_per__mmc3, 3806}; 3807 3808static struct omap_hwmod omap44xx_mmc3_hwmod = { 3809 .name = "mmc3", 3810 .class = &omap44xx_mmc_hwmod_class, 3811 .clkdm_name = "l4_per_clkdm", 3812 .mpu_irqs = omap44xx_mmc3_irqs, 3813 .sdma_reqs = omap44xx_mmc3_sdma_reqs, 3814 .main_clk = "mmc3_fck", 3815 .prcm = { 3816 .omap4 = { 3817 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET, 3818 .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET, 3819 .modulemode = MODULEMODE_SWCTRL, 3820 }, 3821 }, 3822 .slaves = omap44xx_mmc3_slaves, 3823 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves), 3824}; 3825 3826/* mmc4 */ 3827static struct omap_hwmod omap44xx_mmc4_hwmod; 3828static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { 3829 { .irq = 96 + OMAP44XX_IRQ_GIC_START }, 3830 { .irq = -1 } 3831}; 3832 3833static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { 3834 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, 3835 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, 3836 { .dma_req = -1 } 3837}; 3838 3839static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { 3840 { 3841 .pa_start = 0x480d1000, 3842 .pa_end = 0x480d13ff, 3843 .flags = ADDR_TYPE_RT 3844 }, 3845 { } 3846}; 3847 3848/* l4_per -> mmc4 */ 3849static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { 3850 .master = &omap44xx_l4_per_hwmod, 3851 .slave = &omap44xx_mmc4_hwmod, 3852 .clk = "l4_div_ck", 3853 .addr = omap44xx_mmc4_addrs, 3854 .user = OCP_USER_MPU | OCP_USER_SDMA, 3855}; 3856 3857/* mmc4 slave ports */ 3858static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = { 3859 &omap44xx_l4_per__mmc4, 3860}; 3861 3862static struct omap_hwmod omap44xx_mmc4_hwmod = { 3863 .name = "mmc4", 3864 .class = &omap44xx_mmc_hwmod_class, 3865 .clkdm_name = "l4_per_clkdm", 3866 .mpu_irqs = omap44xx_mmc4_irqs, 3867 3868 .sdma_reqs = omap44xx_mmc4_sdma_reqs, 3869 .main_clk = "mmc4_fck", 3870 .prcm = { 3871 .omap4 = { 3872 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET, 3873 .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET, 3874 .modulemode = MODULEMODE_SWCTRL, 3875 }, 3876 }, 3877 .slaves = omap44xx_mmc4_slaves, 3878 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves), 3879}; 3880 3881/* mmc5 */ 3882static struct omap_hwmod omap44xx_mmc5_hwmod; 3883static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { 3884 { .irq = 59 + OMAP44XX_IRQ_GIC_START }, 3885 { .irq = -1 } 3886}; 3887 3888static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { 3889 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, 3890 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, 3891 { .dma_req = -1 } 3892}; 3893 3894static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { 3895 { 3896 .pa_start = 0x480d5000, 3897 .pa_end = 0x480d53ff, 3898 .flags = ADDR_TYPE_RT 3899 }, 3900 { } 3901}; 3902 3903/* l4_per -> mmc5 */ 3904static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { 3905 .master = &omap44xx_l4_per_hwmod, 3906 .slave = &omap44xx_mmc5_hwmod, 3907 .clk = "l4_div_ck", 3908 .addr = omap44xx_mmc5_addrs, 3909 .user = OCP_USER_MPU | OCP_USER_SDMA, 3910}; 3911 3912/* mmc5 slave ports */ 3913static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = { 3914 &omap44xx_l4_per__mmc5, 3915}; 3916 3917static struct omap_hwmod omap44xx_mmc5_hwmod = { 3918 .name = "mmc5", 3919 .class = &omap44xx_mmc_hwmod_class, 3920 .clkdm_name = "l4_per_clkdm", 3921 .mpu_irqs = omap44xx_mmc5_irqs, 3922 .sdma_reqs = omap44xx_mmc5_sdma_reqs, 3923 .main_clk = "mmc5_fck", 3924 .prcm = { 3925 .omap4 = { 3926 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET, 3927 .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET, 3928 .modulemode = MODULEMODE_SWCTRL, 3929 }, 3930 }, 3931 .slaves = omap44xx_mmc5_slaves, 3932 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves), 3933}; 3934 3935/* 3936 * 'mpu' class 3937 * mpu sub-system 3938 */ 3939 3940static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { 3941 .name = "mpu", 3942}; 3943 3944/* mpu */ 3945static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { 3946 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, 3947 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, 3948 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, 3949 { .irq = -1 } 3950}; 3951 3952/* mpu master ports */ 3953static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = { 3954 &omap44xx_mpu__l3_main_1, 3955 &omap44xx_mpu__l4_abe, 3956 &omap44xx_mpu__dmm, 3957}; 3958 3959static struct omap_hwmod omap44xx_mpu_hwmod = { 3960 .name = "mpu", 3961 .class = &omap44xx_mpu_hwmod_class, 3962 .clkdm_name = "mpuss_clkdm", 3963 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, 3964 .mpu_irqs = omap44xx_mpu_irqs, 3965 .main_clk = "dpll_mpu_m2_ck", 3966 .prcm = { 3967 .omap4 = { 3968 .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET, 3969 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET, 3970 }, 3971 }, 3972 .masters = omap44xx_mpu_masters, 3973 .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters), 3974}; 3975 3976/* 3977 * 'smartreflex' class 3978 * smartreflex module (monitor silicon performance and outputs a measure of 3979 * performance error) 3980 */ 3981 3982/* The IP is not compliant to type1 / type2 scheme */ 3983static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { 3984 .sidle_shift = 24, 3985 .enwkup_shift = 26, 3986}; 3987 3988static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { 3989 .sysc_offs = 0x0038, 3990 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), 3991 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 3992 SIDLE_SMART_WKUP), 3993 .sysc_fields = &omap_hwmod_sysc_type_smartreflex, 3994}; 3995 3996static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { 3997 .name = "smartreflex", 3998 .sysc = &omap44xx_smartreflex_sysc, 3999 .rev = 2, 4000}; 4001 4002/* smartreflex_core */ 4003static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { 4004 .sensor_voltdm_name = "core", 4005}; 4006 4007static struct omap_hwmod omap44xx_smartreflex_core_hwmod; 4008static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { 4009 { .irq = 19 + OMAP44XX_IRQ_GIC_START }, 4010 { .irq = -1 } 4011}; 4012 4013static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { 4014 { 4015 .pa_start = 0x4a0dd000, 4016 .pa_end = 0x4a0dd03f, 4017 .flags = ADDR_TYPE_RT 4018 }, 4019 { } 4020}; 4021 4022/* l4_cfg -> smartreflex_core */ 4023static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { 4024 .master = &omap44xx_l4_cfg_hwmod, 4025 .slave = &omap44xx_smartreflex_core_hwmod, 4026 .clk = "l4_div_ck", 4027 .addr = omap44xx_smartreflex_core_addrs, 4028 .user = OCP_USER_MPU | OCP_USER_SDMA, 4029}; 4030 4031/* smartreflex_core slave ports */ 4032static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = { 4033 &omap44xx_l4_cfg__smartreflex_core, 4034}; 4035 4036static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { 4037 .name = "smartreflex_core", 4038 .class = &omap44xx_smartreflex_hwmod_class, 4039 .clkdm_name = "l4_ao_clkdm", 4040 .mpu_irqs = omap44xx_smartreflex_core_irqs, 4041 4042 .main_clk = "smartreflex_core_fck", 4043 .prcm = { 4044 .omap4 = { 4045 .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET, 4046 .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET, 4047 .modulemode = MODULEMODE_SWCTRL, 4048 }, 4049 }, 4050 .slaves = omap44xx_smartreflex_core_slaves, 4051 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves), 4052 .dev_attr = &smartreflex_core_dev_attr, 4053}; 4054 4055/* smartreflex_iva */ 4056static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = { 4057 .sensor_voltdm_name = "iva", 4058}; 4059 4060static struct omap_hwmod omap44xx_smartreflex_iva_hwmod; 4061static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { 4062 { .irq = 102 + OMAP44XX_IRQ_GIC_START }, 4063 { .irq = -1 } 4064}; 4065 4066static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { 4067 { 4068 .pa_start = 0x4a0db000, 4069 .pa_end = 0x4a0db03f, 4070 .flags = ADDR_TYPE_RT 4071 }, 4072 { } 4073}; 4074 4075/* l4_cfg -> smartreflex_iva */ 4076static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { 4077 .master = &omap44xx_l4_cfg_hwmod, 4078 .slave = &omap44xx_smartreflex_iva_hwmod, 4079 .clk = "l4_div_ck", 4080 .addr = omap44xx_smartreflex_iva_addrs, 4081 .user = OCP_USER_MPU | OCP_USER_SDMA, 4082}; 4083 4084/* smartreflex_iva slave ports */ 4085static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = { 4086 &omap44xx_l4_cfg__smartreflex_iva, 4087}; 4088 4089static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { 4090 .name = "smartreflex_iva", 4091 .class = &omap44xx_smartreflex_hwmod_class, 4092 .clkdm_name = "l4_ao_clkdm", 4093 .mpu_irqs = omap44xx_smartreflex_iva_irqs, 4094 .main_clk = "smartreflex_iva_fck", 4095 .prcm = { 4096 .omap4 = { 4097 .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET, 4098 .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET, 4099 .modulemode = MODULEMODE_SWCTRL, 4100 }, 4101 }, 4102 .slaves = omap44xx_smartreflex_iva_slaves, 4103 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves), 4104 .dev_attr = &smartreflex_iva_dev_attr, 4105}; 4106 4107/* smartreflex_mpu */ 4108static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { 4109 .sensor_voltdm_name = "mpu", 4110}; 4111 4112static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod; 4113static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { 4114 { .irq = 18 + OMAP44XX_IRQ_GIC_START }, 4115 { .irq = -1 } 4116}; 4117 4118static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { 4119 { 4120 .pa_start = 0x4a0d9000, 4121 .pa_end = 0x4a0d903f, 4122 .flags = ADDR_TYPE_RT 4123 }, 4124 { } 4125}; 4126 4127/* l4_cfg -> smartreflex_mpu */ 4128static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { 4129 .master = &omap44xx_l4_cfg_hwmod, 4130 .slave = &omap44xx_smartreflex_mpu_hwmod, 4131 .clk = "l4_div_ck", 4132 .addr = omap44xx_smartreflex_mpu_addrs, 4133 .user = OCP_USER_MPU | OCP_USER_SDMA, 4134}; 4135 4136/* smartreflex_mpu slave ports */ 4137static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = { 4138 &omap44xx_l4_cfg__smartreflex_mpu, 4139}; 4140 4141static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { 4142 .name = "smartreflex_mpu", 4143 .class = &omap44xx_smartreflex_hwmod_class, 4144 .clkdm_name = "l4_ao_clkdm", 4145 .mpu_irqs = omap44xx_smartreflex_mpu_irqs, 4146 .main_clk = "smartreflex_mpu_fck", 4147 .prcm = { 4148 .omap4 = { 4149 .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET, 4150 .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET, 4151 .modulemode = MODULEMODE_SWCTRL, 4152 }, 4153 }, 4154 .slaves = omap44xx_smartreflex_mpu_slaves, 4155 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves), 4156 .dev_attr = &smartreflex_mpu_dev_attr, 4157}; 4158 4159/* 4160 * 'spinlock' class 4161 * spinlock provides hardware assistance for synchronizing the processes 4162 * running on multiple processors 4163 */ 4164 4165static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = { 4166 .rev_offs = 0x0000, 4167 .sysc_offs = 0x0010, 4168 .syss_offs = 0x0014, 4169 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 4170 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 4171 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 4172 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 4173 SIDLE_SMART_WKUP), 4174 .sysc_fields = &omap_hwmod_sysc_type1, 4175}; 4176 4177static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = { 4178 .name = "spinlock", 4179 .sysc = &omap44xx_spinlock_sysc, 4180}; 4181 4182/* spinlock */ 4183static struct omap_hwmod omap44xx_spinlock_hwmod; 4184static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { 4185 { 4186 .pa_start = 0x4a0f6000, 4187 .pa_end = 0x4a0f6fff, 4188 .flags = ADDR_TYPE_RT 4189 }, 4190 { } 4191}; 4192 4193/* l4_cfg -> spinlock */ 4194static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { 4195 .master = &omap44xx_l4_cfg_hwmod, 4196 .slave = &omap44xx_spinlock_hwmod, 4197 .clk = "l4_div_ck", 4198 .addr = omap44xx_spinlock_addrs, 4199 .user = OCP_USER_MPU | OCP_USER_SDMA, 4200}; 4201 4202/* spinlock slave ports */ 4203static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = { 4204 &omap44xx_l4_cfg__spinlock, 4205}; 4206 4207static struct omap_hwmod omap44xx_spinlock_hwmod = { 4208 .name = "spinlock", 4209 .class = &omap44xx_spinlock_hwmod_class, 4210 .clkdm_name = "l4_cfg_clkdm", 4211 .prcm = { 4212 .omap4 = { 4213 .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET, 4214 .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET, 4215 }, 4216 }, 4217 .slaves = omap44xx_spinlock_slaves, 4218 .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves), 4219}; 4220 4221/* 4222 * 'timer' class 4223 * general purpose timer module with accurate 1ms tick 4224 * This class contains several variants: ['timer_1ms', 'timer'] 4225 */ 4226 4227static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = { 4228 .rev_offs = 0x0000, 4229 .sysc_offs = 0x0010, 4230 .syss_offs = 0x0014, 4231 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 4232 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | 4233 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 4234 SYSS_HAS_RESET_STATUS), 4235 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 4236 .sysc_fields = &omap_hwmod_sysc_type1, 4237}; 4238 4239static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = { 4240 .name = "timer", 4241 .sysc = &omap44xx_timer_1ms_sysc, 4242}; 4243 4244static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = { 4245 .rev_offs = 0x0000, 4246 .sysc_offs = 0x0010, 4247 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | 4248 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 4249 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 4250 SIDLE_SMART_WKUP), 4251 .sysc_fields = &omap_hwmod_sysc_type2, 4252}; 4253 4254static struct omap_hwmod_class omap44xx_timer_hwmod_class = { 4255 .name = "timer", 4256 .sysc = &omap44xx_timer_sysc, 4257}; 4258 4259/* always-on timers dev attribute */ 4260static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { 4261 .timer_capability = OMAP_TIMER_ALWON, 4262}; 4263 4264/* pwm timers dev attribute */ 4265static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { 4266 .timer_capability = OMAP_TIMER_HAS_PWM, 4267}; 4268 4269/* timer1 */ 4270static struct omap_hwmod omap44xx_timer1_hwmod; 4271static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { 4272 { .irq = 37 + OMAP44XX_IRQ_GIC_START }, 4273 { .irq = -1 } 4274}; 4275 4276static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { 4277 { 4278 .pa_start = 0x4a318000, 4279 .pa_end = 0x4a31807f, 4280 .flags = ADDR_TYPE_RT 4281 }, 4282 { } 4283}; 4284 4285/* l4_wkup -> timer1 */ 4286static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { 4287 .master = &omap44xx_l4_wkup_hwmod, 4288 .slave = &omap44xx_timer1_hwmod, 4289 .clk = "l4_wkup_clk_mux_ck", 4290 .addr = omap44xx_timer1_addrs, 4291 .user = OCP_USER_MPU | OCP_USER_SDMA, 4292}; 4293 4294/* timer1 slave ports */ 4295static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = { 4296 &omap44xx_l4_wkup__timer1, 4297}; 4298 4299static struct omap_hwmod omap44xx_timer1_hwmod = { 4300 .name = "timer1", 4301 .class = &omap44xx_timer_1ms_hwmod_class, 4302 .clkdm_name = "l4_wkup_clkdm", 4303 .mpu_irqs = omap44xx_timer1_irqs, 4304 .main_clk = "timer1_fck", 4305 .prcm = { 4306 .omap4 = { 4307 .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET, 4308 .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET, 4309 .modulemode = MODULEMODE_SWCTRL, 4310 }, 4311 }, 4312 .dev_attr = &capability_alwon_dev_attr, 4313 .slaves = omap44xx_timer1_slaves, 4314 .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves), 4315}; 4316 4317/* timer2 */ 4318static struct omap_hwmod omap44xx_timer2_hwmod; 4319static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { 4320 { .irq = 38 + OMAP44XX_IRQ_GIC_START }, 4321 { .irq = -1 } 4322}; 4323 4324static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { 4325 { 4326 .pa_start = 0x48032000, 4327 .pa_end = 0x4803207f, 4328 .flags = ADDR_TYPE_RT 4329 }, 4330 { } 4331}; 4332 4333/* l4_per -> timer2 */ 4334static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { 4335 .master = &omap44xx_l4_per_hwmod, 4336 .slave = &omap44xx_timer2_hwmod, 4337 .clk = "l4_div_ck", 4338 .addr = omap44xx_timer2_addrs, 4339 .user = OCP_USER_MPU | OCP_USER_SDMA, 4340}; 4341 4342/* timer2 slave ports */ 4343static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = { 4344 &omap44xx_l4_per__timer2, 4345}; 4346 4347static struct omap_hwmod omap44xx_timer2_hwmod = { 4348 .name = "timer2", 4349 .class = &omap44xx_timer_1ms_hwmod_class, 4350 .clkdm_name = "l4_per_clkdm", 4351 .mpu_irqs = omap44xx_timer2_irqs, 4352 .main_clk = "timer2_fck", 4353 .prcm = { 4354 .omap4 = { 4355 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET, 4356 .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET, 4357 .modulemode = MODULEMODE_SWCTRL, 4358 }, 4359 }, 4360 .dev_attr = &capability_alwon_dev_attr, 4361 .slaves = omap44xx_timer2_slaves, 4362 .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves), 4363}; 4364 4365/* timer3 */ 4366static struct omap_hwmod omap44xx_timer3_hwmod; 4367static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { 4368 { .irq = 39 + OMAP44XX_IRQ_GIC_START }, 4369 { .irq = -1 } 4370}; 4371 4372static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { 4373 { 4374 .pa_start = 0x48034000, 4375 .pa_end = 0x4803407f, 4376 .flags = ADDR_TYPE_RT 4377 }, 4378 { } 4379}; 4380 4381/* l4_per -> timer3 */ 4382static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { 4383 .master = &omap44xx_l4_per_hwmod, 4384 .slave = &omap44xx_timer3_hwmod, 4385 .clk = "l4_div_ck", 4386 .addr = omap44xx_timer3_addrs, 4387 .user = OCP_USER_MPU | OCP_USER_SDMA, 4388}; 4389 4390/* timer3 slave ports */ 4391static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = { 4392 &omap44xx_l4_per__timer3, 4393}; 4394 4395static struct omap_hwmod omap44xx_timer3_hwmod = { 4396 .name = "timer3", 4397 .class = &omap44xx_timer_hwmod_class, 4398 .clkdm_name = "l4_per_clkdm", 4399 .mpu_irqs = omap44xx_timer3_irqs, 4400 .main_clk = "timer3_fck", 4401 .prcm = { 4402 .omap4 = { 4403 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET, 4404 .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET, 4405 .modulemode = MODULEMODE_SWCTRL, 4406 }, 4407 }, 4408 .dev_attr = &capability_alwon_dev_attr, 4409 .slaves = omap44xx_timer3_slaves, 4410 .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves), 4411}; 4412 4413/* timer4 */ 4414static struct omap_hwmod omap44xx_timer4_hwmod; 4415static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { 4416 { .irq = 40 + OMAP44XX_IRQ_GIC_START }, 4417 { .irq = -1 } 4418}; 4419 4420static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { 4421 { 4422 .pa_start = 0x48036000, 4423 .pa_end = 0x4803607f, 4424 .flags = ADDR_TYPE_RT 4425 }, 4426 { } 4427}; 4428 4429/* l4_per -> timer4 */ 4430static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { 4431 .master = &omap44xx_l4_per_hwmod, 4432 .slave = &omap44xx_timer4_hwmod, 4433 .clk = "l4_div_ck", 4434 .addr = omap44xx_timer4_addrs, 4435 .user = OCP_USER_MPU | OCP_USER_SDMA, 4436}; 4437 4438/* timer4 slave ports */ 4439static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = { 4440 &omap44xx_l4_per__timer4, 4441}; 4442 4443static struct omap_hwmod omap44xx_timer4_hwmod = { 4444 .name = "timer4", 4445 .class = &omap44xx_timer_hwmod_class, 4446 .clkdm_name = "l4_per_clkdm", 4447 .mpu_irqs = omap44xx_timer4_irqs, 4448 .main_clk = "timer4_fck", 4449 .prcm = { 4450 .omap4 = { 4451 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET, 4452 .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET, 4453 .modulemode = MODULEMODE_SWCTRL, 4454 }, 4455 }, 4456 .dev_attr = &capability_alwon_dev_attr, 4457 .slaves = omap44xx_timer4_slaves, 4458 .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves), 4459}; 4460 4461/* timer5 */ 4462static struct omap_hwmod omap44xx_timer5_hwmod; 4463static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { 4464 { .irq = 41 + OMAP44XX_IRQ_GIC_START }, 4465 { .irq = -1 } 4466}; 4467 4468static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { 4469 { 4470 .pa_start = 0x40138000, 4471 .pa_end = 0x4013807f, 4472 .flags = ADDR_TYPE_RT 4473 }, 4474 { } 4475}; 4476 4477/* l4_abe -> timer5 */ 4478static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { 4479 .master = &omap44xx_l4_abe_hwmod, 4480 .slave = &omap44xx_timer5_hwmod, 4481 .clk = "ocp_abe_iclk", 4482 .addr = omap44xx_timer5_addrs, 4483 .user = OCP_USER_MPU, 4484}; 4485 4486static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { 4487 { 4488 .pa_start = 0x49038000, 4489 .pa_end = 0x4903807f, 4490 .flags = ADDR_TYPE_RT 4491 }, 4492 { } 4493}; 4494 4495/* l4_abe -> timer5 (dma) */ 4496static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { 4497 .master = &omap44xx_l4_abe_hwmod, 4498 .slave = &omap44xx_timer5_hwmod, 4499 .clk = "ocp_abe_iclk", 4500 .addr = omap44xx_timer5_dma_addrs, 4501 .user = OCP_USER_SDMA, 4502}; 4503 4504/* timer5 slave ports */ 4505static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = { 4506 &omap44xx_l4_abe__timer5, 4507 &omap44xx_l4_abe__timer5_dma, 4508}; 4509 4510static struct omap_hwmod omap44xx_timer5_hwmod = { 4511 .name = "timer5", 4512 .class = &omap44xx_timer_hwmod_class, 4513 .clkdm_name = "abe_clkdm", 4514 .mpu_irqs = omap44xx_timer5_irqs, 4515 .main_clk = "timer5_fck", 4516 .prcm = { 4517 .omap4 = { 4518 .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET, 4519 .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET, 4520 .modulemode = MODULEMODE_SWCTRL, 4521 }, 4522 }, 4523 .dev_attr = &capability_alwon_dev_attr, 4524 .slaves = omap44xx_timer5_slaves, 4525 .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves), 4526}; 4527 4528/* timer6 */ 4529static struct omap_hwmod omap44xx_timer6_hwmod; 4530static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { 4531 { .irq = 42 + OMAP44XX_IRQ_GIC_START }, 4532 { .irq = -1 } 4533}; 4534 4535static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { 4536 { 4537 .pa_start = 0x4013a000, 4538 .pa_end = 0x4013a07f, 4539 .flags = ADDR_TYPE_RT 4540 }, 4541 { } 4542}; 4543 4544/* l4_abe -> timer6 */ 4545static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { 4546 .master = &omap44xx_l4_abe_hwmod, 4547 .slave = &omap44xx_timer6_hwmod, 4548 .clk = "ocp_abe_iclk", 4549 .addr = omap44xx_timer6_addrs, 4550 .user = OCP_USER_MPU, 4551}; 4552 4553static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { 4554 { 4555 .pa_start = 0x4903a000, 4556 .pa_end = 0x4903a07f, 4557 .flags = ADDR_TYPE_RT 4558 }, 4559 { } 4560}; 4561 4562/* l4_abe -> timer6 (dma) */ 4563static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { 4564 .master = &omap44xx_l4_abe_hwmod, 4565 .slave = &omap44xx_timer6_hwmod, 4566 .clk = "ocp_abe_iclk", 4567 .addr = omap44xx_timer6_dma_addrs, 4568 .user = OCP_USER_SDMA, 4569}; 4570 4571/* timer6 slave ports */ 4572static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = { 4573 &omap44xx_l4_abe__timer6, 4574 &omap44xx_l4_abe__timer6_dma, 4575}; 4576 4577static struct omap_hwmod omap44xx_timer6_hwmod = { 4578 .name = "timer6", 4579 .class = &omap44xx_timer_hwmod_class, 4580 .clkdm_name = "abe_clkdm", 4581 .mpu_irqs = omap44xx_timer6_irqs, 4582 4583 .main_clk = "timer6_fck", 4584 .prcm = { 4585 .omap4 = { 4586 .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET, 4587 .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET, 4588 .modulemode = MODULEMODE_SWCTRL, 4589 }, 4590 }, 4591 .dev_attr = &capability_alwon_dev_attr, 4592 .slaves = omap44xx_timer6_slaves, 4593 .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves), 4594}; 4595 4596/* timer7 */ 4597static struct omap_hwmod omap44xx_timer7_hwmod; 4598static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { 4599 { .irq = 43 + OMAP44XX_IRQ_GIC_START }, 4600 { .irq = -1 } 4601}; 4602 4603static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { 4604 { 4605 .pa_start = 0x4013c000, 4606 .pa_end = 0x4013c07f, 4607 .flags = ADDR_TYPE_RT 4608 }, 4609 { } 4610}; 4611 4612/* l4_abe -> timer7 */ 4613static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { 4614 .master = &omap44xx_l4_abe_hwmod, 4615 .slave = &omap44xx_timer7_hwmod, 4616 .clk = "ocp_abe_iclk", 4617 .addr = omap44xx_timer7_addrs, 4618 .user = OCP_USER_MPU, 4619}; 4620 4621static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { 4622 { 4623 .pa_start = 0x4903c000, 4624 .pa_end = 0x4903c07f, 4625 .flags = ADDR_TYPE_RT 4626 }, 4627 { } 4628}; 4629 4630/* l4_abe -> timer7 (dma) */ 4631static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { 4632 .master = &omap44xx_l4_abe_hwmod, 4633 .slave = &omap44xx_timer7_hwmod, 4634 .clk = "ocp_abe_iclk", 4635 .addr = omap44xx_timer7_dma_addrs, 4636 .user = OCP_USER_SDMA, 4637}; 4638 4639/* timer7 slave ports */ 4640static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = { 4641 &omap44xx_l4_abe__timer7, 4642 &omap44xx_l4_abe__timer7_dma, 4643}; 4644 4645static struct omap_hwmod omap44xx_timer7_hwmod = { 4646 .name = "timer7", 4647 .class = &omap44xx_timer_hwmod_class, 4648 .clkdm_name = "abe_clkdm", 4649 .mpu_irqs = omap44xx_timer7_irqs, 4650 .main_clk = "timer7_fck", 4651 .prcm = { 4652 .omap4 = { 4653 .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET, 4654 .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET, 4655 .modulemode = MODULEMODE_SWCTRL, 4656 }, 4657 }, 4658 .dev_attr = &capability_alwon_dev_attr, 4659 .slaves = omap44xx_timer7_slaves, 4660 .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves), 4661}; 4662 4663/* timer8 */ 4664static struct omap_hwmod omap44xx_timer8_hwmod; 4665static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { 4666 { .irq = 44 + OMAP44XX_IRQ_GIC_START }, 4667 { .irq = -1 } 4668}; 4669 4670static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { 4671 { 4672 .pa_start = 0x4013e000, 4673 .pa_end = 0x4013e07f, 4674 .flags = ADDR_TYPE_RT 4675 }, 4676 { } 4677}; 4678 4679/* l4_abe -> timer8 */ 4680static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { 4681 .master = &omap44xx_l4_abe_hwmod, 4682 .slave = &omap44xx_timer8_hwmod, 4683 .clk = "ocp_abe_iclk", 4684 .addr = omap44xx_timer8_addrs, 4685 .user = OCP_USER_MPU, 4686}; 4687 4688static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { 4689 { 4690 .pa_start = 0x4903e000, 4691 .pa_end = 0x4903e07f, 4692 .flags = ADDR_TYPE_RT 4693 }, 4694 { } 4695}; 4696 4697/* l4_abe -> timer8 (dma) */ 4698static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { 4699 .master = &omap44xx_l4_abe_hwmod, 4700 .slave = &omap44xx_timer8_hwmod, 4701 .clk = "ocp_abe_iclk", 4702 .addr = omap44xx_timer8_dma_addrs, 4703 .user = OCP_USER_SDMA, 4704}; 4705 4706/* timer8 slave ports */ 4707static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = { 4708 &omap44xx_l4_abe__timer8, 4709 &omap44xx_l4_abe__timer8_dma, 4710}; 4711 4712static struct omap_hwmod omap44xx_timer8_hwmod = { 4713 .name = "timer8", 4714 .class = &omap44xx_timer_hwmod_class, 4715 .clkdm_name = "abe_clkdm", 4716 .mpu_irqs = omap44xx_timer8_irqs, 4717 .main_clk = "timer8_fck", 4718 .prcm = { 4719 .omap4 = { 4720 .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET, 4721 .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET, 4722 .modulemode = MODULEMODE_SWCTRL, 4723 }, 4724 }, 4725 .dev_attr = &capability_pwm_dev_attr, 4726 .slaves = omap44xx_timer8_slaves, 4727 .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves), 4728}; 4729 4730/* timer9 */ 4731static struct omap_hwmod omap44xx_timer9_hwmod; 4732static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { 4733 { .irq = 45 + OMAP44XX_IRQ_GIC_START }, 4734 { .irq = -1 } 4735}; 4736 4737static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { 4738 { 4739 .pa_start = 0x4803e000, 4740 .pa_end = 0x4803e07f, 4741 .flags = ADDR_TYPE_RT 4742 }, 4743 { } 4744}; 4745 4746/* l4_per -> timer9 */ 4747static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { 4748 .master = &omap44xx_l4_per_hwmod, 4749 .slave = &omap44xx_timer9_hwmod, 4750 .clk = "l4_div_ck", 4751 .addr = omap44xx_timer9_addrs, 4752 .user = OCP_USER_MPU | OCP_USER_SDMA, 4753}; 4754 4755/* timer9 slave ports */ 4756static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = { 4757 &omap44xx_l4_per__timer9, 4758}; 4759 4760static struct omap_hwmod omap44xx_timer9_hwmod = { 4761 .name = "timer9", 4762 .class = &omap44xx_timer_hwmod_class, 4763 .clkdm_name = "l4_per_clkdm", 4764 .mpu_irqs = omap44xx_timer9_irqs, 4765 .main_clk = "timer9_fck", 4766 .prcm = { 4767 .omap4 = { 4768 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET, 4769 .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET, 4770 .modulemode = MODULEMODE_SWCTRL, 4771 }, 4772 }, 4773 .dev_attr = &capability_pwm_dev_attr, 4774 .slaves = omap44xx_timer9_slaves, 4775 .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves), 4776}; 4777 4778/* timer10 */ 4779static struct omap_hwmod omap44xx_timer10_hwmod; 4780static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { 4781 { .irq = 46 + OMAP44XX_IRQ_GIC_START }, 4782 { .irq = -1 } 4783}; 4784 4785static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { 4786 { 4787 .pa_start = 0x48086000, 4788 .pa_end = 0x4808607f, 4789 .flags = ADDR_TYPE_RT 4790 }, 4791 { } 4792}; 4793 4794/* l4_per -> timer10 */ 4795static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { 4796 .master = &omap44xx_l4_per_hwmod, 4797 .slave = &omap44xx_timer10_hwmod, 4798 .clk = "l4_div_ck", 4799 .addr = omap44xx_timer10_addrs, 4800 .user = OCP_USER_MPU | OCP_USER_SDMA, 4801}; 4802 4803/* timer10 slave ports */ 4804static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = { 4805 &omap44xx_l4_per__timer10, 4806}; 4807 4808static struct omap_hwmod omap44xx_timer10_hwmod = { 4809 .name = "timer10", 4810 .class = &omap44xx_timer_1ms_hwmod_class, 4811 .clkdm_name = "l4_per_clkdm", 4812 .mpu_irqs = omap44xx_timer10_irqs, 4813 .main_clk = "timer10_fck", 4814 .prcm = { 4815 .omap4 = { 4816 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET, 4817 .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET, 4818 .modulemode = MODULEMODE_SWCTRL, 4819 }, 4820 }, 4821 .dev_attr = &capability_pwm_dev_attr, 4822 .slaves = omap44xx_timer10_slaves, 4823 .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves), 4824}; 4825 4826/* timer11 */ 4827static struct omap_hwmod omap44xx_timer11_hwmod; 4828static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { 4829 { .irq = 47 + OMAP44XX_IRQ_GIC_START }, 4830 { .irq = -1 } 4831}; 4832 4833static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { 4834 { 4835 .pa_start = 0x48088000, 4836 .pa_end = 0x4808807f, 4837 .flags = ADDR_TYPE_RT 4838 }, 4839 { } 4840}; 4841 4842/* l4_per -> timer11 */ 4843static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { 4844 .master = &omap44xx_l4_per_hwmod, 4845 .slave = &omap44xx_timer11_hwmod, 4846 .clk = "l4_div_ck", 4847 .addr = omap44xx_timer11_addrs, 4848 .user = OCP_USER_MPU | OCP_USER_SDMA, 4849}; 4850 4851/* timer11 slave ports */ 4852static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = { 4853 &omap44xx_l4_per__timer11, 4854}; 4855 4856static struct omap_hwmod omap44xx_timer11_hwmod = { 4857 .name = "timer11", 4858 .class = &omap44xx_timer_hwmod_class, 4859 .clkdm_name = "l4_per_clkdm", 4860 .mpu_irqs = omap44xx_timer11_irqs, 4861 .main_clk = "timer11_fck", 4862 .prcm = { 4863 .omap4 = { 4864 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET, 4865 .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET, 4866 .modulemode = MODULEMODE_SWCTRL, 4867 }, 4868 }, 4869 .dev_attr = &capability_pwm_dev_attr, 4870 .slaves = omap44xx_timer11_slaves, 4871 .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves), 4872}; 4873 4874/* 4875 * 'uart' class 4876 * universal asynchronous receiver/transmitter (uart) 4877 */ 4878 4879static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { 4880 .rev_offs = 0x0050, 4881 .sysc_offs = 0x0054, 4882 .syss_offs = 0x0058, 4883 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | 4884 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 4885 SYSS_HAS_RESET_STATUS), 4886 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 4887 SIDLE_SMART_WKUP), 4888 .sysc_fields = &omap_hwmod_sysc_type1, 4889}; 4890 4891static struct omap_hwmod_class omap44xx_uart_hwmod_class = { 4892 .name = "uart", 4893 .sysc = &omap44xx_uart_sysc, 4894}; 4895 4896/* uart1 */ 4897static struct omap_hwmod omap44xx_uart1_hwmod; 4898static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { 4899 { .irq = 72 + OMAP44XX_IRQ_GIC_START }, 4900 { .irq = -1 } 4901}; 4902 4903static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { 4904 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, 4905 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, 4906 { .dma_req = -1 } 4907}; 4908 4909static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { 4910 { 4911 .pa_start = 0x4806a000, 4912 .pa_end = 0x4806a0ff, 4913 .flags = ADDR_TYPE_RT 4914 }, 4915 { } 4916}; 4917 4918/* l4_per -> uart1 */ 4919static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { 4920 .master = &omap44xx_l4_per_hwmod, 4921 .slave = &omap44xx_uart1_hwmod, 4922 .clk = "l4_div_ck", 4923 .addr = omap44xx_uart1_addrs, 4924 .user = OCP_USER_MPU | OCP_USER_SDMA, 4925}; 4926 4927/* uart1 slave ports */ 4928static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = { 4929 &omap44xx_l4_per__uart1, 4930}; 4931 4932static struct omap_hwmod omap44xx_uart1_hwmod = { 4933 .name = "uart1", 4934 .class = &omap44xx_uart_hwmod_class, 4935 .clkdm_name = "l4_per_clkdm", 4936 .mpu_irqs = omap44xx_uart1_irqs, 4937 .sdma_reqs = omap44xx_uart1_sdma_reqs, 4938 .main_clk = "uart1_fck", 4939 .prcm = { 4940 .omap4 = { 4941 .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET, 4942 .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET, 4943 .modulemode = MODULEMODE_SWCTRL, 4944 }, 4945 }, 4946 .slaves = omap44xx_uart1_slaves, 4947 .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves), 4948}; 4949 4950/* uart2 */ 4951static struct omap_hwmod omap44xx_uart2_hwmod; 4952static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { 4953 { .irq = 73 + OMAP44XX_IRQ_GIC_START }, 4954 { .irq = -1 } 4955}; 4956 4957static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { 4958 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, 4959 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, 4960 { .dma_req = -1 } 4961}; 4962 4963static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { 4964 { 4965 .pa_start = 0x4806c000, 4966 .pa_end = 0x4806c0ff, 4967 .flags = ADDR_TYPE_RT 4968 }, 4969 { } 4970}; 4971 4972/* l4_per -> uart2 */ 4973static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { 4974 .master = &omap44xx_l4_per_hwmod, 4975 .slave = &omap44xx_uart2_hwmod, 4976 .clk = "l4_div_ck", 4977 .addr = omap44xx_uart2_addrs, 4978 .user = OCP_USER_MPU | OCP_USER_SDMA, 4979}; 4980 4981/* uart2 slave ports */ 4982static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = { 4983 &omap44xx_l4_per__uart2, 4984}; 4985 4986static struct omap_hwmod omap44xx_uart2_hwmod = { 4987 .name = "uart2", 4988 .class = &omap44xx_uart_hwmod_class, 4989 .clkdm_name = "l4_per_clkdm", 4990 .mpu_irqs = omap44xx_uart2_irqs, 4991 .sdma_reqs = omap44xx_uart2_sdma_reqs, 4992 .main_clk = "uart2_fck", 4993 .prcm = { 4994 .omap4 = { 4995 .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET, 4996 .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET, 4997 .modulemode = MODULEMODE_SWCTRL, 4998 }, 4999 }, 5000 .slaves = omap44xx_uart2_slaves, 5001 .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves), 5002}; 5003 5004/* uart3 */ 5005static struct omap_hwmod omap44xx_uart3_hwmod; 5006static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { 5007 { .irq = 74 + OMAP44XX_IRQ_GIC_START }, 5008 { .irq = -1 } 5009}; 5010 5011static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { 5012 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, 5013 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, 5014 { .dma_req = -1 } 5015}; 5016 5017static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { 5018 { 5019 .pa_start = 0x48020000, 5020 .pa_end = 0x480200ff, 5021 .flags = ADDR_TYPE_RT 5022 }, 5023 { } 5024}; 5025 5026/* l4_per -> uart3 */ 5027static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { 5028 .master = &omap44xx_l4_per_hwmod, 5029 .slave = &omap44xx_uart3_hwmod, 5030 .clk = "l4_div_ck", 5031 .addr = omap44xx_uart3_addrs, 5032 .user = OCP_USER_MPU | OCP_USER_SDMA, 5033}; 5034 5035/* uart3 slave ports */ 5036static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = { 5037 &omap44xx_l4_per__uart3, 5038}; 5039 5040static struct omap_hwmod omap44xx_uart3_hwmod = { 5041 .name = "uart3", 5042 .class = &omap44xx_uart_hwmod_class, 5043 .clkdm_name = "l4_per_clkdm", 5044 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, 5045 .mpu_irqs = omap44xx_uart3_irqs, 5046 .sdma_reqs = omap44xx_uart3_sdma_reqs, 5047 .main_clk = "uart3_fck", 5048 .prcm = { 5049 .omap4 = { 5050 .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET, 5051 .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET, 5052 .modulemode = MODULEMODE_SWCTRL, 5053 }, 5054 }, 5055 .slaves = omap44xx_uart3_slaves, 5056 .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves), 5057}; 5058 5059/* uart4 */ 5060static struct omap_hwmod omap44xx_uart4_hwmod; 5061static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { 5062 { .irq = 70 + OMAP44XX_IRQ_GIC_START }, 5063 { .irq = -1 } 5064}; 5065 5066static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { 5067 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, 5068 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, 5069 { .dma_req = -1 } 5070}; 5071 5072static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { 5073 { 5074 .pa_start = 0x4806e000, 5075 .pa_end = 0x4806e0ff, 5076 .flags = ADDR_TYPE_RT 5077 }, 5078 { } 5079}; 5080 5081/* l4_per -> uart4 */ 5082static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { 5083 .master = &omap44xx_l4_per_hwmod, 5084 .slave = &omap44xx_uart4_hwmod, 5085 .clk = "l4_div_ck", 5086 .addr = omap44xx_uart4_addrs, 5087 .user = OCP_USER_MPU | OCP_USER_SDMA, 5088}; 5089 5090/* uart4 slave ports */ 5091static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = { 5092 &omap44xx_l4_per__uart4, 5093}; 5094 5095static struct omap_hwmod omap44xx_uart4_hwmod = { 5096 .name = "uart4", 5097 .class = &omap44xx_uart_hwmod_class, 5098 .clkdm_name = "l4_per_clkdm", 5099 .mpu_irqs = omap44xx_uart4_irqs, 5100 .sdma_reqs = omap44xx_uart4_sdma_reqs, 5101 .main_clk = "uart4_fck", 5102 .prcm = { 5103 .omap4 = { 5104 .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET, 5105 .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET, 5106 .modulemode = MODULEMODE_SWCTRL, 5107 }, 5108 }, 5109 .slaves = omap44xx_uart4_slaves, 5110 .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves), 5111}; 5112 5113/* 5114 * 'usb_otg_hs' class 5115 * high-speed on-the-go universal serial bus (usb_otg_hs) controller 5116 */ 5117 5118static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = { 5119 .rev_offs = 0x0400, 5120 .sysc_offs = 0x0404, 5121 .syss_offs = 0x0408, 5122 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | 5123 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | 5124 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 5125 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 5126 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | 5127 MSTANDBY_SMART), 5128 .sysc_fields = &omap_hwmod_sysc_type1, 5129}; 5130 5131static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { 5132 .name = "usb_otg_hs", 5133 .sysc = &omap44xx_usb_otg_hs_sysc, 5134}; 5135 5136/* usb_otg_hs */ 5137static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { 5138 { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START }, 5139 { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START }, 5140 { .irq = -1 } 5141}; 5142 5143/* usb_otg_hs master ports */ 5144static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = { 5145 &omap44xx_usb_otg_hs__l3_main_2, 5146}; 5147 5148static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { 5149 { 5150 .pa_start = 0x4a0ab000, 5151 .pa_end = 0x4a0ab003, 5152 .flags = ADDR_TYPE_RT 5153 }, 5154 { } 5155}; 5156 5157/* l4_cfg -> usb_otg_hs */ 5158static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { 5159 .master = &omap44xx_l4_cfg_hwmod, 5160 .slave = &omap44xx_usb_otg_hs_hwmod, 5161 .clk = "l4_div_ck", 5162 .addr = omap44xx_usb_otg_hs_addrs, 5163 .user = OCP_USER_MPU | OCP_USER_SDMA, 5164}; 5165 5166/* usb_otg_hs slave ports */ 5167static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = { 5168 &omap44xx_l4_cfg__usb_otg_hs, 5169}; 5170 5171static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { 5172 { .role = "xclk", .clk = "usb_otg_hs_xclk" }, 5173}; 5174 5175static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { 5176 .name = "usb_otg_hs", 5177 .class = &omap44xx_usb_otg_hs_hwmod_class, 5178 .clkdm_name = "l3_init_clkdm", 5179 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, 5180 .mpu_irqs = omap44xx_usb_otg_hs_irqs, 5181 .main_clk = "usb_otg_hs_ick", 5182 .prcm = { 5183 .omap4 = { 5184 .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET, 5185 .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET, 5186 .modulemode = MODULEMODE_HWCTRL, 5187 }, 5188 }, 5189 .opt_clks = usb_otg_hs_opt_clks, 5190 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), 5191 .slaves = omap44xx_usb_otg_hs_slaves, 5192 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves), 5193 .masters = omap44xx_usb_otg_hs_masters, 5194 .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters), 5195}; 5196 5197/* 5198 * 'wd_timer' class 5199 * 32-bit watchdog upward counter that generates a pulse on the reset pin on 5200 * overflow condition 5201 */ 5202 5203static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { 5204 .rev_offs = 0x0000, 5205 .sysc_offs = 0x0010, 5206 .syss_offs = 0x0014, 5207 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | 5208 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 5209 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 5210 SIDLE_SMART_WKUP), 5211 .sysc_fields = &omap_hwmod_sysc_type1, 5212}; 5213 5214static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { 5215 .name = "wd_timer", 5216 .sysc = &omap44xx_wd_timer_sysc, 5217 .pre_shutdown = &omap2_wd_timer_disable, 5218}; 5219 5220/* wd_timer2 */ 5221static struct omap_hwmod omap44xx_wd_timer2_hwmod; 5222static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { 5223 { .irq = 80 + OMAP44XX_IRQ_GIC_START }, 5224 { .irq = -1 } 5225}; 5226 5227static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { 5228 { 5229 .pa_start = 0x4a314000, 5230 .pa_end = 0x4a31407f, 5231 .flags = ADDR_TYPE_RT 5232 }, 5233 { } 5234}; 5235 5236/* l4_wkup -> wd_timer2 */ 5237static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { 5238 .master = &omap44xx_l4_wkup_hwmod, 5239 .slave = &omap44xx_wd_timer2_hwmod, 5240 .clk = "l4_wkup_clk_mux_ck", 5241 .addr = omap44xx_wd_timer2_addrs, 5242 .user = OCP_USER_MPU | OCP_USER_SDMA, 5243}; 5244 5245/* wd_timer2 slave ports */ 5246static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = { 5247 &omap44xx_l4_wkup__wd_timer2, 5248}; 5249 5250static struct omap_hwmod omap44xx_wd_timer2_hwmod = { 5251 .name = "wd_timer2", 5252 .class = &omap44xx_wd_timer_hwmod_class, 5253 .clkdm_name = "l4_wkup_clkdm", 5254 .mpu_irqs = omap44xx_wd_timer2_irqs, 5255 .main_clk = "wd_timer2_fck", 5256 .prcm = { 5257 .omap4 = { 5258 .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET, 5259 .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET, 5260 .modulemode = MODULEMODE_SWCTRL, 5261 }, 5262 }, 5263 .slaves = omap44xx_wd_timer2_slaves, 5264 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves), 5265}; 5266 5267/* wd_timer3 */ 5268static struct omap_hwmod omap44xx_wd_timer3_hwmod; 5269static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { 5270 { .irq = 36 + OMAP44XX_IRQ_GIC_START }, 5271 { .irq = -1 } 5272}; 5273 5274static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { 5275 { 5276 .pa_start = 0x40130000, 5277 .pa_end = 0x4013007f, 5278 .flags = ADDR_TYPE_RT 5279 }, 5280 { } 5281}; 5282 5283/* l4_abe -> wd_timer3 */ 5284static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { 5285 .master = &omap44xx_l4_abe_hwmod, 5286 .slave = &omap44xx_wd_timer3_hwmod, 5287 .clk = "ocp_abe_iclk", 5288 .addr = omap44xx_wd_timer3_addrs, 5289 .user = OCP_USER_MPU, 5290}; 5291 5292static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { 5293 { 5294 .pa_start = 0x49030000, 5295 .pa_end = 0x4903007f, 5296 .flags = ADDR_TYPE_RT 5297 }, 5298 { } 5299}; 5300 5301/* l4_abe -> wd_timer3 (dma) */ 5302static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { 5303 .master = &omap44xx_l4_abe_hwmod, 5304 .slave = &omap44xx_wd_timer3_hwmod, 5305 .clk = "ocp_abe_iclk", 5306 .addr = omap44xx_wd_timer3_dma_addrs, 5307 .user = OCP_USER_SDMA, 5308}; 5309 5310/* wd_timer3 slave ports */ 5311static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = { 5312 &omap44xx_l4_abe__wd_timer3, 5313 &omap44xx_l4_abe__wd_timer3_dma, 5314}; 5315 5316static struct omap_hwmod omap44xx_wd_timer3_hwmod = { 5317 .name = "wd_timer3", 5318 .class = &omap44xx_wd_timer_hwmod_class, 5319 .clkdm_name = "abe_clkdm", 5320 .mpu_irqs = omap44xx_wd_timer3_irqs, 5321 .main_clk = "wd_timer3_fck", 5322 .prcm = { 5323 .omap4 = { 5324 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, 5325 .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET, 5326 .modulemode = MODULEMODE_SWCTRL, 5327 }, 5328 }, 5329 .slaves = omap44xx_wd_timer3_slaves, 5330 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves), 5331}; 5332 5333/* 5334 * 'usb_host_hs' class 5335 * high-speed multi-port usb host controller 5336 */ 5337static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { 5338 .master = &omap44xx_usb_host_hs_hwmod, 5339 .slave = &omap44xx_l3_main_2_hwmod, 5340 .clk = "l3_div_ck", 5341 .user = OCP_USER_MPU | OCP_USER_SDMA, 5342}; 5343 5344static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { 5345 .rev_offs = 0x0000, 5346 .sysc_offs = 0x0010, 5347 .syss_offs = 0x0014, 5348 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | 5349 SYSC_HAS_SOFTRESET), 5350 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 5351 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | 5352 MSTANDBY_SMART | MSTANDBY_SMART_WKUP), 5353 .sysc_fields = &omap_hwmod_sysc_type2, 5354}; 5355 5356static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { 5357 .name = "usb_host_hs", 5358 .sysc = &omap44xx_usb_host_hs_sysc, 5359}; 5360 5361static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_masters[] = { 5362 &omap44xx_usb_host_hs__l3_main_2, 5363}; 5364 5365static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { 5366 { 5367 .name = "uhh", 5368 .pa_start = 0x4a064000, 5369 .pa_end = 0x4a0647ff, 5370 .flags = ADDR_TYPE_RT 5371 }, 5372 { 5373 .name = "ohci", 5374 .pa_start = 0x4a064800, 5375 .pa_end = 0x4a064bff, 5376 }, 5377 { 5378 .name = "ehci", 5379 .pa_start = 0x4a064c00, 5380 .pa_end = 0x4a064fff, 5381 }, 5382 {} 5383}; 5384 5385static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { 5386 { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START }, 5387 { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START }, 5388 { .irq = -1 } 5389}; 5390 5391static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { 5392 .master = &omap44xx_l4_cfg_hwmod, 5393 .slave = &omap44xx_usb_host_hs_hwmod, 5394 .clk = "l4_div_ck", 5395 .addr = omap44xx_usb_host_hs_addrs, 5396 .user = OCP_USER_MPU | OCP_USER_SDMA, 5397}; 5398 5399static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_slaves[] = { 5400 &omap44xx_l4_cfg__usb_host_hs, 5401}; 5402 5403static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { 5404 .name = "usb_host_hs", 5405 .class = &omap44xx_usb_host_hs_hwmod_class, 5406 .clkdm_name = "l3_init_clkdm", 5407 .main_clk = "usb_host_hs_fck", 5408 .prcm = { 5409 .omap4 = { 5410 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, 5411 .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, 5412 .modulemode = MODULEMODE_SWCTRL, 5413 }, 5414 }, 5415 .mpu_irqs = omap44xx_usb_host_hs_irqs, 5416 .slaves = omap44xx_usb_host_hs_slaves, 5417 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_slaves), 5418 .masters = omap44xx_usb_host_hs_masters, 5419 .masters_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_masters), 5420 5421 /* 5422 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock 5423 * id: i660 5424 * 5425 * Description: 5426 * In the following configuration : 5427 * - USBHOST module is set to smart-idle mode 5428 * - PRCM asserts idle_req to the USBHOST module ( This typically 5429 * happens when the system is going to a low power mode : all ports 5430 * have been suspended, the master part of the USBHOST module has 5431 * entered the standby state, and SW has cut the functional clocks) 5432 * - an USBHOST interrupt occurs before the module is able to answer 5433 * idle_ack, typically a remote wakeup IRQ. 5434 * Then the USB HOST module will enter a deadlock situation where it 5435 * is no more accessible nor functional. 5436 * 5437 * Workaround: 5438 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE 5439 */ 5440 5441 /* 5442 * Errata: USB host EHCI may stall when entering smart-standby mode 5443 * Id: i571 5444 * 5445 * Description: 5446 * When the USBHOST module is set to smart-standby mode, and when it is 5447 * ready to enter the standby state (i.e. all ports are suspended and 5448 * all attached devices are in suspend mode), then it can wrongly assert 5449 * the Mstandby signal too early while there are still some residual OCP 5450 * transactions ongoing. If this condition occurs, the internal state 5451 * machine may go to an undefined state and the USB link may be stuck 5452 * upon the next resume. 5453 * 5454 * Workaround: 5455 * Don't use smart standby; use only force standby, 5456 * hence HWMOD_SWSUP_MSTANDBY 5457 */ 5458 5459 /* 5460 * During system boot; If the hwmod framework resets the module 5461 * the module will have smart idle settings; which can lead to deadlock 5462 * (above Errata Id:i660); so, dont reset the module during boot; 5463 * Use HWMOD_INIT_NO_RESET. 5464 */ 5465 5466 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | 5467 HWMOD_INIT_NO_RESET, 5468}; 5469 5470/* 5471 * 'usb_tll_hs' class 5472 * usb_tll_hs module is the adapter on the usb_host_hs ports 5473 */ 5474static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { 5475 .rev_offs = 0x0000, 5476 .sysc_offs = 0x0010, 5477 .syss_offs = 0x0014, 5478 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 5479 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 5480 SYSC_HAS_AUTOIDLE), 5481 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 5482 .sysc_fields = &omap_hwmod_sysc_type1, 5483}; 5484 5485static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { 5486 .name = "usb_tll_hs", 5487 .sysc = &omap44xx_usb_tll_hs_sysc, 5488}; 5489 5490static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { 5491 { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, 5492 { .irq = -1 } 5493}; 5494 5495static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { 5496 { 5497 .name = "tll", 5498 .pa_start = 0x4a062000, 5499 .pa_end = 0x4a063fff, 5500 .flags = ADDR_TYPE_RT 5501 }, 5502 {} 5503}; 5504 5505static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { 5506 .master = &omap44xx_l4_cfg_hwmod, 5507 .slave = &omap44xx_usb_tll_hs_hwmod, 5508 .clk = "l4_div_ck", 5509 .addr = omap44xx_usb_tll_hs_addrs, 5510 .user = OCP_USER_MPU | OCP_USER_SDMA, 5511}; 5512 5513static struct omap_hwmod_ocp_if *omap44xx_usb_tll_hs_slaves[] = { 5514 &omap44xx_l4_cfg__usb_tll_hs, 5515}; 5516 5517static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { 5518 .name = "usb_tll_hs", 5519 .class = &omap44xx_usb_tll_hs_hwmod_class, 5520 .clkdm_name = "l3_init_clkdm", 5521 .main_clk = "usb_tll_hs_ick", 5522 .prcm = { 5523 .omap4 = { 5524 .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, 5525 .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, 5526 .modulemode = MODULEMODE_HWCTRL, 5527 }, 5528 }, 5529 .mpu_irqs = omap44xx_usb_tll_hs_irqs, 5530 .slaves = omap44xx_usb_tll_hs_slaves, 5531 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_tll_hs_slaves), 5532}; 5533 5534static __initdata struct omap_hwmod *omap44xx_hwmods[] = { 5535 5536 /* dmm class */ 5537 &omap44xx_dmm_hwmod, 5538 5539 /* emif_fw class */ 5540 &omap44xx_emif_fw_hwmod, 5541 5542 /* l3 class */ 5543 &omap44xx_l3_instr_hwmod, 5544 &omap44xx_l3_main_1_hwmod, 5545 &omap44xx_l3_main_2_hwmod, 5546 &omap44xx_l3_main_3_hwmod, 5547 5548 /* l4 class */ 5549 &omap44xx_l4_abe_hwmod, 5550 &omap44xx_l4_cfg_hwmod, 5551 &omap44xx_l4_per_hwmod, 5552 &omap44xx_l4_wkup_hwmod, 5553 5554 /* mpu_bus class */ 5555 &omap44xx_mpu_private_hwmod, 5556 5557 /* aess class */ 5558/* &omap44xx_aess_hwmod, */ 5559 5560 /* bandgap class */ 5561 &omap44xx_bandgap_hwmod, 5562 5563 /* counter class */ 5564/* &omap44xx_counter_32k_hwmod, */ 5565 5566 /* dma class */ 5567 &omap44xx_dma_system_hwmod, 5568 5569 /* dmic class */ 5570 &omap44xx_dmic_hwmod, 5571 5572 /* dsp class */ 5573 &omap44xx_dsp_hwmod, 5574 &omap44xx_dsp_c0_hwmod, 5575 5576 /* dss class */ 5577 &omap44xx_dss_hwmod, 5578 &omap44xx_dss_dispc_hwmod, 5579 &omap44xx_dss_dsi1_hwmod, 5580 &omap44xx_dss_dsi2_hwmod, 5581 &omap44xx_dss_hdmi_hwmod, 5582 &omap44xx_dss_rfbi_hwmod, 5583 &omap44xx_dss_venc_hwmod, 5584 5585 /* gpio class */ 5586 &omap44xx_gpio1_hwmod, 5587 &omap44xx_gpio2_hwmod, 5588 &omap44xx_gpio3_hwmod, 5589 &omap44xx_gpio4_hwmod, 5590 &omap44xx_gpio5_hwmod, 5591 &omap44xx_gpio6_hwmod, 5592 5593 /* hsi class */ 5594/* &omap44xx_hsi_hwmod, */ 5595 5596 /* i2c class */ 5597 &omap44xx_i2c1_hwmod, 5598 &omap44xx_i2c2_hwmod, 5599 &omap44xx_i2c3_hwmod, 5600 &omap44xx_i2c4_hwmod, 5601 5602 /* ipu class */ 5603 &omap44xx_ipu_hwmod, 5604 &omap44xx_ipu_c0_hwmod, 5605 &omap44xx_ipu_c1_hwmod, 5606 5607 /* iss class */ 5608/* &omap44xx_iss_hwmod, */ 5609 5610 /* iva class */ 5611 &omap44xx_iva_hwmod, 5612 &omap44xx_iva_seq0_hwmod, 5613 &omap44xx_iva_seq1_hwmod, 5614 5615 /* kbd class */ 5616 &omap44xx_kbd_hwmod, 5617 5618 /* mailbox class */ 5619 &omap44xx_mailbox_hwmod, 5620 5621 /* mcbsp class */ 5622 &omap44xx_mcbsp1_hwmod, 5623 &omap44xx_mcbsp2_hwmod, 5624 &omap44xx_mcbsp3_hwmod, 5625 &omap44xx_mcbsp4_hwmod, 5626 5627 /* mcpdm class */ 5628 &omap44xx_mcpdm_hwmod, 5629 5630 /* mcspi class */ 5631 &omap44xx_mcspi1_hwmod, 5632 &omap44xx_mcspi2_hwmod, 5633 &omap44xx_mcspi3_hwmod, 5634 &omap44xx_mcspi4_hwmod, 5635 5636 /* mmc class */ 5637 &omap44xx_mmc1_hwmod, 5638 &omap44xx_mmc2_hwmod, 5639 &omap44xx_mmc3_hwmod, 5640 &omap44xx_mmc4_hwmod, 5641 &omap44xx_mmc5_hwmod, 5642 5643 /* mpu class */ 5644 &omap44xx_mpu_hwmod, 5645 5646 /* smartreflex class */ 5647 &omap44xx_smartreflex_core_hwmod, 5648 &omap44xx_smartreflex_iva_hwmod, 5649 &omap44xx_smartreflex_mpu_hwmod, 5650 5651 /* spinlock class */ 5652 &omap44xx_spinlock_hwmod, 5653 5654 /* timer class */ 5655 &omap44xx_timer1_hwmod, 5656 &omap44xx_timer2_hwmod, 5657 &omap44xx_timer3_hwmod, 5658 &omap44xx_timer4_hwmod, 5659 &omap44xx_timer5_hwmod, 5660 &omap44xx_timer6_hwmod, 5661 &omap44xx_timer7_hwmod, 5662 &omap44xx_timer8_hwmod, 5663 &omap44xx_timer9_hwmod, 5664 &omap44xx_timer10_hwmod, 5665 &omap44xx_timer11_hwmod, 5666 5667 /* uart class */ 5668 &omap44xx_uart1_hwmod, 5669 &omap44xx_uart2_hwmod, 5670 &omap44xx_uart3_hwmod, 5671 &omap44xx_uart4_hwmod, 5672 5673 /* usb host class */ 5674 &omap44xx_usb_host_hs_hwmod, 5675 &omap44xx_usb_tll_hs_hwmod, 5676 5677 /* usb_otg_hs class */ 5678 &omap44xx_usb_otg_hs_hwmod, 5679 5680 /* wd_timer class */ 5681 &omap44xx_wd_timer2_hwmod, 5682 &omap44xx_wd_timer3_hwmod, 5683 NULL, 5684}; 5685 5686int __init omap44xx_hwmod_init(void) 5687{ 5688 return omap_hwmod_register(omap44xx_hwmods); 5689} 5690 5691