1/* 2 * arch/arm/mach-spear3xx/spear320.c 3 * 4 * SPEAr320 machine source file 5 * 6 * Copyright (C) 2009 ST Microelectronics 7 * Viresh Kumar<viresh.kumar@st.com> 8 * 9 * This file is licensed under the terms of the GNU General Public 10 * License version 2. This program is licensed "as is" without any 11 * warranty of any kind, whether express or implied. 12 */ 13 14#include <linux/ptrace.h> 15#include <asm/irq.h> 16#include <plat/shirq.h> 17#include <mach/generic.h> 18#include <mach/hardware.h> 19 20/* pad multiplexing support */ 21/* muxing registers */ 22#define PAD_MUX_CONFIG_REG 0x0C 23#define MODE_CONFIG_REG 0x10 24 25/* modes */ 26#define AUTO_NET_SMII_MODE (1 << 0) 27#define AUTO_NET_MII_MODE (1 << 1) 28#define AUTO_EXP_MODE (1 << 2) 29#define SMALL_PRINTERS_MODE (1 << 3) 30#define ALL_MODES 0xF 31 32struct pmx_mode spear320_auto_net_smii_mode = { 33 .id = AUTO_NET_SMII_MODE, 34 .name = "Automation Networking SMII Mode", 35 .mask = 0x00, 36}; 37 38struct pmx_mode spear320_auto_net_mii_mode = { 39 .id = AUTO_NET_MII_MODE, 40 .name = "Automation Networking MII Mode", 41 .mask = 0x01, 42}; 43 44struct pmx_mode spear320_auto_exp_mode = { 45 .id = AUTO_EXP_MODE, 46 .name = "Automation Expanded Mode", 47 .mask = 0x02, 48}; 49 50struct pmx_mode spear320_small_printers_mode = { 51 .id = SMALL_PRINTERS_MODE, 52 .name = "Small Printers Mode", 53 .mask = 0x03, 54}; 55 56/* devices */ 57static struct pmx_dev_mode pmx_clcd_modes[] = { 58 { 59 .ids = AUTO_NET_SMII_MODE, 60 .mask = 0x0, 61 }, 62}; 63 64struct pmx_dev spear320_pmx_clcd = { 65 .name = "clcd", 66 .modes = pmx_clcd_modes, 67 .mode_count = ARRAY_SIZE(pmx_clcd_modes), 68 .enb_on_reset = 1, 69}; 70 71static struct pmx_dev_mode pmx_emi_modes[] = { 72 { 73 .ids = AUTO_EXP_MODE, 74 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, 75 }, 76}; 77 78struct pmx_dev spear320_pmx_emi = { 79 .name = "emi", 80 .modes = pmx_emi_modes, 81 .mode_count = ARRAY_SIZE(pmx_emi_modes), 82 .enb_on_reset = 1, 83}; 84 85static struct pmx_dev_mode pmx_fsmc_modes[] = { 86 { 87 .ids = ALL_MODES, 88 .mask = 0x0, 89 }, 90}; 91 92struct pmx_dev spear320_pmx_fsmc = { 93 .name = "fsmc", 94 .modes = pmx_fsmc_modes, 95 .mode_count = ARRAY_SIZE(pmx_fsmc_modes), 96 .enb_on_reset = 1, 97}; 98 99static struct pmx_dev_mode pmx_spp_modes[] = { 100 { 101 .ids = SMALL_PRINTERS_MODE, 102 .mask = 0x0, 103 }, 104}; 105 106struct pmx_dev spear320_pmx_spp = { 107 .name = "spp", 108 .modes = pmx_spp_modes, 109 .mode_count = ARRAY_SIZE(pmx_spp_modes), 110 .enb_on_reset = 1, 111}; 112 113static struct pmx_dev_mode pmx_sdhci_modes[] = { 114 { 115 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | 116 SMALL_PRINTERS_MODE, 117 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, 118 }, 119}; 120 121struct pmx_dev spear320_pmx_sdhci = { 122 .name = "sdhci", 123 .modes = pmx_sdhci_modes, 124 .mode_count = ARRAY_SIZE(pmx_sdhci_modes), 125 .enb_on_reset = 1, 126}; 127 128static struct pmx_dev_mode pmx_i2s_modes[] = { 129 { 130 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, 131 .mask = PMX_UART0_MODEM_MASK, 132 }, 133}; 134 135struct pmx_dev spear320_pmx_i2s = { 136 .name = "i2s", 137 .modes = pmx_i2s_modes, 138 .mode_count = ARRAY_SIZE(pmx_i2s_modes), 139 .enb_on_reset = 1, 140}; 141 142static struct pmx_dev_mode pmx_uart1_modes[] = { 143 { 144 .ids = ALL_MODES, 145 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK, 146 }, 147}; 148 149struct pmx_dev spear320_pmx_uart1 = { 150 .name = "uart1", 151 .modes = pmx_uart1_modes, 152 .mode_count = ARRAY_SIZE(pmx_uart1_modes), 153 .enb_on_reset = 1, 154}; 155 156static struct pmx_dev_mode pmx_uart1_modem_modes[] = { 157 { 158 .ids = AUTO_EXP_MODE, 159 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | 160 PMX_SSP_CS_MASK, 161 }, { 162 .ids = SMALL_PRINTERS_MODE, 163 .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK | 164 PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK, 165 }, 166}; 167 168struct pmx_dev spear320_pmx_uart1_modem = { 169 .name = "uart1_modem", 170 .modes = pmx_uart1_modem_modes, 171 .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes), 172 .enb_on_reset = 1, 173}; 174 175static struct pmx_dev_mode pmx_uart2_modes[] = { 176 { 177 .ids = ALL_MODES, 178 .mask = PMX_FIRDA_MASK, 179 }, 180}; 181 182struct pmx_dev spear320_pmx_uart2 = { 183 .name = "uart2", 184 .modes = pmx_uart2_modes, 185 .mode_count = ARRAY_SIZE(pmx_uart2_modes), 186 .enb_on_reset = 1, 187}; 188 189static struct pmx_dev_mode pmx_touchscreen_modes[] = { 190 { 191 .ids = AUTO_NET_SMII_MODE, 192 .mask = PMX_SSP_CS_MASK, 193 }, 194}; 195 196struct pmx_dev spear320_pmx_touchscreen = { 197 .name = "touchscreen", 198 .modes = pmx_touchscreen_modes, 199 .mode_count = ARRAY_SIZE(pmx_touchscreen_modes), 200 .enb_on_reset = 1, 201}; 202 203static struct pmx_dev_mode pmx_can_modes[] = { 204 { 205 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE, 206 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | 207 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, 208 }, 209}; 210 211struct pmx_dev spear320_pmx_can = { 212 .name = "can", 213 .modes = pmx_can_modes, 214 .mode_count = ARRAY_SIZE(pmx_can_modes), 215 .enb_on_reset = 1, 216}; 217 218static struct pmx_dev_mode pmx_sdhci_led_modes[] = { 219 { 220 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, 221 .mask = PMX_SSP_CS_MASK, 222 }, 223}; 224 225struct pmx_dev spear320_pmx_sdhci_led = { 226 .name = "sdhci_led", 227 .modes = pmx_sdhci_led_modes, 228 .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes), 229 .enb_on_reset = 1, 230}; 231 232static struct pmx_dev_mode pmx_pwm0_modes[] = { 233 { 234 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, 235 .mask = PMX_UART0_MODEM_MASK, 236 }, { 237 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE, 238 .mask = PMX_MII_MASK, 239 }, 240}; 241 242struct pmx_dev spear320_pmx_pwm0 = { 243 .name = "pwm0", 244 .modes = pmx_pwm0_modes, 245 .mode_count = ARRAY_SIZE(pmx_pwm0_modes), 246 .enb_on_reset = 1, 247}; 248 249static struct pmx_dev_mode pmx_pwm1_modes[] = { 250 { 251 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, 252 .mask = PMX_UART0_MODEM_MASK, 253 }, { 254 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE, 255 .mask = PMX_MII_MASK, 256 }, 257}; 258 259struct pmx_dev spear320_pmx_pwm1 = { 260 .name = "pwm1", 261 .modes = pmx_pwm1_modes, 262 .mode_count = ARRAY_SIZE(pmx_pwm1_modes), 263 .enb_on_reset = 1, 264}; 265 266static struct pmx_dev_mode pmx_pwm2_modes[] = { 267 { 268 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, 269 .mask = PMX_SSP_CS_MASK, 270 }, { 271 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE, 272 .mask = PMX_MII_MASK, 273 }, 274}; 275 276struct pmx_dev spear320_pmx_pwm2 = { 277 .name = "pwm2", 278 .modes = pmx_pwm2_modes, 279 .mode_count = ARRAY_SIZE(pmx_pwm2_modes), 280 .enb_on_reset = 1, 281}; 282 283static struct pmx_dev_mode pmx_pwm3_modes[] = { 284 { 285 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE, 286 .mask = PMX_MII_MASK, 287 }, 288}; 289 290struct pmx_dev spear320_pmx_pwm3 = { 291 .name = "pwm3", 292 .modes = pmx_pwm3_modes, 293 .mode_count = ARRAY_SIZE(pmx_pwm3_modes), 294 .enb_on_reset = 1, 295}; 296 297static struct pmx_dev_mode pmx_ssp1_modes[] = { 298 { 299 .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE, 300 .mask = PMX_MII_MASK, 301 }, 302}; 303 304struct pmx_dev spear320_pmx_ssp1 = { 305 .name = "ssp1", 306 .modes = pmx_ssp1_modes, 307 .mode_count = ARRAY_SIZE(pmx_ssp1_modes), 308 .enb_on_reset = 1, 309}; 310 311static struct pmx_dev_mode pmx_ssp2_modes[] = { 312 { 313 .ids = AUTO_NET_SMII_MODE, 314 .mask = PMX_MII_MASK, 315 }, 316}; 317 318struct pmx_dev spear320_pmx_ssp2 = { 319 .name = "ssp2", 320 .modes = pmx_ssp2_modes, 321 .mode_count = ARRAY_SIZE(pmx_ssp2_modes), 322 .enb_on_reset = 1, 323}; 324 325static struct pmx_dev_mode pmx_mii1_modes[] = { 326 { 327 .ids = AUTO_NET_MII_MODE, 328 .mask = 0x0, 329 }, 330}; 331 332struct pmx_dev spear320_pmx_mii1 = { 333 .name = "mii1", 334 .modes = pmx_mii1_modes, 335 .mode_count = ARRAY_SIZE(pmx_mii1_modes), 336 .enb_on_reset = 1, 337}; 338 339static struct pmx_dev_mode pmx_smii0_modes[] = { 340 { 341 .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE, 342 .mask = PMX_MII_MASK, 343 }, 344}; 345 346struct pmx_dev spear320_pmx_smii0 = { 347 .name = "smii0", 348 .modes = pmx_smii0_modes, 349 .mode_count = ARRAY_SIZE(pmx_smii0_modes), 350 .enb_on_reset = 1, 351}; 352 353static struct pmx_dev_mode pmx_smii1_modes[] = { 354 { 355 .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE, 356 .mask = PMX_MII_MASK, 357 }, 358}; 359 360struct pmx_dev spear320_pmx_smii1 = { 361 .name = "smii1", 362 .modes = pmx_smii1_modes, 363 .mode_count = ARRAY_SIZE(pmx_smii1_modes), 364 .enb_on_reset = 1, 365}; 366 367static struct pmx_dev_mode pmx_i2c1_modes[] = { 368 { 369 .ids = AUTO_EXP_MODE, 370 .mask = 0x0, 371 }, 372}; 373 374struct pmx_dev spear320_pmx_i2c1 = { 375 .name = "i2c1", 376 .modes = pmx_i2c1_modes, 377 .mode_count = ARRAY_SIZE(pmx_i2c1_modes), 378 .enb_on_reset = 1, 379}; 380 381/* pmx driver structure */ 382static struct pmx_driver pmx_driver = { 383 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007}, 384 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, 385}; 386 387/* spear3xx shared irq */ 388static struct shirq_dev_config shirq_ras1_config[] = { 389 { 390 .virq = SPEAR320_VIRQ_EMI, 391 .status_mask = SPEAR320_EMI_IRQ_MASK, 392 .clear_mask = SPEAR320_EMI_IRQ_MASK, 393 }, { 394 .virq = SPEAR320_VIRQ_CLCD, 395 .status_mask = SPEAR320_CLCD_IRQ_MASK, 396 .clear_mask = SPEAR320_CLCD_IRQ_MASK, 397 }, { 398 .virq = SPEAR320_VIRQ_SPP, 399 .status_mask = SPEAR320_SPP_IRQ_MASK, 400 .clear_mask = SPEAR320_SPP_IRQ_MASK, 401 }, 402}; 403 404static struct spear_shirq shirq_ras1 = { 405 .irq = SPEAR3XX_IRQ_GEN_RAS_1, 406 .dev_config = shirq_ras1_config, 407 .dev_count = ARRAY_SIZE(shirq_ras1_config), 408 .regs = { 409 .enb_reg = -1, 410 .status_reg = SPEAR320_INT_STS_MASK_REG, 411 .status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK, 412 .clear_reg = SPEAR320_INT_CLR_MASK_REG, 413 .reset_to_clear = 1, 414 }, 415}; 416 417static struct shirq_dev_config shirq_ras3_config[] = { 418 { 419 .virq = SPEAR320_VIRQ_PLGPIO, 420 .enb_mask = SPEAR320_GPIO_IRQ_MASK, 421 .status_mask = SPEAR320_GPIO_IRQ_MASK, 422 .clear_mask = SPEAR320_GPIO_IRQ_MASK, 423 }, { 424 .virq = SPEAR320_VIRQ_I2S_PLAY, 425 .enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK, 426 .status_mask = SPEAR320_I2S_PLAY_IRQ_MASK, 427 .clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK, 428 }, { 429 .virq = SPEAR320_VIRQ_I2S_REC, 430 .enb_mask = SPEAR320_I2S_REC_IRQ_MASK, 431 .status_mask = SPEAR320_I2S_REC_IRQ_MASK, 432 .clear_mask = SPEAR320_I2S_REC_IRQ_MASK, 433 }, 434}; 435 436static struct spear_shirq shirq_ras3 = { 437 .irq = SPEAR3XX_IRQ_GEN_RAS_3, 438 .dev_config = shirq_ras3_config, 439 .dev_count = ARRAY_SIZE(shirq_ras3_config), 440 .regs = { 441 .enb_reg = SPEAR320_INT_ENB_MASK_REG, 442 .reset_to_enb = 1, 443 .status_reg = SPEAR320_INT_STS_MASK_REG, 444 .status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK, 445 .clear_reg = SPEAR320_INT_CLR_MASK_REG, 446 .reset_to_clear = 1, 447 }, 448}; 449 450static struct shirq_dev_config shirq_intrcomm_ras_config[] = { 451 { 452 .virq = SPEAR320_VIRQ_CANU, 453 .status_mask = SPEAR320_CAN_U_IRQ_MASK, 454 .clear_mask = SPEAR320_CAN_U_IRQ_MASK, 455 }, { 456 .virq = SPEAR320_VIRQ_CANL, 457 .status_mask = SPEAR320_CAN_L_IRQ_MASK, 458 .clear_mask = SPEAR320_CAN_L_IRQ_MASK, 459 }, { 460 .virq = SPEAR320_VIRQ_UART1, 461 .status_mask = SPEAR320_UART1_IRQ_MASK, 462 .clear_mask = SPEAR320_UART1_IRQ_MASK, 463 }, { 464 .virq = SPEAR320_VIRQ_UART2, 465 .status_mask = SPEAR320_UART2_IRQ_MASK, 466 .clear_mask = SPEAR320_UART2_IRQ_MASK, 467 }, { 468 .virq = SPEAR320_VIRQ_SSP1, 469 .status_mask = SPEAR320_SSP1_IRQ_MASK, 470 .clear_mask = SPEAR320_SSP1_IRQ_MASK, 471 }, { 472 .virq = SPEAR320_VIRQ_SSP2, 473 .status_mask = SPEAR320_SSP2_IRQ_MASK, 474 .clear_mask = SPEAR320_SSP2_IRQ_MASK, 475 }, { 476 .virq = SPEAR320_VIRQ_SMII0, 477 .status_mask = SPEAR320_SMII0_IRQ_MASK, 478 .clear_mask = SPEAR320_SMII0_IRQ_MASK, 479 }, { 480 .virq = SPEAR320_VIRQ_MII1_SMII1, 481 .status_mask = SPEAR320_MII1_SMII1_IRQ_MASK, 482 .clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK, 483 }, { 484 .virq = SPEAR320_VIRQ_WAKEUP_SMII0, 485 .status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK, 486 .clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK, 487 }, { 488 .virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1, 489 .status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK, 490 .clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK, 491 }, { 492 .virq = SPEAR320_VIRQ_I2C1, 493 .status_mask = SPEAR320_I2C1_IRQ_MASK, 494 .clear_mask = SPEAR320_I2C1_IRQ_MASK, 495 }, 496}; 497 498static struct spear_shirq shirq_intrcomm_ras = { 499 .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM, 500 .dev_config = shirq_intrcomm_ras_config, 501 .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config), 502 .regs = { 503 .enb_reg = -1, 504 .status_reg = SPEAR320_INT_STS_MASK_REG, 505 .status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK, 506 .clear_reg = SPEAR320_INT_CLR_MASK_REG, 507 .reset_to_clear = 1, 508 }, 509}; 510 511/* Add spear320 specific devices here */ 512 513/* spear320 routines */ 514void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, 515 u8 pmx_dev_count) 516{ 517 void __iomem *base; 518 int ret = 0; 519 520 /* call spear3xx family common init function */ 521 spear3xx_init(); 522 523 /* shared irq registration */ 524 base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K); 525 if (base) { 526 /* shirq 1 */ 527 shirq_ras1.regs.base = base; 528 ret = spear_shirq_register(&shirq_ras1); 529 if (ret) 530 printk(KERN_ERR "Error registering Shared IRQ 1\n"); 531 532 /* shirq 3 */ 533 shirq_ras3.regs.base = base; 534 ret = spear_shirq_register(&shirq_ras3); 535 if (ret) 536 printk(KERN_ERR "Error registering Shared IRQ 3\n"); 537 538 /* shirq 4 */ 539 shirq_intrcomm_ras.regs.base = base; 540 ret = spear_shirq_register(&shirq_intrcomm_ras); 541 if (ret) 542 printk(KERN_ERR "Error registering Shared IRQ 4\n"); 543 } 544 545 /* pmx initialization */ 546 pmx_driver.base = base; 547 pmx_driver.mode = pmx_mode; 548 pmx_driver.devs = pmx_devs; 549 pmx_driver.devs_count = pmx_dev_count; 550 551 ret = pmx_register(&pmx_driver); 552 if (ret) 553 printk(KERN_ERR "padmux: registration failed. err no: %d\n", 554 ret); 555} 556