1/*
2 * bfin_dma.h - Blackfin DMA defines/structures/etc...
3 *
4 * Copyright 2004-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __ASM_BFIN_DMA_H__
10#define __ASM_BFIN_DMA_H__
11
12#include <linux/types.h>
13
14/* DMA_CONFIG Masks */
15#define DMAEN			0x0001	/* DMA Channel Enable */
16#define WNR				0x0002	/* Channel Direction (W/R*) */
17#define WDSIZE_8		0x0000	/* Transfer Word Size = 8 */
18#define WDSIZE_16		0x0004	/* Transfer Word Size = 16 */
19#define WDSIZE_32		0x0008	/* Transfer Word Size = 32 */
20#define DMA2D			0x0010	/* DMA Mode (2D/1D*) */
21#define RESTART			0x0020	/* DMA Buffer Clear */
22#define DI_SEL			0x0040	/* Data Interrupt Timing Select */
23#define DI_EN			0x0080	/* Data Interrupt Enable */
24#define NDSIZE_0		0x0000	/* Next Descriptor Size = 0 (Stop/Autobuffer) */
25#define NDSIZE_1		0x0100	/* Next Descriptor Size = 1 */
26#define NDSIZE_2		0x0200	/* Next Descriptor Size = 2 */
27#define NDSIZE_3		0x0300	/* Next Descriptor Size = 3 */
28#define NDSIZE_4		0x0400	/* Next Descriptor Size = 4 */
29#define NDSIZE_5		0x0500	/* Next Descriptor Size = 5 */
30#define NDSIZE_6		0x0600	/* Next Descriptor Size = 6 */
31#define NDSIZE_7		0x0700	/* Next Descriptor Size = 7 */
32#define NDSIZE_8		0x0800	/* Next Descriptor Size = 8 */
33#define NDSIZE_9		0x0900	/* Next Descriptor Size = 9 */
34#define NDSIZE			0x0f00	/* Next Descriptor Size */
35#define DMAFLOW			0x7000	/* Flow Control */
36#define DMAFLOW_STOP	0x0000	/* Stop Mode */
37#define DMAFLOW_AUTO	0x1000	/* Autobuffer Mode */
38#define DMAFLOW_ARRAY	0x4000	/* Descriptor Array Mode */
39#define DMAFLOW_SMALL	0x6000	/* Small Model Descriptor List Mode */
40#define DMAFLOW_LARGE	0x7000	/* Large Model Descriptor List Mode */
41
42/* DMA_IRQ_STATUS Masks */
43#define DMA_DONE		0x0001	/* DMA Completion Interrupt Status */
44#define DMA_ERR			0x0002	/* DMA Error Interrupt Status */
45#define DFETCH			0x0004	/* DMA Descriptor Fetch Indicator */
46#define DMA_RUN			0x0008	/* DMA Channel Running Indicator */
47
48/*
49 * All Blackfin system MMRs are padded to 32bits even if the register
50 * itself is only 16bits.  So use a helper macro to streamline this.
51 */
52#define __BFP(m) u16 m; u16 __pad_##m
53
54/*
55 * bfin dma registers layout
56 */
57struct bfin_dma_regs {
58	u32 next_desc_ptr;
59	u32 start_addr;
60	__BFP(config);
61	u32 __pad0;
62	__BFP(x_count);
63	__BFP(x_modify);
64	__BFP(y_count);
65	__BFP(y_modify);
66	u32 curr_desc_ptr;
67	u32 curr_addr;
68	__BFP(irq_status);
69	__BFP(peripheral_map);
70	__BFP(curr_x_count);
71	u32 __pad1;
72	__BFP(curr_y_count);
73	u32 __pad2;
74};
75
76/*
77 * bfin handshake mdma registers layout
78 */
79struct bfin_hmdma_regs {
80	__BFP(control);
81	__BFP(ecinit);
82	__BFP(bcinit);
83	__BFP(ecurgent);
84	__BFP(ecoverflow);
85	__BFP(ecount);
86	__BFP(bcount);
87};
88
89#undef __BFP
90
91#endif
92