1/*
2 * Copyright (C) 2003, Axis Communications AB.
3 */
4
5#include <asm/irq.h>
6#include <linux/irq.h>
7#include <linux/interrupt.h>
8#include <linux/smp.h>
9#include <linux/kernel.h>
10#include <linux/errno.h>
11#include <linux/init.h>
12#include <linux/profile.h>
13#include <linux/proc_fs.h>
14#include <linux/seq_file.h>
15#include <linux/threads.h>
16#include <linux/spinlock.h>
17#include <linux/kernel_stat.h>
18#include <hwregs/reg_map.h>
19#include <hwregs/reg_rdwr.h>
20#include <hwregs/intr_vect.h>
21#include <hwregs/intr_vect_defs.h>
22
23#define CPU_FIXED -1
24
25/* IRQ masks (refer to comment for crisv32_do_multiple) */
26#if TIMER0_INTR_VECT - FIRST_IRQ < 32
27#define TIMER_MASK (1 << (TIMER0_INTR_VECT - FIRST_IRQ))
28#undef TIMER_VECT1
29#else
30#define TIMER_MASK (1 << (TIMER0_INTR_VECT - FIRST_IRQ - 32))
31#define TIMER_VECT1
32#endif
33#ifdef CONFIG_ETRAX_KGDB
34#if defined(CONFIG_ETRAX_KGDB_PORT0)
35#define IGNOREMASK (1 << (SER0_INTR_VECT - FIRST_IRQ))
36#elif defined(CONFIG_ETRAX_KGDB_PORT1)
37#define IGNOREMASK (1 << (SER1_INTR_VECT - FIRST_IRQ))
38#elif defined(CONFIG_ETRAX_KGB_PORT2)
39#define IGNOREMASK (1 << (SER2_INTR_VECT - FIRST_IRQ))
40#elif defined(CONFIG_ETRAX_KGDB_PORT3)
41#define IGNOREMASK (1 << (SER3_INTR_VECT - FIRST_IRQ))
42#endif
43#endif
44
45DEFINE_SPINLOCK(irq_lock);
46
47struct cris_irq_allocation
48{
49  int cpu; /* The CPU to which the IRQ is currently allocated. */
50  cpumask_t mask; /* The CPUs to which the IRQ may be allocated. */
51};
52
53struct cris_irq_allocation irq_allocations[NR_REAL_IRQS] =
54  { [0 ... NR_REAL_IRQS - 1] = {0, CPU_MASK_ALL} };
55
56static unsigned long irq_regs[NR_CPUS] =
57{
58  regi_irq,
59#ifdef CONFIG_SMP
60  regi_irq2,
61#endif
62};
63
64#if NR_REAL_IRQS > 32
65#define NBR_REGS 2
66#else
67#define NBR_REGS 1
68#endif
69
70unsigned long cpu_irq_counters[NR_CPUS];
71unsigned long irq_counters[NR_REAL_IRQS];
72
73/* From irq.c. */
74extern void weird_irq(void);
75
76/* From entry.S. */
77extern void system_call(void);
78extern void nmi_interrupt(void);
79extern void multiple_interrupt(void);
80extern void gdb_handle_exception(void);
81extern void i_mmu_refill(void);
82extern void i_mmu_invalid(void);
83extern void i_mmu_access(void);
84extern void i_mmu_execute(void);
85extern void d_mmu_refill(void);
86extern void d_mmu_invalid(void);
87extern void d_mmu_access(void);
88extern void d_mmu_write(void);
89
90/* From kgdb.c. */
91extern void kgdb_init(void);
92extern void breakpoint(void);
93
94/* From traps.c.  */
95extern void breakh_BUG(void);
96
97/*
98 * Build the IRQ handler stubs using macros from irq.h.
99 */
100#ifdef CONFIG_CRIS_MACH_ARTPEC3
101BUILD_TIMER_IRQ(0x31, 0)
102#else
103BUILD_IRQ(0x31)
104#endif
105BUILD_IRQ(0x32)
106BUILD_IRQ(0x33)
107BUILD_IRQ(0x34)
108BUILD_IRQ(0x35)
109BUILD_IRQ(0x36)
110BUILD_IRQ(0x37)
111BUILD_IRQ(0x38)
112BUILD_IRQ(0x39)
113BUILD_IRQ(0x3a)
114BUILD_IRQ(0x3b)
115BUILD_IRQ(0x3c)
116BUILD_IRQ(0x3d)
117BUILD_IRQ(0x3e)
118BUILD_IRQ(0x3f)
119BUILD_IRQ(0x40)
120BUILD_IRQ(0x41)
121BUILD_IRQ(0x42)
122BUILD_IRQ(0x43)
123BUILD_IRQ(0x44)
124BUILD_IRQ(0x45)
125BUILD_IRQ(0x46)
126BUILD_IRQ(0x47)
127BUILD_IRQ(0x48)
128BUILD_IRQ(0x49)
129BUILD_IRQ(0x4a)
130#ifdef CONFIG_ETRAXFS
131BUILD_TIMER_IRQ(0x4b, 0)
132#else
133BUILD_IRQ(0x4b)
134#endif
135BUILD_IRQ(0x4c)
136BUILD_IRQ(0x4d)
137BUILD_IRQ(0x4e)
138BUILD_IRQ(0x4f)
139BUILD_IRQ(0x50)
140#if MACH_IRQS > 32
141BUILD_IRQ(0x51)
142BUILD_IRQ(0x52)
143BUILD_IRQ(0x53)
144BUILD_IRQ(0x54)
145BUILD_IRQ(0x55)
146BUILD_IRQ(0x56)
147BUILD_IRQ(0x57)
148BUILD_IRQ(0x58)
149BUILD_IRQ(0x59)
150BUILD_IRQ(0x5a)
151BUILD_IRQ(0x5b)
152BUILD_IRQ(0x5c)
153BUILD_IRQ(0x5d)
154BUILD_IRQ(0x5e)
155BUILD_IRQ(0x5f)
156BUILD_IRQ(0x60)
157BUILD_IRQ(0x61)
158BUILD_IRQ(0x62)
159BUILD_IRQ(0x63)
160BUILD_IRQ(0x64)
161BUILD_IRQ(0x65)
162BUILD_IRQ(0x66)
163BUILD_IRQ(0x67)
164BUILD_IRQ(0x68)
165BUILD_IRQ(0x69)
166BUILD_IRQ(0x6a)
167BUILD_IRQ(0x6b)
168BUILD_IRQ(0x6c)
169BUILD_IRQ(0x6d)
170BUILD_IRQ(0x6e)
171BUILD_IRQ(0x6f)
172BUILD_IRQ(0x70)
173#endif
174
175/* Pointers to the low-level handlers. */
176static void (*interrupt[MACH_IRQS])(void) = {
177	IRQ0x31_interrupt, IRQ0x32_interrupt, IRQ0x33_interrupt,
178	IRQ0x34_interrupt, IRQ0x35_interrupt, IRQ0x36_interrupt,
179	IRQ0x37_interrupt, IRQ0x38_interrupt, IRQ0x39_interrupt,
180	IRQ0x3a_interrupt, IRQ0x3b_interrupt, IRQ0x3c_interrupt,
181	IRQ0x3d_interrupt, IRQ0x3e_interrupt, IRQ0x3f_interrupt,
182	IRQ0x40_interrupt, IRQ0x41_interrupt, IRQ0x42_interrupt,
183	IRQ0x43_interrupt, IRQ0x44_interrupt, IRQ0x45_interrupt,
184	IRQ0x46_interrupt, IRQ0x47_interrupt, IRQ0x48_interrupt,
185	IRQ0x49_interrupt, IRQ0x4a_interrupt, IRQ0x4b_interrupt,
186	IRQ0x4c_interrupt, IRQ0x4d_interrupt, IRQ0x4e_interrupt,
187	IRQ0x4f_interrupt, IRQ0x50_interrupt,
188#if MACH_IRQS > 32
189	IRQ0x51_interrupt, IRQ0x52_interrupt, IRQ0x53_interrupt,
190	IRQ0x54_interrupt, IRQ0x55_interrupt, IRQ0x56_interrupt,
191	IRQ0x57_interrupt, IRQ0x58_interrupt, IRQ0x59_interrupt,
192	IRQ0x5a_interrupt, IRQ0x5b_interrupt, IRQ0x5c_interrupt,
193	IRQ0x5d_interrupt, IRQ0x5e_interrupt, IRQ0x5f_interrupt,
194	IRQ0x60_interrupt, IRQ0x61_interrupt, IRQ0x62_interrupt,
195	IRQ0x63_interrupt, IRQ0x64_interrupt, IRQ0x65_interrupt,
196	IRQ0x66_interrupt, IRQ0x67_interrupt, IRQ0x68_interrupt,
197	IRQ0x69_interrupt, IRQ0x6a_interrupt, IRQ0x6b_interrupt,
198	IRQ0x6c_interrupt, IRQ0x6d_interrupt, IRQ0x6e_interrupt,
199	IRQ0x6f_interrupt, IRQ0x70_interrupt,
200#endif
201};
202
203void
204block_irq(int irq, int cpu)
205{
206	int intr_mask;
207        unsigned long flags;
208
209	spin_lock_irqsave(&irq_lock, flags);
210	/* Remember, 1 let thru, 0 block. */
211	if (irq - FIRST_IRQ < 32) {
212		intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
213			rw_mask, 0);
214		intr_mask &= ~(1 << (irq - FIRST_IRQ));
215		REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
216			0, intr_mask);
217	} else {
218		intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
219			rw_mask, 1);
220		intr_mask &= ~(1 << (irq - FIRST_IRQ - 32));
221		REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
222			1, intr_mask);
223	}
224        spin_unlock_irqrestore(&irq_lock, flags);
225}
226
227void
228unblock_irq(int irq, int cpu)
229{
230	int intr_mask;
231        unsigned long flags;
232
233        spin_lock_irqsave(&irq_lock, flags);
234	/* Remember, 1 let thru, 0 block. */
235	if (irq - FIRST_IRQ < 32) {
236		intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
237			rw_mask, 0);
238		intr_mask |= (1 << (irq - FIRST_IRQ));
239		REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
240			0, intr_mask);
241	} else {
242		intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
243			rw_mask, 1);
244		intr_mask |= (1 << (irq - FIRST_IRQ - 32));
245		REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
246			1, intr_mask);
247	}
248        spin_unlock_irqrestore(&irq_lock, flags);
249}
250
251/* Find out which CPU the irq should be allocated to. */
252static int irq_cpu(int irq)
253{
254	int cpu;
255        unsigned long flags;
256
257        spin_lock_irqsave(&irq_lock, flags);
258        cpu = irq_allocations[irq - FIRST_IRQ].cpu;
259
260	/* Fixed interrupts stay on the local CPU. */
261	if (cpu == CPU_FIXED)
262        {
263		spin_unlock_irqrestore(&irq_lock, flags);
264		return smp_processor_id();
265        }
266
267
268	/* Let the interrupt stay if possible */
269	if (cpumask_test_cpu(cpu, &irq_allocations[irq - FIRST_IRQ].mask))
270		goto out;
271
272	/* IRQ must be moved to another CPU. */
273	cpu = cpumask_first(&irq_allocations[irq - FIRST_IRQ].mask);
274	irq_allocations[irq - FIRST_IRQ].cpu = cpu;
275out:
276	spin_unlock_irqrestore(&irq_lock, flags);
277	return cpu;
278}
279
280void crisv32_mask_irq(int irq)
281{
282	int cpu;
283
284	for (cpu = 0; cpu < NR_CPUS; cpu++)
285		block_irq(irq, cpu);
286}
287
288void crisv32_unmask_irq(int irq)
289{
290	unblock_irq(irq, irq_cpu(irq));
291}
292
293
294static void enable_crisv32_irq(struct irq_data *data)
295{
296	crisv32_unmask_irq(data->irq);
297}
298
299static void disable_crisv32_irq(struct irq_data *data)
300{
301	crisv32_mask_irq(data->irq);
302}
303
304static int set_affinity_crisv32_irq(struct irq_data *data,
305				    const struct cpumask *dest, bool force)
306{
307	unsigned long flags;
308
309	spin_lock_irqsave(&irq_lock, flags);
310	irq_allocations[data->irq - FIRST_IRQ].mask = *dest;
311	spin_unlock_irqrestore(&irq_lock, flags);
312	return 0;
313}
314
315static struct irq_chip crisv32_irq_type = {
316	.name			= "CRISv32",
317	.irq_shutdown		= disable_crisv32_irq,
318	.irq_enable		= enable_crisv32_irq,
319	.irq_disable		= disable_crisv32_irq,
320	.irq_set_affinity	= set_affinity_crisv32_irq,
321};
322
323void
324set_exception_vector(int n, irqvectptr addr)
325{
326	etrax_irv->v[n] = (irqvectptr) addr;
327}
328
329extern void do_IRQ(int irq, struct pt_regs * regs);
330
331void
332crisv32_do_IRQ(int irq, int block, struct pt_regs* regs)
333{
334	/* Interrupts that may not be moved to another CPU and
335         * are IRQF_DISABLED may skip blocking. This is currently
336         * only valid for the timer IRQ and the IPI and is used
337         * for the timer interrupt to avoid watchdog starvation.
338         */
339	if (!block) {
340		do_IRQ(irq, regs);
341		return;
342	}
343
344	block_irq(irq, smp_processor_id());
345	do_IRQ(irq, regs);
346
347	unblock_irq(irq, irq_cpu(irq));
348}
349
350/* If multiple interrupts occur simultaneously we get a multiple
351 * interrupt from the CPU and software has to sort out which
352 * interrupts that happened. There are two special cases here:
353 *
354 * 1. Timer interrupts may never be blocked because of the
355 *    watchdog (refer to comment in include/asr/arch/irq.h)
356 * 2. GDB serial port IRQs are unhandled here and will be handled
357 *    as a single IRQ when it strikes again because the GDB
358 *    stubb wants to save the registers in its own fashion.
359 */
360void
361crisv32_do_multiple(struct pt_regs* regs)
362{
363	int cpu;
364	int mask;
365	int masked[NBR_REGS];
366	int bit;
367	int i;
368
369	cpu = smp_processor_id();
370
371	/* An extra irq_enter here to prevent softIRQs to run after
372         * each do_IRQ. This will decrease the interrupt latency.
373	 */
374	irq_enter();
375
376	for (i = 0; i < NBR_REGS; i++) {
377		/* Get which IRQs that happened. */
378		masked[i] = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
379			r_masked_vect, i);
380
381		/* Calculate new IRQ mask with these IRQs disabled. */
382		mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i);
383		mask &= ~masked[i];
384
385	/* Timer IRQ is never masked */
386#ifdef TIMER_VECT1
387		if ((i == 1) && (masked[0] & TIMER_MASK))
388			mask |= TIMER_MASK;
389#else
390		if ((i == 0) && (masked[0] & TIMER_MASK))
391			mask |= TIMER_MASK;
392#endif
393		/* Block all the IRQs */
394		REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i, mask);
395
396	/* Check for timer IRQ and handle it special. */
397#ifdef TIMER_VECT1
398		if ((i == 1) && (masked[i] & TIMER_MASK)) {
399			masked[i] &= ~TIMER_MASK;
400			do_IRQ(TIMER0_INTR_VECT, regs);
401		}
402#else
403		if ((i == 0) && (masked[i] & TIMER_MASK)) {
404			 masked[i] &= ~TIMER_MASK;
405			 do_IRQ(TIMER0_INTR_VECT, regs);
406		}
407#endif
408	}
409
410#ifdef IGNORE_MASK
411	/* Remove IRQs that can't be handled as multiple. */
412	masked[0] &= ~IGNORE_MASK;
413#endif
414
415	/* Handle the rest of the IRQs. */
416	for (i = 0; i < NBR_REGS; i++) {
417		for (bit = 0; bit < 32; bit++) {
418			if (masked[i] & (1 << bit))
419				do_IRQ(bit + FIRST_IRQ + i*32, regs);
420		}
421	}
422
423	/* Unblock all the IRQs. */
424	for (i = 0; i < NBR_REGS; i++) {
425		mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i);
426		mask |= masked[i];
427		REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i, mask);
428	}
429
430	/* This irq_exit() will trigger the soft IRQs. */
431	irq_exit();
432}
433
434/*
435 * This is called by start_kernel. It fixes the IRQ masks and setup the
436 * interrupt vector table to point to bad_interrupt pointers.
437 */
438void __init
439init_IRQ(void)
440{
441	int i;
442	int j;
443	reg_intr_vect_rw_mask vect_mask = {0};
444
445	/* Clear all interrupts masks. */
446	for (i = 0; i < NBR_REGS; i++)
447		REG_WR_VECT(intr_vect, regi_irq, rw_mask, i, vect_mask);
448
449	for (i = 0; i < 256; i++)
450		etrax_irv->v[i] = weird_irq;
451
452	/* Point all IRQ's to bad handlers. */
453	for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) {
454		irq_set_chip_and_handler(j, &crisv32_irq_type,
455					 handle_simple_irq);
456		set_exception_vector(i, interrupt[j]);
457	}
458
459	/* Mark Timer and IPI IRQs as CPU local */
460	irq_allocations[TIMER0_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;
461	irq_set_status_flags(TIMER0_INTR_VECT, IRQ_PER_CPU);
462	irq_allocations[IPI_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;
463	irq_set_status_flags(IPI_INTR_VECT, IRQ_PER_CPU);
464
465	set_exception_vector(0x00, nmi_interrupt);
466	set_exception_vector(0x30, multiple_interrupt);
467
468	/* Set up handler for various MMU bus faults. */
469	set_exception_vector(0x04, i_mmu_refill);
470	set_exception_vector(0x05, i_mmu_invalid);
471	set_exception_vector(0x06, i_mmu_access);
472	set_exception_vector(0x07, i_mmu_execute);
473	set_exception_vector(0x08, d_mmu_refill);
474	set_exception_vector(0x09, d_mmu_invalid);
475	set_exception_vector(0x0a, d_mmu_access);
476	set_exception_vector(0x0b, d_mmu_write);
477
478#ifdef CONFIG_BUG
479	/* Break 14 handler, used to implement cheap BUG().  */
480	set_exception_vector(0x1e, breakh_BUG);
481#endif
482
483	/* The system-call trap is reached by "break 13". */
484	set_exception_vector(0x1d, system_call);
485
486	/* Exception handlers for debugging, both user-mode and kernel-mode. */
487
488	/* Break 8. */
489	set_exception_vector(0x18, gdb_handle_exception);
490	/* Hardware single step. */
491	set_exception_vector(0x3, gdb_handle_exception);
492	/* Hardware breakpoint. */
493	set_exception_vector(0xc, gdb_handle_exception);
494
495#ifdef CONFIG_ETRAX_KGDB
496	kgdb_init();
497	/* Everything is set up; now trap the kernel. */
498	breakpoint();
499#endif
500}
501
502