1#ifndef _ASM_M32R_M32R_H_ 2#define _ASM_M32R_M32R_H_ 3 4/* 5 * Renesas M32R processor 6 * 7 * Copyright (C) 2003, 2004 Renesas Technology Corp. 8 */ 9 10 11/* Chip type */ 12#if defined(CONFIG_CHIP_XNUX_MP) || defined(CONFIG_CHIP_XNUX2_MP) 13#include <asm/m32r_mp_fpga.h> 14#elif defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \ 15 || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \ 16 || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104) 17#include <asm/m32102.h> 18#endif 19 20/* Platform type */ 21#if defined(CONFIG_PLAT_M32700UT) 22#include <asm/m32700ut/m32700ut_pld.h> 23#include <asm/m32700ut/m32700ut_lan.h> 24#include <asm/m32700ut/m32700ut_lcd.h> 25/* for ei_handler:linux/arch/m32r/kernel/entry.S */ 26#define M32R_INT1ICU_ISTS PLD_ICUISTS 27#define M32R_INT1ICU_IRQ_BASE M32700UT_PLD_IRQ_BASE 28#define M32R_INT0ICU_ISTS M32700UT_LAN_ICUISTS 29#define M32R_INT0ICU_IRQ_BASE M32700UT_LAN_PLD_IRQ_BASE 30#define M32R_INT2ICU_ISTS M32700UT_LCD_ICUISTS 31#define M32R_INT2ICU_IRQ_BASE M32700UT_LCD_PLD_IRQ_BASE 32#endif /* CONFIG_PLAT_M32700UT */ 33 34#if defined(CONFIG_PLAT_OPSPUT) 35#include <asm/opsput/opsput_pld.h> 36#include <asm/opsput/opsput_lan.h> 37#include <asm/opsput/opsput_lcd.h> 38/* for ei_handler:linux/arch/m32r/kernel/entry.S */ 39#define M32R_INT1ICU_ISTS PLD_ICUISTS 40#define M32R_INT1ICU_IRQ_BASE OPSPUT_PLD_IRQ_BASE 41#define M32R_INT0ICU_ISTS OPSPUT_LAN_ICUISTS 42#define M32R_INT0ICU_IRQ_BASE OPSPUT_LAN_PLD_IRQ_BASE 43#define M32R_INT2ICU_ISTS OPSPUT_LCD_ICUISTS 44#define M32R_INT2ICU_IRQ_BASE OPSPUT_LCD_PLD_IRQ_BASE 45#endif /* CONFIG_PLAT_OPSPUT */ 46 47#if defined(CONFIG_PLAT_MAPPI2) 48#include <asm/mappi2/mappi2_pld.h> 49#endif /* CONFIG_PLAT_MAPPI2 */ 50 51#if defined(CONFIG_PLAT_MAPPI3) 52#include <asm/mappi3/mappi3_pld.h> 53#endif /* CONFIG_PLAT_MAPPI3 */ 54 55#if defined(CONFIG_PLAT_USRV) 56#include <asm/m32700ut/m32700ut_pld.h> 57/* for ei_handler:linux/arch/m32r/kernel/entry.S */ 58#define M32R_INT1ICU_ISTS PLD_ICUISTS 59#define M32R_INT1ICU_IRQ_BASE M32700UT_PLD_IRQ_BASE 60#endif 61 62#if defined(CONFIG_PLAT_M32104UT) 63#include <asm/m32104ut/m32104ut_pld.h> 64/* for ei_handler:linux/arch/m32r/kernel/entry.S */ 65#define M32R_INT1ICU_ISTS PLD_ICUISTS 66#define M32R_INT1ICU_IRQ_BASE M32104UT_PLD_IRQ_BASE 67#endif /* CONFIG_PLAT_M32104 */ 68 69/* 70 * M32R Register 71 */ 72 73/* 74 * MMU Register 75 */ 76 77#define MMU_REG_BASE (0xffff0000) 78#define ITLB_BASE (0xfe000000) 79#define DTLB_BASE (0xfe000800) 80 81#define NR_TLB_ENTRIES CONFIG_TLB_ENTRIES 82 83#define MATM MMU_REG_BASE /* MMU Address Translation Mode 84 Register */ 85#define MPSZ (0x04 + MMU_REG_BASE) /* MMU Page Size Designation Register */ 86#define MASID (0x08 + MMU_REG_BASE) /* MMU Address Space ID Register */ 87#define MESTS (0x0c + MMU_REG_BASE) /* MMU Exception Status Register */ 88#define MDEVA (0x10 + MMU_REG_BASE) /* MMU Operand Exception Virtual 89 Address Register */ 90#define MDEVP (0x14 + MMU_REG_BASE) /* MMU Operand Exception Virtual Page 91 Number Register */ 92#define MPTB (0x18 + MMU_REG_BASE) /* MMU Page Table Base Register */ 93#define MSVA (0x20 + MMU_REG_BASE) /* MMU Search Virtual Address 94 Register */ 95#define MTOP (0x24 + MMU_REG_BASE) /* MMU TLB Operation Register */ 96#define MIDXI (0x28 + MMU_REG_BASE) /* MMU Index Register for 97 Instruciton */ 98#define MIDXD (0x2c + MMU_REG_BASE) /* MMU Index Register for Operand */ 99 100#define MATM_offset (MATM - MMU_REG_BASE) 101#define MPSZ_offset (MPSZ - MMU_REG_BASE) 102#define MASID_offset (MASID - MMU_REG_BASE) 103#define MESTS_offset (MESTS - MMU_REG_BASE) 104#define MDEVA_offset (MDEVA - MMU_REG_BASE) 105#define MDEVP_offset (MDEVP - MMU_REG_BASE) 106#define MPTB_offset (MPTB - MMU_REG_BASE) 107#define MSVA_offset (MSVA - MMU_REG_BASE) 108#define MTOP_offset (MTOP - MMU_REG_BASE) 109#define MIDXI_offset (MIDXI - MMU_REG_BASE) 110#define MIDXD_offset (MIDXD - MMU_REG_BASE) 111 112#define MESTS_IT (1 << 0) /* Instruction TLB miss */ 113#define MESTS_IA (1 << 1) /* Instruction Access Exception */ 114#define MESTS_DT (1 << 4) /* Operand TLB miss */ 115#define MESTS_DA (1 << 5) /* Operand Access Exception */ 116#define MESTS_DRW (1 << 6) /* Operand Write Exception Flag */ 117 118/* 119 * PSW (Processor Status Word) 120 */ 121 122/* PSW bit */ 123#define M32R_PSW_BIT_SM (7) /* Stack Mode */ 124#define M32R_PSW_BIT_IE (6) /* Interrupt Enable */ 125#define M32R_PSW_BIT_PM (3) /* Processor Mode [0:Supervisor,1:User] */ 126#define M32R_PSW_BIT_C (0) /* Condition */ 127#define M32R_PSW_BIT_BSM (7+8) /* Backup Stack Mode */ 128#define M32R_PSW_BIT_BIE (6+8) /* Backup Interrupt Enable */ 129#define M32R_PSW_BIT_BPM (3+8) /* Backup Processor Mode */ 130#define M32R_PSW_BIT_BC (0+8) /* Backup Condition */ 131 132/* PSW bit map */ 133#define M32R_PSW_SM (1UL<< M32R_PSW_BIT_SM) /* Stack Mode */ 134#define M32R_PSW_IE (1UL<< M32R_PSW_BIT_IE) /* Interrupt Enable */ 135#define M32R_PSW_PM (1UL<< M32R_PSW_BIT_PM) /* Processor Mode */ 136#define M32R_PSW_C (1UL<< M32R_PSW_BIT_C) /* Condition */ 137#define M32R_PSW_BSM (1UL<< M32R_PSW_BIT_BSM) /* Backup Stack Mode */ 138#define M32R_PSW_BIE (1UL<< M32R_PSW_BIT_BIE) /* Backup Interrupt Enable */ 139#define M32R_PSW_BPM (1UL<< M32R_PSW_BIT_BPM) /* Backup Processor Mode */ 140#define M32R_PSW_BC (1UL<< M32R_PSW_BIT_BC) /* Backup Condition */ 141 142/* 143 * Direct address to SFR 144 */ 145 146#include <asm/page.h> 147#ifdef CONFIG_MMU 148#define NONCACHE_OFFSET (__PAGE_OFFSET + 0x20000000) 149#else 150#define NONCACHE_OFFSET __PAGE_OFFSET 151#endif /* CONFIG_MMU */ 152 153#define M32R_ICU_ISTS_ADDR M32R_ICU_ISTS_PORTL+NONCACHE_OFFSET 154#define M32R_ICU_IPICR_ADDR M32R_ICU_IPICR0_PORTL+NONCACHE_OFFSET 155#define M32R_ICU_IMASK_ADDR M32R_ICU_IMASK_PORTL+NONCACHE_OFFSET 156#define M32R_FPGA_CPU_NAME_ADDR M32R_FPGA_CPU_NAME0_PORTL+NONCACHE_OFFSET 157#define M32R_FPGA_MODEL_ID_ADDR M32R_FPGA_MODEL_ID0_PORTL+NONCACHE_OFFSET 158#define M32R_FPGA_VERSION_ADDR M32R_FPGA_VERSION0_PORTL+NONCACHE_OFFSET 159 160#endif /* _ASM_M32R_M32R_H_ */ 161