1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License.  See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 * Copyright (C) 2008 Cavium Networks <support@caviumnetworks.com>
8 */
9#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
10#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
11
12#define R4600_V1_INDEX_ICACHEOP_WAR	0
13#define R4600_V1_HIT_CACHEOP_WAR	0
14#define R4600_V2_HIT_CACHEOP_WAR	0
15#define R5432_CP0_INTERRUPT_WAR		0
16#define BCM1250_M3_WAR			0
17#define SIBYTE_1956_WAR			0
18#define MIPS4K_ICACHE_REFILL_WAR	0
19#define MIPS_CACHE_SYNC_WAR		0
20#define TX49XX_ICACHE_INDEX_INV_WAR	0
21#define RM9000_CDEX_SMP_WAR		0
22#define ICACHE_REFILLS_WORKAROUND_WAR	0
23#define R10000_LLSC_WAR			0
24#define MIPS34K_MISSED_ITLB_WAR		0
25
26#endif /* __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H */
27