1/* 2 * Copyright 2001 MontaVista Software Inc. 3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net 4 * 5 * Copyright (C) 2001 Ralf Baechle 6 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. 7 * Author: Maciej W. Rozycki <macro@mips.com> 8 * 9 * This file define the irq handler for MIPS CPU interrupts. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 */ 16 17/* 18 * Almost all MIPS CPUs define 8 interrupt sources. They are typically 19 * level triggered (i.e., cannot be cleared from CPU; must be cleared from 20 * device). The first two are software interrupts which we don't really 21 * use or support. The last one is usually the CPU timer interrupt if 22 * counter register is present or, for CPUs with an external FPU, by 23 * convention it's the FPU exception interrupt. 24 * 25 * Don't even think about using this on SMP. You have been warned. 26 * 27 * This file exports one global function: 28 * void mips_cpu_irq_init(void); 29 */ 30#include <linux/init.h> 31#include <linux/interrupt.h> 32#include <linux/kernel.h> 33#include <linux/irq.h> 34 35#include <asm/irq_cpu.h> 36#include <asm/mipsregs.h> 37#include <asm/mipsmtregs.h> 38 39static inline void unmask_mips_irq(struct irq_data *d) 40{ 41 set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); 42 irq_enable_hazard(); 43} 44 45static inline void mask_mips_irq(struct irq_data *d) 46{ 47 clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); 48 irq_disable_hazard(); 49} 50 51static struct irq_chip mips_cpu_irq_controller = { 52 .name = "MIPS", 53 .irq_ack = mask_mips_irq, 54 .irq_mask = mask_mips_irq, 55 .irq_mask_ack = mask_mips_irq, 56 .irq_unmask = unmask_mips_irq, 57 .irq_eoi = unmask_mips_irq, 58}; 59 60/* 61 * Basically the same as above but taking care of all the MT stuff 62 */ 63 64static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d) 65{ 66 unsigned int vpflags = dvpe(); 67 68 clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); 69 evpe(vpflags); 70 unmask_mips_irq(d); 71 return 0; 72} 73 74/* 75 * While we ack the interrupt interrupts are disabled and thus we don't need 76 * to deal with concurrency issues. Same for mips_cpu_irq_end. 77 */ 78static void mips_mt_cpu_irq_ack(struct irq_data *d) 79{ 80 unsigned int vpflags = dvpe(); 81 clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); 82 evpe(vpflags); 83 mask_mips_irq(d); 84} 85 86static struct irq_chip mips_mt_cpu_irq_controller = { 87 .name = "MIPS", 88 .irq_startup = mips_mt_cpu_irq_startup, 89 .irq_ack = mips_mt_cpu_irq_ack, 90 .irq_mask = mask_mips_irq, 91 .irq_mask_ack = mips_mt_cpu_irq_ack, 92 .irq_unmask = unmask_mips_irq, 93 .irq_eoi = unmask_mips_irq, 94}; 95 96void __init mips_cpu_irq_init(void) 97{ 98 int irq_base = MIPS_CPU_IRQ_BASE; 99 int i; 100 101 /* Mask interrupts. */ 102 clear_c0_status(ST0_IM); 103 clear_c0_cause(CAUSEF_IP); 104 105 /* Software interrupts are used for MT/CMT IPI */ 106 for (i = irq_base; i < irq_base + 2; i++) 107 irq_set_chip_and_handler(i, cpu_has_mipsmt ? 108 &mips_mt_cpu_irq_controller : 109 &mips_cpu_irq_controller, 110 handle_percpu_irq); 111 112 for (i = irq_base + 2; i < irq_base + 8; i++) 113 irq_set_chip_and_handler(i, &mips_cpu_irq_controller, 114 handle_percpu_irq); 115} 116