smtc.c revision 033890b084adfa367c544864451d7730552ce8bf
1/* Copyright (C) 2004 Mips Technologies, Inc */ 2 3#include <linux/kernel.h> 4#include <linux/sched.h> 5#include <linux/cpumask.h> 6#include <linux/interrupt.h> 7#include <linux/kernel_stat.h> 8#include <linux/module.h> 9 10#include <asm/cpu.h> 11#include <asm/processor.h> 12#include <asm/atomic.h> 13#include <asm/system.h> 14#include <asm/hardirq.h> 15#include <asm/hazards.h> 16#include <asm/irq.h> 17#include <asm/mmu_context.h> 18#include <asm/smp.h> 19#include <asm/mipsregs.h> 20#include <asm/cacheflush.h> 21#include <asm/time.h> 22#include <asm/addrspace.h> 23#include <asm/smtc.h> 24#include <asm/smtc_ipi.h> 25#include <asm/smtc_proc.h> 26 27/* 28 * This file should be built into the kernel only if CONFIG_MIPS_MT_SMTC is set. 29 */ 30 31#define MIPS_CPU_IPI_IRQ 1 32 33#define LOCK_MT_PRA() \ 34 local_irq_save(flags); \ 35 mtflags = dmt() 36 37#define UNLOCK_MT_PRA() \ 38 emt(mtflags); \ 39 local_irq_restore(flags) 40 41#define LOCK_CORE_PRA() \ 42 local_irq_save(flags); \ 43 mtflags = dvpe() 44 45#define UNLOCK_CORE_PRA() \ 46 evpe(mtflags); \ 47 local_irq_restore(flags) 48 49/* 50 * Data structures purely associated with SMTC parallelism 51 */ 52 53 54/* 55 * Table for tracking ASIDs whose lifetime is prolonged. 56 */ 57 58asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS]; 59 60/* 61 * Clock interrupt "latch" buffers, per "CPU" 62 */ 63 64unsigned int ipi_timer_latch[NR_CPUS]; 65 66/* 67 * Number of InterProcessor Interupt (IPI) message buffers to allocate 68 */ 69 70#define IPIBUF_PER_CPU 4 71 72static struct smtc_ipi_q IPIQ[NR_CPUS]; 73static struct smtc_ipi_q freeIPIq; 74 75 76/* Forward declarations */ 77 78void ipi_decode(struct smtc_ipi *); 79static void post_direct_ipi(int cpu, struct smtc_ipi *pipi); 80static void setup_cross_vpe_interrupts(unsigned int nvpe); 81void init_smtc_stats(void); 82 83/* Global SMTC Status */ 84 85unsigned int smtc_status = 0; 86 87/* Boot command line configuration overrides */ 88 89static int vpelimit = 0; 90static int tclimit = 0; 91static int ipibuffers = 0; 92static int nostlb = 0; 93static int asidmask = 0; 94unsigned long smtc_asid_mask = 0xff; 95 96static int __init maxvpes(char *str) 97{ 98 get_option(&str, &vpelimit); 99 return 1; 100} 101 102static int __init maxtcs(char *str) 103{ 104 get_option(&str, &tclimit); 105 return 1; 106} 107 108static int __init ipibufs(char *str) 109{ 110 get_option(&str, &ipibuffers); 111 return 1; 112} 113 114static int __init stlb_disable(char *s) 115{ 116 nostlb = 1; 117 return 1; 118} 119 120static int __init asidmask_set(char *str) 121{ 122 get_option(&str, &asidmask); 123 switch (asidmask) { 124 case 0x1: 125 case 0x3: 126 case 0x7: 127 case 0xf: 128 case 0x1f: 129 case 0x3f: 130 case 0x7f: 131 case 0xff: 132 smtc_asid_mask = (unsigned long)asidmask; 133 break; 134 default: 135 printk("ILLEGAL ASID mask 0x%x from command line\n", asidmask); 136 } 137 return 1; 138} 139 140__setup("maxvpes=", maxvpes); 141__setup("maxtcs=", maxtcs); 142__setup("ipibufs=", ipibufs); 143__setup("nostlb", stlb_disable); 144__setup("asidmask=", asidmask_set); 145 146#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG 147 148static int hang_trig = 0; 149 150static int __init hangtrig_enable(char *s) 151{ 152 hang_trig = 1; 153 return 1; 154} 155 156 157__setup("hangtrig", hangtrig_enable); 158 159#define DEFAULT_BLOCKED_IPI_LIMIT 32 160 161static int timerq_limit = DEFAULT_BLOCKED_IPI_LIMIT; 162 163static int __init tintq(char *str) 164{ 165 get_option(&str, &timerq_limit); 166 return 1; 167} 168 169__setup("tintq=", tintq); 170 171int imstuckcount[2][8]; 172/* vpemask represents IM/IE bits of per-VPE Status registers, low-to-high */ 173int vpemask[2][8] = { 174 {0, 0, 1, 0, 0, 0, 0, 1}, 175 {0, 0, 0, 0, 0, 0, 0, 1} 176}; 177int tcnoprog[NR_CPUS]; 178static atomic_t idle_hook_initialized = {0}; 179static int clock_hang_reported[NR_CPUS]; 180 181#endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */ 182 183/* Initialize shared TLB - the should probably migrate to smtc_setup_cpus() */ 184 185void __init sanitize_tlb_entries(void) 186{ 187 printk("Deprecated sanitize_tlb_entries() invoked\n"); 188} 189 190 191/* 192 * Configure shared TLB - VPC configuration bit must be set by caller 193 */ 194 195static void smtc_configure_tlb(void) 196{ 197 int i,tlbsiz,vpes; 198 unsigned long mvpconf0; 199 unsigned long config1val; 200 201 /* Set up ASID preservation table */ 202 for (vpes=0; vpes<MAX_SMTC_TLBS; vpes++) { 203 for(i = 0; i < MAX_SMTC_ASIDS; i++) { 204 smtc_live_asid[vpes][i] = 0; 205 } 206 } 207 mvpconf0 = read_c0_mvpconf0(); 208 209 if ((vpes = ((mvpconf0 & MVPCONF0_PVPE) 210 >> MVPCONF0_PVPE_SHIFT) + 1) > 1) { 211 /* If we have multiple VPEs, try to share the TLB */ 212 if ((mvpconf0 & MVPCONF0_TLBS) && !nostlb) { 213 /* 214 * If TLB sizing is programmable, shared TLB 215 * size is the total available complement. 216 * Otherwise, we have to take the sum of all 217 * static VPE TLB entries. 218 */ 219 if ((tlbsiz = ((mvpconf0 & MVPCONF0_PTLBE) 220 >> MVPCONF0_PTLBE_SHIFT)) == 0) { 221 /* 222 * If there's more than one VPE, there had better 223 * be more than one TC, because we need one to bind 224 * to each VPE in turn to be able to read 225 * its configuration state! 226 */ 227 settc(1); 228 /* Stop the TC from doing anything foolish */ 229 write_tc_c0_tchalt(TCHALT_H); 230 mips_ihb(); 231 /* No need to un-Halt - that happens later anyway */ 232 for (i=0; i < vpes; i++) { 233 write_tc_c0_tcbind(i); 234 /* 235 * To be 100% sure we're really getting the right 236 * information, we exit the configuration state 237 * and do an IHB after each rebinding. 238 */ 239 write_c0_mvpcontrol( 240 read_c0_mvpcontrol() & ~ MVPCONTROL_VPC ); 241 mips_ihb(); 242 /* 243 * Only count if the MMU Type indicated is TLB 244 */ 245 if (((read_vpe_c0_config() & MIPS_CONF_MT) >> 7) == 1) { 246 config1val = read_vpe_c0_config1(); 247 tlbsiz += ((config1val >> 25) & 0x3f) + 1; 248 } 249 250 /* Put core back in configuration state */ 251 write_c0_mvpcontrol( 252 read_c0_mvpcontrol() | MVPCONTROL_VPC ); 253 mips_ihb(); 254 } 255 } 256 write_c0_mvpcontrol(read_c0_mvpcontrol() | MVPCONTROL_STLB); 257 ehb(); 258 259 /* 260 * Setup kernel data structures to use software total, 261 * rather than read the per-VPE Config1 value. The values 262 * for "CPU 0" gets copied to all the other CPUs as part 263 * of their initialization in smtc_cpu_setup(). 264 */ 265 266 /* MIPS32 limits TLB indices to 64 */ 267 if (tlbsiz > 64) 268 tlbsiz = 64; 269 cpu_data[0].tlbsize = current_cpu_data.tlbsize = tlbsiz; 270 smtc_status |= SMTC_TLB_SHARED; 271 local_flush_tlb_all(); 272 273 printk("TLB of %d entry pairs shared by %d VPEs\n", 274 tlbsiz, vpes); 275 } else { 276 printk("WARNING: TLB Not Sharable on SMTC Boot!\n"); 277 } 278 } 279} 280 281 282/* 283 * Incrementally build the CPU map out of constituent MIPS MT cores, 284 * using the specified available VPEs and TCs. Plaform code needs 285 * to ensure that each MIPS MT core invokes this routine on reset, 286 * one at a time(!). 287 * 288 * This version of the build_cpu_map and prepare_cpus routines assumes 289 * that *all* TCs of a MIPS MT core will be used for Linux, and that 290 * they will be spread across *all* available VPEs (to minimise the 291 * loss of efficiency due to exception service serialization). 292 * An improved version would pick up configuration information and 293 * possibly leave some TCs/VPEs as "slave" processors. 294 * 295 * Use c0_MVPConf0 to find out how many TCs are available, setting up 296 * phys_cpu_present_map and the logical/physical mappings. 297 */ 298 299int __init mipsmt_build_cpu_map(int start_cpu_slot) 300{ 301 int i, ntcs; 302 303 /* 304 * The CPU map isn't actually used for anything at this point, 305 * so it's not clear what else we should do apart from set 306 * everything up so that "logical" = "physical". 307 */ 308 ntcs = ((read_c0_mvpconf0() & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1; 309 for (i=start_cpu_slot; i<NR_CPUS && i<ntcs; i++) { 310 cpu_set(i, phys_cpu_present_map); 311 __cpu_number_map[i] = i; 312 __cpu_logical_map[i] = i; 313 } 314 /* Initialize map of CPUs with FPUs */ 315 cpus_clear(mt_fpu_cpumask); 316 317 /* One of those TC's is the one booting, and not a secondary... */ 318 printk("%i available secondary CPU TC(s)\n", i - 1); 319 320 return i; 321} 322 323/* 324 * Common setup before any secondaries are started 325 * Make sure all CPU's are in a sensible state before we boot any of the 326 * secondaries. 327 * 328 * For MIPS MT "SMTC" operation, we set up all TCs, spread as evenly 329 * as possible across the available VPEs. 330 */ 331 332static void smtc_tc_setup(int vpe, int tc, int cpu) 333{ 334 settc(tc); 335 write_tc_c0_tchalt(TCHALT_H); 336 mips_ihb(); 337 write_tc_c0_tcstatus((read_tc_c0_tcstatus() 338 & ~(TCSTATUS_TKSU | TCSTATUS_DA | TCSTATUS_IXMT)) 339 | TCSTATUS_A); 340 write_tc_c0_tccontext(0); 341 /* Bind tc to vpe */ 342 write_tc_c0_tcbind(vpe); 343 /* In general, all TCs should have the same cpu_data indications */ 344 memcpy(&cpu_data[cpu], &cpu_data[0], sizeof(struct cpuinfo_mips)); 345 /* For 34Kf, start with TC/CPU 0 as sole owner of single FPU context */ 346 if (cpu_data[0].cputype == CPU_34K) 347 cpu_data[cpu].options &= ~MIPS_CPU_FPU; 348 cpu_data[cpu].vpe_id = vpe; 349 cpu_data[cpu].tc_id = tc; 350} 351 352 353void mipsmt_prepare_cpus(void) 354{ 355 int i, vpe, tc, ntc, nvpe, tcpervpe, slop, cpu; 356 unsigned long flags; 357 unsigned long val; 358 int nipi; 359 struct smtc_ipi *pipi; 360 361 /* disable interrupts so we can disable MT */ 362 local_irq_save(flags); 363 /* disable MT so we can configure */ 364 dvpe(); 365 dmt(); 366 367 spin_lock_init(&freeIPIq.lock); 368 369 /* 370 * We probably don't have as many VPEs as we do SMP "CPUs", 371 * but it's possible - and in any case we'll never use more! 372 */ 373 for (i=0; i<NR_CPUS; i++) { 374 IPIQ[i].head = IPIQ[i].tail = NULL; 375 spin_lock_init(&IPIQ[i].lock); 376 IPIQ[i].depth = 0; 377 ipi_timer_latch[i] = 0; 378 } 379 380 /* cpu_data index starts at zero */ 381 cpu = 0; 382 cpu_data[cpu].vpe_id = 0; 383 cpu_data[cpu].tc_id = 0; 384 cpu++; 385 386 /* Report on boot-time options */ 387 mips_mt_set_cpuoptions (); 388 if (vpelimit > 0) 389 printk("Limit of %d VPEs set\n", vpelimit); 390 if (tclimit > 0) 391 printk("Limit of %d TCs set\n", tclimit); 392 if (nostlb) { 393 printk("Shared TLB Use Inhibited - UNSAFE for Multi-VPE Operation\n"); 394 } 395 if (asidmask) 396 printk("ASID mask value override to 0x%x\n", asidmask); 397 398 /* Temporary */ 399#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG 400 if (hang_trig) 401 printk("Logic Analyser Trigger on suspected TC hang\n"); 402#endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */ 403 404 /* Put MVPE's into 'configuration state' */ 405 write_c0_mvpcontrol( read_c0_mvpcontrol() | MVPCONTROL_VPC ); 406 407 val = read_c0_mvpconf0(); 408 nvpe = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; 409 if (vpelimit > 0 && nvpe > vpelimit) 410 nvpe = vpelimit; 411 ntc = ((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1; 412 if (ntc > NR_CPUS) 413 ntc = NR_CPUS; 414 if (tclimit > 0 && ntc > tclimit) 415 ntc = tclimit; 416 tcpervpe = ntc / nvpe; 417 slop = ntc % nvpe; /* Residual TCs, < NVPE */ 418 419 /* Set up shared TLB */ 420 smtc_configure_tlb(); 421 422 for (tc = 0, vpe = 0 ; (vpe < nvpe) && (tc < ntc) ; vpe++) { 423 /* 424 * Set the MVP bits. 425 */ 426 settc(tc); 427 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_MVP); 428 if (vpe != 0) 429 printk(", "); 430 printk("VPE %d: TC", vpe); 431 for (i = 0; i < tcpervpe; i++) { 432 /* 433 * TC 0 is bound to VPE 0 at reset, 434 * and is presumably executing this 435 * code. Leave it alone! 436 */ 437 if (tc != 0) { 438 smtc_tc_setup(vpe,tc, cpu); 439 cpu++; 440 } 441 printk(" %d", tc); 442 tc++; 443 } 444 if (slop) { 445 if (tc != 0) { 446 smtc_tc_setup(vpe,tc, cpu); 447 cpu++; 448 } 449 printk(" %d", tc); 450 tc++; 451 slop--; 452 } 453 if (vpe != 0) { 454 /* 455 * Clear any stale software interrupts from VPE's Cause 456 */ 457 write_vpe_c0_cause(0); 458 459 /* 460 * Clear ERL/EXL of VPEs other than 0 461 * and set restricted interrupt enable/mask. 462 */ 463 write_vpe_c0_status((read_vpe_c0_status() 464 & ~(ST0_BEV | ST0_ERL | ST0_EXL | ST0_IM)) 465 | (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP7 466 | ST0_IE)); 467 /* 468 * set config to be the same as vpe0, 469 * particularly kseg0 coherency alg 470 */ 471 write_vpe_c0_config(read_c0_config()); 472 /* Clear any pending timer interrupt */ 473 write_vpe_c0_compare(0); 474 /* Propagate Config7 */ 475 write_vpe_c0_config7(read_c0_config7()); 476 write_vpe_c0_count(read_c0_count()); 477 } 478 /* enable multi-threading within VPE */ 479 write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() | VPECONTROL_TE); 480 /* enable the VPE */ 481 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA); 482 } 483 484 /* 485 * Pull any physically present but unused TCs out of circulation. 486 */ 487 while (tc < (((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1)) { 488 cpu_clear(tc, phys_cpu_present_map); 489 cpu_clear(tc, cpu_present_map); 490 tc++; 491 } 492 493 /* release config state */ 494 write_c0_mvpcontrol( read_c0_mvpcontrol() & ~ MVPCONTROL_VPC ); 495 496 printk("\n"); 497 498 /* Set up coprocessor affinity CPU mask(s) */ 499 500 for (tc = 0; tc < ntc; tc++) { 501 if (cpu_data[tc].options & MIPS_CPU_FPU) 502 cpu_set(tc, mt_fpu_cpumask); 503 } 504 505 /* set up ipi interrupts... */ 506 507 /* If we have multiple VPEs running, set up the cross-VPE interrupt */ 508 509 setup_cross_vpe_interrupts(nvpe); 510 511 /* Set up queue of free IPI "messages". */ 512 nipi = NR_CPUS * IPIBUF_PER_CPU; 513 if (ipibuffers > 0) 514 nipi = ipibuffers; 515 516 pipi = kmalloc(nipi *sizeof(struct smtc_ipi), GFP_KERNEL); 517 if (pipi == NULL) 518 panic("kmalloc of IPI message buffers failed\n"); 519 else 520 printk("IPI buffer pool of %d buffers\n", nipi); 521 for (i = 0; i < nipi; i++) { 522 smtc_ipi_nq(&freeIPIq, pipi); 523 pipi++; 524 } 525 526 /* Arm multithreading and enable other VPEs - but all TCs are Halted */ 527 emt(EMT_ENABLE); 528 evpe(EVPE_ENABLE); 529 local_irq_restore(flags); 530 /* Initialize SMTC /proc statistics/diagnostics */ 531 init_smtc_stats(); 532} 533 534 535/* 536 * Setup the PC, SP, and GP of a secondary processor and start it 537 * running! 538 * smp_bootstrap is the place to resume from 539 * __KSTK_TOS(idle) is apparently the stack pointer 540 * (unsigned long)idle->thread_info the gp 541 * 542 */ 543void smtc_boot_secondary(int cpu, struct task_struct *idle) 544{ 545 extern u32 kernelsp[NR_CPUS]; 546 long flags; 547 int mtflags; 548 549 LOCK_MT_PRA(); 550 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) { 551 dvpe(); 552 } 553 settc(cpu_data[cpu].tc_id); 554 555 /* pc */ 556 write_tc_c0_tcrestart((unsigned long)&smp_bootstrap); 557 558 /* stack pointer */ 559 kernelsp[cpu] = __KSTK_TOS(idle); 560 write_tc_gpr_sp(__KSTK_TOS(idle)); 561 562 /* global pointer */ 563 write_tc_gpr_gp((unsigned long)task_thread_info(idle)); 564 565 smtc_status |= SMTC_MTC_ACTIVE; 566 write_tc_c0_tchalt(0); 567 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) { 568 evpe(EVPE_ENABLE); 569 } 570 UNLOCK_MT_PRA(); 571} 572 573void smtc_init_secondary(void) 574{ 575 /* 576 * Start timer on secondary VPEs if necessary. 577 * plat_timer_setup has already have been invoked by init/main 578 * on "boot" TC. Like per_cpu_trap_init() hack, this assumes that 579 * SMTC init code assigns TCs consdecutively and in ascending order 580 * to across available VPEs. 581 */ 582 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && 583 ((read_c0_tcbind() & TCBIND_CURVPE) 584 != cpu_data[smp_processor_id() - 1].vpe_id)){ 585 write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ); 586 } 587 588 local_irq_enable(); 589} 590 591void smtc_smp_finish(void) 592{ 593 printk("TC %d going on-line as CPU %d\n", 594 cpu_data[smp_processor_id()].tc_id, smp_processor_id()); 595} 596 597void smtc_cpus_done(void) 598{ 599} 600 601/* 602 * Support for SMTC-optimized driver IRQ registration 603 */ 604 605/* 606 * SMTC Kernel needs to manipulate low-level CPU interrupt mask 607 * in do_IRQ. These are passed in setup_irq_smtc() and stored 608 * in this table. 609 */ 610 611int setup_irq_smtc(unsigned int irq, struct irqaction * new, 612 unsigned long hwmask) 613{ 614#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG 615 unsigned int vpe = current_cpu_data.vpe_id; 616 617 vpemask[vpe][irq - MIPS_CPU_IRQ_BASE] = 1; 618#endif 619 irq_hwmask[irq] = hwmask; 620 621 return setup_irq(irq, new); 622} 623 624/* 625 * IPI model for SMTC is tricky, because interrupts aren't TC-specific. 626 * Within a VPE one TC can interrupt another by different approaches. 627 * The easiest to get right would probably be to make all TCs except 628 * the target IXMT and set a software interrupt, but an IXMT-based 629 * scheme requires that a handler must run before a new IPI could 630 * be sent, which would break the "broadcast" loops in MIPS MT. 631 * A more gonzo approach within a VPE is to halt the TC, extract 632 * its Restart, Status, and a couple of GPRs, and program the Restart 633 * address to emulate an interrupt. 634 * 635 * Within a VPE, one can be confident that the target TC isn't in 636 * a critical EXL state when halted, since the write to the Halt 637 * register could not have issued on the writing thread if the 638 * halting thread had EXL set. So k0 and k1 of the target TC 639 * can be used by the injection code. Across VPEs, one can't 640 * be certain that the target TC isn't in a critical exception 641 * state. So we try a two-step process of sending a software 642 * interrupt to the target VPE, which either handles the event 643 * itself (if it was the target) or injects the event within 644 * the VPE. 645 */ 646 647static void smtc_ipi_qdump(void) 648{ 649 int i; 650 651 for (i = 0; i < NR_CPUS ;i++) { 652 printk("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n", 653 i, (unsigned)IPIQ[i].head, (unsigned)IPIQ[i].tail, 654 IPIQ[i].depth); 655 } 656} 657 658/* 659 * The standard atomic.h primitives don't quite do what we want 660 * here: We need an atomic add-and-return-previous-value (which 661 * could be done with atomic_add_return and a decrement) and an 662 * atomic set/zero-and-return-previous-value (which can't really 663 * be done with the atomic.h primitives). And since this is 664 * MIPS MT, we can assume that we have LL/SC. 665 */ 666static __inline__ int atomic_postincrement(unsigned int *pv) 667{ 668 unsigned long result; 669 670 unsigned long temp; 671 672 __asm__ __volatile__( 673 "1: ll %0, %2 \n" 674 " addu %1, %0, 1 \n" 675 " sc %1, %2 \n" 676 " beqz %1, 1b \n" 677 " sync \n" 678 : "=&r" (result), "=&r" (temp), "=m" (*pv) 679 : "m" (*pv) 680 : "memory"); 681 682 return result; 683} 684 685void smtc_send_ipi(int cpu, int type, unsigned int action) 686{ 687 int tcstatus; 688 struct smtc_ipi *pipi; 689 long flags; 690 int mtflags; 691 692 if (cpu == smp_processor_id()) { 693 printk("Cannot Send IPI to self!\n"); 694 return; 695 } 696 /* Set up a descriptor, to be delivered either promptly or queued */ 697 pipi = smtc_ipi_dq(&freeIPIq); 698 if (pipi == NULL) { 699 bust_spinlocks(1); 700 mips_mt_regdump(dvpe()); 701 panic("IPI Msg. Buffers Depleted\n"); 702 } 703 pipi->type = type; 704 pipi->arg = (void *)action; 705 pipi->dest = cpu; 706 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) { 707 /* If not on same VPE, enqueue and send cross-VPE interupt */ 708 smtc_ipi_nq(&IPIQ[cpu], pipi); 709 LOCK_CORE_PRA(); 710 settc(cpu_data[cpu].tc_id); 711 write_vpe_c0_cause(read_vpe_c0_cause() | C_SW1); 712 UNLOCK_CORE_PRA(); 713 } else { 714 /* 715 * Not sufficient to do a LOCK_MT_PRA (dmt) here, 716 * since ASID shootdown on the other VPE may 717 * collide with this operation. 718 */ 719 LOCK_CORE_PRA(); 720 settc(cpu_data[cpu].tc_id); 721 /* Halt the targeted TC */ 722 write_tc_c0_tchalt(TCHALT_H); 723 mips_ihb(); 724 725 /* 726 * Inspect TCStatus - if IXMT is set, we have to queue 727 * a message. Otherwise, we set up the "interrupt" 728 * of the other TC 729 */ 730 tcstatus = read_tc_c0_tcstatus(); 731 732 if ((tcstatus & TCSTATUS_IXMT) != 0) { 733 /* 734 * Spin-waiting here can deadlock, 735 * so we queue the message for the target TC. 736 */ 737 write_tc_c0_tchalt(0); 738 UNLOCK_CORE_PRA(); 739 /* Try to reduce redundant timer interrupt messages */ 740 if (type == SMTC_CLOCK_TICK) { 741 if (atomic_postincrement(&ipi_timer_latch[cpu])!=0){ 742 smtc_ipi_nq(&freeIPIq, pipi); 743 return; 744 } 745 } 746 smtc_ipi_nq(&IPIQ[cpu], pipi); 747 } else { 748 post_direct_ipi(cpu, pipi); 749 write_tc_c0_tchalt(0); 750 UNLOCK_CORE_PRA(); 751 } 752 } 753} 754 755/* 756 * Send IPI message to Halted TC, TargTC/TargVPE already having been set 757 */ 758static void post_direct_ipi(int cpu, struct smtc_ipi *pipi) 759{ 760 struct pt_regs *kstack; 761 unsigned long tcstatus; 762 unsigned long tcrestart; 763 extern u32 kernelsp[NR_CPUS]; 764 extern void __smtc_ipi_vector(void); 765 766 /* Extract Status, EPC from halted TC */ 767 tcstatus = read_tc_c0_tcstatus(); 768 tcrestart = read_tc_c0_tcrestart(); 769 /* If TCRestart indicates a WAIT instruction, advance the PC */ 770 if ((tcrestart & 0x80000000) 771 && ((*(unsigned int *)tcrestart & 0xfe00003f) == 0x42000020)) { 772 tcrestart += 4; 773 } 774 /* 775 * Save on TC's future kernel stack 776 * 777 * CU bit of Status is indicator that TC was 778 * already running on a kernel stack... 779 */ 780 if (tcstatus & ST0_CU0) { 781 /* Note that this "- 1" is pointer arithmetic */ 782 kstack = ((struct pt_regs *)read_tc_gpr_sp()) - 1; 783 } else { 784 kstack = ((struct pt_regs *)kernelsp[cpu]) - 1; 785 } 786 787 kstack->cp0_epc = (long)tcrestart; 788 /* Save TCStatus */ 789 kstack->cp0_tcstatus = tcstatus; 790 /* Pass token of operation to be performed kernel stack pad area */ 791 kstack->pad0[4] = (unsigned long)pipi; 792 /* Pass address of function to be called likewise */ 793 kstack->pad0[5] = (unsigned long)&ipi_decode; 794 /* Set interrupt exempt and kernel mode */ 795 tcstatus |= TCSTATUS_IXMT; 796 tcstatus &= ~TCSTATUS_TKSU; 797 write_tc_c0_tcstatus(tcstatus); 798 ehb(); 799 /* Set TC Restart address to be SMTC IPI vector */ 800 write_tc_c0_tcrestart(__smtc_ipi_vector); 801} 802 803static void ipi_resched_interrupt(void) 804{ 805 /* Return from interrupt should be enough to cause scheduler check */ 806} 807 808 809static void ipi_call_interrupt(void) 810{ 811 /* Invoke generic function invocation code in smp.c */ 812 smp_call_function_interrupt(); 813} 814 815void ipi_decode(struct smtc_ipi *pipi) 816{ 817 void *arg_copy = pipi->arg; 818 int type_copy = pipi->type; 819 int dest_copy = pipi->dest; 820 821 smtc_ipi_nq(&freeIPIq, pipi); 822 switch (type_copy) { 823 case SMTC_CLOCK_TICK: 824 irq_enter(); 825 kstat_this_cpu.irqs[MIPS_CPU_IRQ_BASE + cp0_compare_irq]++; 826 /* Invoke Clock "Interrupt" */ 827 ipi_timer_latch[dest_copy] = 0; 828#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG 829 clock_hang_reported[dest_copy] = 0; 830#endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */ 831 local_timer_interrupt(0, NULL); 832 irq_exit(); 833 break; 834 case LINUX_SMP_IPI: 835 switch ((int)arg_copy) { 836 case SMP_RESCHEDULE_YOURSELF: 837 ipi_resched_interrupt(); 838 break; 839 case SMP_CALL_FUNCTION: 840 ipi_call_interrupt(); 841 break; 842 default: 843 printk("Impossible SMTC IPI Argument 0x%x\n", 844 (int)arg_copy); 845 break; 846 } 847 break; 848 default: 849 printk("Impossible SMTC IPI Type 0x%x\n", type_copy); 850 break; 851 } 852} 853 854void deferred_smtc_ipi(void) 855{ 856 struct smtc_ipi *pipi; 857 unsigned long flags; 858/* DEBUG */ 859 int q = smp_processor_id(); 860 861 /* 862 * Test is not atomic, but much faster than a dequeue, 863 * and the vast majority of invocations will have a null queue. 864 */ 865 if (IPIQ[q].head != NULL) { 866 while((pipi = smtc_ipi_dq(&IPIQ[q])) != NULL) { 867 /* ipi_decode() should be called with interrupts off */ 868 local_irq_save(flags); 869 ipi_decode(pipi); 870 local_irq_restore(flags); 871 } 872 } 873} 874 875/* 876 * Send clock tick to all TCs except the one executing the funtion 877 */ 878 879void smtc_timer_broadcast(int vpe) 880{ 881 int cpu; 882 int myTC = cpu_data[smp_processor_id()].tc_id; 883 int myVPE = cpu_data[smp_processor_id()].vpe_id; 884 885 smtc_cpu_stats[smp_processor_id()].timerints++; 886 887 for_each_online_cpu(cpu) { 888 if (cpu_data[cpu].vpe_id == myVPE && 889 cpu_data[cpu].tc_id != myTC) 890 smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0); 891 } 892} 893 894/* 895 * Cross-VPE interrupts in the SMTC prototype use "software interrupts" 896 * set via cross-VPE MTTR manipulation of the Cause register. It would be 897 * in some regards preferable to have external logic for "doorbell" hardware 898 * interrupts. 899 */ 900 901static int cpu_ipi_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_IRQ; 902 903static irqreturn_t ipi_interrupt(int irq, void *dev_idm) 904{ 905 int my_vpe = cpu_data[smp_processor_id()].vpe_id; 906 int my_tc = cpu_data[smp_processor_id()].tc_id; 907 int cpu; 908 struct smtc_ipi *pipi; 909 unsigned long tcstatus; 910 int sent; 911 long flags; 912 unsigned int mtflags; 913 unsigned int vpflags; 914 915 /* 916 * So long as cross-VPE interrupts are done via 917 * MFTR/MTTR read-modify-writes of Cause, we need 918 * to stop other VPEs whenever the local VPE does 919 * anything similar. 920 */ 921 local_irq_save(flags); 922 vpflags = dvpe(); 923 clear_c0_cause(0x100 << MIPS_CPU_IPI_IRQ); 924 set_c0_status(0x100 << MIPS_CPU_IPI_IRQ); 925 irq_enable_hazard(); 926 evpe(vpflags); 927 local_irq_restore(flags); 928 929 /* 930 * Cross-VPE Interrupt handler: Try to directly deliver IPIs 931 * queued for TCs on this VPE other than the current one. 932 * Return-from-interrupt should cause us to drain the queue 933 * for the current TC, so we ought not to have to do it explicitly here. 934 */ 935 936 for_each_online_cpu(cpu) { 937 if (cpu_data[cpu].vpe_id != my_vpe) 938 continue; 939 940 pipi = smtc_ipi_dq(&IPIQ[cpu]); 941 if (pipi != NULL) { 942 if (cpu_data[cpu].tc_id != my_tc) { 943 sent = 0; 944 LOCK_MT_PRA(); 945 settc(cpu_data[cpu].tc_id); 946 write_tc_c0_tchalt(TCHALT_H); 947 mips_ihb(); 948 tcstatus = read_tc_c0_tcstatus(); 949 if ((tcstatus & TCSTATUS_IXMT) == 0) { 950 post_direct_ipi(cpu, pipi); 951 sent = 1; 952 } 953 write_tc_c0_tchalt(0); 954 UNLOCK_MT_PRA(); 955 if (!sent) { 956 smtc_ipi_req(&IPIQ[cpu], pipi); 957 } 958 } else { 959 /* 960 * ipi_decode() should be called 961 * with interrupts off 962 */ 963 local_irq_save(flags); 964 ipi_decode(pipi); 965 local_irq_restore(flags); 966 } 967 } 968 } 969 970 return IRQ_HANDLED; 971} 972 973static void ipi_irq_dispatch(void) 974{ 975 do_IRQ(cpu_ipi_irq); 976} 977 978static struct irqaction irq_ipi = { 979 .handler = ipi_interrupt, 980 .flags = IRQF_DISABLED, 981 .name = "SMTC_IPI", 982 .flags = IRQF_PERCPU 983}; 984 985static void setup_cross_vpe_interrupts(unsigned int nvpe) 986{ 987 if (nvpe < 1) 988 return; 989 990 if (!cpu_has_vint) 991 panic("SMTC Kernel requires Vectored Interupt support"); 992 993 set_vi_handler(MIPS_CPU_IPI_IRQ, ipi_irq_dispatch); 994 995 setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ)); 996 997 set_irq_handler(cpu_ipi_irq, handle_percpu_irq); 998} 999 1000/* 1001 * SMTC-specific hacks invoked from elsewhere in the kernel. 1002 * 1003 * smtc_ipi_replay is called from raw_local_irq_restore which is only ever 1004 * called with interrupts disabled. We do rely on interrupts being disabled 1005 * here because using spin_lock_irqsave()/spin_unlock_irqrestore() would 1006 * result in a recursive call to raw_local_irq_restore(). 1007 */ 1008 1009static void __smtc_ipi_replay(void) 1010{ 1011 unsigned int cpu = smp_processor_id(); 1012 1013 /* 1014 * To the extent that we've ever turned interrupts off, 1015 * we may have accumulated deferred IPIs. This is subtle. 1016 * If we use the smtc_ipi_qdepth() macro, we'll get an 1017 * exact number - but we'll also disable interrupts 1018 * and create a window of failure where a new IPI gets 1019 * queued after we test the depth but before we re-enable 1020 * interrupts. So long as IXMT never gets set, however, 1021 * we should be OK: If we pick up something and dispatch 1022 * it here, that's great. If we see nothing, but concurrent 1023 * with this operation, another TC sends us an IPI, IXMT 1024 * is clear, and we'll handle it as a real pseudo-interrupt 1025 * and not a pseudo-pseudo interrupt. 1026 */ 1027 if (IPIQ[cpu].depth > 0) { 1028 while (1) { 1029 struct smtc_ipi_q *q = &IPIQ[cpu]; 1030 struct smtc_ipi *pipi; 1031 extern void self_ipi(struct smtc_ipi *); 1032 1033 spin_lock(&q->lock); 1034 pipi = __smtc_ipi_dq(q); 1035 spin_unlock(&q->lock); 1036 if (!pipi) 1037 break; 1038 1039 self_ipi(pipi); 1040 smtc_cpu_stats[cpu].selfipis++; 1041 } 1042 } 1043} 1044 1045void smtc_ipi_replay(void) 1046{ 1047 raw_local_irq_disable(); 1048 __smtc_ipi_replay(); 1049} 1050 1051EXPORT_SYMBOL(smtc_ipi_replay); 1052 1053void smtc_idle_loop_hook(void) 1054{ 1055#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG 1056 int im; 1057 int flags; 1058 int mtflags; 1059 int bit; 1060 int vpe; 1061 int tc; 1062 int hook_ntcs; 1063 /* 1064 * printk within DMT-protected regions can deadlock, 1065 * so buffer diagnostic messages for later output. 1066 */ 1067 char *pdb_msg; 1068 char id_ho_db_msg[768]; /* worst-case use should be less than 700 */ 1069 1070 if (atomic_read(&idle_hook_initialized) == 0) { /* fast test */ 1071 if (atomic_add_return(1, &idle_hook_initialized) == 1) { 1072 int mvpconf0; 1073 /* Tedious stuff to just do once */ 1074 mvpconf0 = read_c0_mvpconf0(); 1075 hook_ntcs = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1; 1076 if (hook_ntcs > NR_CPUS) 1077 hook_ntcs = NR_CPUS; 1078 for (tc = 0; tc < hook_ntcs; tc++) { 1079 tcnoprog[tc] = 0; 1080 clock_hang_reported[tc] = 0; 1081 } 1082 for (vpe = 0; vpe < 2; vpe++) 1083 for (im = 0; im < 8; im++) 1084 imstuckcount[vpe][im] = 0; 1085 printk("Idle loop test hook initialized for %d TCs\n", hook_ntcs); 1086 atomic_set(&idle_hook_initialized, 1000); 1087 } else { 1088 /* Someone else is initializing in parallel - let 'em finish */ 1089 while (atomic_read(&idle_hook_initialized) < 1000) 1090 ; 1091 } 1092 } 1093 1094 /* Have we stupidly left IXMT set somewhere? */ 1095 if (read_c0_tcstatus() & 0x400) { 1096 write_c0_tcstatus(read_c0_tcstatus() & ~0x400); 1097 ehb(); 1098 printk("Dangling IXMT in cpu_idle()\n"); 1099 } 1100 1101 /* Have we stupidly left an IM bit turned off? */ 1102#define IM_LIMIT 2000 1103 local_irq_save(flags); 1104 mtflags = dmt(); 1105 pdb_msg = &id_ho_db_msg[0]; 1106 im = read_c0_status(); 1107 vpe = current_cpu_data.vpe_id; 1108 for (bit = 0; bit < 8; bit++) { 1109 /* 1110 * In current prototype, I/O interrupts 1111 * are masked for VPE > 0 1112 */ 1113 if (vpemask[vpe][bit]) { 1114 if (!(im & (0x100 << bit))) 1115 imstuckcount[vpe][bit]++; 1116 else 1117 imstuckcount[vpe][bit] = 0; 1118 if (imstuckcount[vpe][bit] > IM_LIMIT) { 1119 set_c0_status(0x100 << bit); 1120 ehb(); 1121 imstuckcount[vpe][bit] = 0; 1122 pdb_msg += sprintf(pdb_msg, 1123 "Dangling IM %d fixed for VPE %d\n", bit, 1124 vpe); 1125 } 1126 } 1127 } 1128 1129 /* 1130 * Now that we limit outstanding timer IPIs, check for hung TC 1131 */ 1132 for (tc = 0; tc < NR_CPUS; tc++) { 1133 /* Don't check ourself - we'll dequeue IPIs just below */ 1134 if ((tc != smp_processor_id()) && 1135 ipi_timer_latch[tc] > timerq_limit) { 1136 if (clock_hang_reported[tc] == 0) { 1137 pdb_msg += sprintf(pdb_msg, 1138 "TC %d looks hung with timer latch at %d\n", 1139 tc, ipi_timer_latch[tc]); 1140 clock_hang_reported[tc]++; 1141 } 1142 } 1143 } 1144 emt(mtflags); 1145 local_irq_restore(flags); 1146 if (pdb_msg != &id_ho_db_msg[0]) 1147 printk("CPU%d: %s", smp_processor_id(), id_ho_db_msg); 1148#endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */ 1149 1150 /* 1151 * Replay any accumulated deferred IPIs. If "Instant Replay" 1152 * is in use, there should never be any. 1153 */ 1154#ifndef CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY 1155 { 1156 unsigned long flags; 1157 1158 local_irq_save(flags); 1159 __smtc_ipi_replay(); 1160 local_irq_restore(flags); 1161 } 1162#endif /* CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY */ 1163} 1164 1165void smtc_soft_dump(void) 1166{ 1167 int i; 1168 1169 printk("Counter Interrupts taken per CPU (TC)\n"); 1170 for (i=0; i < NR_CPUS; i++) { 1171 printk("%d: %ld\n", i, smtc_cpu_stats[i].timerints); 1172 } 1173 printk("Self-IPI invocations:\n"); 1174 for (i=0; i < NR_CPUS; i++) { 1175 printk("%d: %ld\n", i, smtc_cpu_stats[i].selfipis); 1176 } 1177 smtc_ipi_qdump(); 1178 printk("Timer IPI Backlogs:\n"); 1179 for (i=0; i < NR_CPUS; i++) { 1180 printk("%d: %d\n", i, ipi_timer_latch[i]); 1181 } 1182 printk("%d Recoveries of \"stolen\" FPU\n", 1183 atomic_read(&smtc_fpu_recoveries)); 1184} 1185 1186 1187/* 1188 * TLB management routines special to SMTC 1189 */ 1190 1191void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) 1192{ 1193 unsigned long flags, mtflags, tcstat, prevhalt, asid; 1194 int tlb, i; 1195 1196 /* 1197 * It would be nice to be able to use a spinlock here, 1198 * but this is invoked from within TLB flush routines 1199 * that protect themselves with DVPE, so if a lock is 1200 * held by another TC, it'll never be freed. 1201 * 1202 * DVPE/DMT must not be done with interrupts enabled, 1203 * so even so most callers will already have disabled 1204 * them, let's be really careful... 1205 */ 1206 1207 local_irq_save(flags); 1208 if (smtc_status & SMTC_TLB_SHARED) { 1209 mtflags = dvpe(); 1210 tlb = 0; 1211 } else { 1212 mtflags = dmt(); 1213 tlb = cpu_data[cpu].vpe_id; 1214 } 1215 asid = asid_cache(cpu); 1216 1217 do { 1218 if (!((asid += ASID_INC) & ASID_MASK) ) { 1219 if (cpu_has_vtag_icache) 1220 flush_icache_all(); 1221 /* Traverse all online CPUs (hack requires contigous range) */ 1222 for (i = 0; i < num_online_cpus(); i++) { 1223 /* 1224 * We don't need to worry about our own CPU, nor those of 1225 * CPUs who don't share our TLB. 1226 */ 1227 if ((i != smp_processor_id()) && 1228 ((smtc_status & SMTC_TLB_SHARED) || 1229 (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))) { 1230 settc(cpu_data[i].tc_id); 1231 prevhalt = read_tc_c0_tchalt() & TCHALT_H; 1232 if (!prevhalt) { 1233 write_tc_c0_tchalt(TCHALT_H); 1234 mips_ihb(); 1235 } 1236 tcstat = read_tc_c0_tcstatus(); 1237 smtc_live_asid[tlb][(tcstat & ASID_MASK)] |= (asiduse)(0x1 << i); 1238 if (!prevhalt) 1239 write_tc_c0_tchalt(0); 1240 } 1241 } 1242 if (!asid) /* fix version if needed */ 1243 asid = ASID_FIRST_VERSION; 1244 local_flush_tlb_all(); /* start new asid cycle */ 1245 } 1246 } while (smtc_live_asid[tlb][(asid & ASID_MASK)]); 1247 1248 /* 1249 * SMTC shares the TLB within VPEs and possibly across all VPEs. 1250 */ 1251 for (i = 0; i < num_online_cpus(); i++) { 1252 if ((smtc_status & SMTC_TLB_SHARED) || 1253 (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id)) 1254 cpu_context(i, mm) = asid_cache(i) = asid; 1255 } 1256 1257 if (smtc_status & SMTC_TLB_SHARED) 1258 evpe(mtflags); 1259 else 1260 emt(mtflags); 1261 local_irq_restore(flags); 1262} 1263 1264/* 1265 * Invoked from macros defined in mmu_context.h 1266 * which must already have disabled interrupts 1267 * and done a DVPE or DMT as appropriate. 1268 */ 1269 1270void smtc_flush_tlb_asid(unsigned long asid) 1271{ 1272 int entry; 1273 unsigned long ehi; 1274 1275 entry = read_c0_wired(); 1276 1277 /* Traverse all non-wired entries */ 1278 while (entry < current_cpu_data.tlbsize) { 1279 write_c0_index(entry); 1280 ehb(); 1281 tlb_read(); 1282 ehb(); 1283 ehi = read_c0_entryhi(); 1284 if ((ehi & ASID_MASK) == asid) { 1285 /* 1286 * Invalidate only entries with specified ASID, 1287 * makiing sure all entries differ. 1288 */ 1289 write_c0_entryhi(CKSEG0 + (entry << (PAGE_SHIFT + 1))); 1290 write_c0_entrylo0(0); 1291 write_c0_entrylo1(0); 1292 mtc0_tlbw_hazard(); 1293 tlb_write_indexed(); 1294 } 1295 entry++; 1296 } 1297 write_c0_index(PARKED_INDEX); 1298 tlbw_use_hazard(); 1299} 1300 1301/* 1302 * Support for single-threading cache flush operations. 1303 */ 1304 1305static int halt_state_save[NR_CPUS]; 1306 1307/* 1308 * To really, really be sure that nothing is being done 1309 * by other TCs, halt them all. This code assumes that 1310 * a DVPE has already been done, so while their Halted 1311 * state is theoretically architecturally unstable, in 1312 * practice, it's not going to change while we're looking 1313 * at it. 1314 */ 1315 1316void smtc_cflush_lockdown(void) 1317{ 1318 int cpu; 1319 1320 for_each_online_cpu(cpu) { 1321 if (cpu != smp_processor_id()) { 1322 settc(cpu_data[cpu].tc_id); 1323 halt_state_save[cpu] = read_tc_c0_tchalt(); 1324 write_tc_c0_tchalt(TCHALT_H); 1325 } 1326 } 1327 mips_ihb(); 1328} 1329 1330/* It would be cheating to change the cpu_online states during a flush! */ 1331 1332void smtc_cflush_release(void) 1333{ 1334 int cpu; 1335 1336 /* 1337 * Start with a hazard barrier to ensure 1338 * that all CACHE ops have played through. 1339 */ 1340 mips_ihb(); 1341 1342 for_each_online_cpu(cpu) { 1343 if (cpu != smp_processor_id()) { 1344 settc(cpu_data[cpu].tc_id); 1345 write_tc_c0_tchalt(halt_state_save[cpu]); 1346 } 1347 } 1348 mips_ihb(); 1349} 1350