1/*
2 * Freescale MPC85xx/MPC86xx RapidIO support
3 *
4 * Copyright 2009 Sysgo AG
5 * Thomas Moll <thomas.moll@sysgo.com>
6 * - fixed maintenance access routines, check for aligned access
7 *
8 * Copyright 2009 Integrated Device Technology, Inc.
9 * Alex Bounine <alexandre.bounine@idt.com>
10 * - Added Port-Write message handling
11 * - Added Machine Check exception handling
12 *
13 * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
14 * Zhang Wei <wei.zhang@freescale.com>
15 *
16 * Copyright 2005 MontaVista Software, Inc.
17 * Matt Porter <mporter@kernel.crashing.org>
18 *
19 * This program is free software; you can redistribute  it and/or modify it
20 * under  the terms of  the GNU General  Public License as published by the
21 * Free Software Foundation;  either version 2 of the  License, or (at your
22 * option) any later version.
23 */
24
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/dma-mapping.h>
29#include <linux/interrupt.h>
30#include <linux/device.h>
31#include <linux/of_platform.h>
32#include <linux/delay.h>
33#include <linux/slab.h>
34
35#include <linux/io.h>
36#include <linux/uaccess.h>
37#include <asm/machdep.h>
38
39#include "fsl_rio.h"
40
41#undef DEBUG_PW	/* Port-Write debugging */
42
43#define RIO_PORT1_EDCSR		0x0640
44#define RIO_PORT2_EDCSR		0x0680
45#define RIO_PORT1_IECSR		0x10130
46#define RIO_PORT2_IECSR		0x101B0
47
48#define RIO_GCCSR		0x13c
49#define RIO_ESCSR		0x158
50#define ESCSR_CLEAR		0x07120204
51#define RIO_PORT2_ESCSR		0x178
52#define RIO_CCSR		0x15c
53#define RIO_LTLEDCSR_IER	0x80000000
54#define RIO_LTLEDCSR_PRT	0x01000000
55#define IECSR_CLEAR		0x80000000
56#define RIO_ISR_AACR		0x10120
57#define RIO_ISR_AACR_AA		0x1	/* Accept All ID */
58
59#define __fsl_read_rio_config(x, addr, err, op)		\
60	__asm__ __volatile__(				\
61		"1:	"op" %1,0(%2)\n"		\
62		"	eieio\n"			\
63		"2:\n"					\
64		".section .fixup,\"ax\"\n"		\
65		"3:	li %1,-1\n"			\
66		"	li %0,%3\n"			\
67		"	b 2b\n"				\
68		".section __ex_table,\"a\"\n"		\
69			PPC_LONG_ALIGN "\n"		\
70			PPC_LONG "1b,3b\n"		\
71		".text"					\
72		: "=r" (err), "=r" (x)			\
73		: "b" (addr), "i" (-EFAULT), "0" (err))
74
75void __iomem *rio_regs_win;
76void __iomem *rmu_regs_win;
77resource_size_t rio_law_start;
78
79struct fsl_rio_dbell *dbell;
80struct fsl_rio_pw *pw;
81
82#ifdef CONFIG_E500
83int fsl_rio_mcheck_exception(struct pt_regs *regs)
84{
85	const struct exception_table_entry *entry;
86	unsigned long reason;
87
88	if (!rio_regs_win)
89		return 0;
90
91	reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR));
92	if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) {
93		/* Check if we are prepared to handle this fault */
94		entry = search_exception_tables(regs->nip);
95		if (entry) {
96			pr_debug("RIO: %s - MC Exception handled\n",
97				 __func__);
98			out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR),
99				 0);
100			regs->msr |= MSR_RI;
101			regs->nip = entry->fixup;
102			return 1;
103		}
104	}
105
106	return 0;
107}
108EXPORT_SYMBOL_GPL(fsl_rio_mcheck_exception);
109#endif
110
111/**
112 * fsl_local_config_read - Generate a MPC85xx local config space read
113 * @mport: RapidIO master port info
114 * @index: ID of RapdiIO interface
115 * @offset: Offset into configuration space
116 * @len: Length (in bytes) of the maintenance transaction
117 * @data: Value to be read into
118 *
119 * Generates a MPC85xx local configuration space read. Returns %0 on
120 * success or %-EINVAL on failure.
121 */
122static int fsl_local_config_read(struct rio_mport *mport,
123				int index, u32 offset, int len, u32 *data)
124{
125	struct rio_priv *priv = mport->priv;
126	pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
127		 offset);
128	*data = in_be32(priv->regs_win + offset);
129
130	return 0;
131}
132
133/**
134 * fsl_local_config_write - Generate a MPC85xx local config space write
135 * @mport: RapidIO master port info
136 * @index: ID of RapdiIO interface
137 * @offset: Offset into configuration space
138 * @len: Length (in bytes) of the maintenance transaction
139 * @data: Value to be written
140 *
141 * Generates a MPC85xx local configuration space write. Returns %0 on
142 * success or %-EINVAL on failure.
143 */
144static int fsl_local_config_write(struct rio_mport *mport,
145				int index, u32 offset, int len, u32 data)
146{
147	struct rio_priv *priv = mport->priv;
148	pr_debug
149		("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
150		index, offset, data);
151	out_be32(priv->regs_win + offset, data);
152
153	return 0;
154}
155
156/**
157 * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
158 * @mport: RapidIO master port info
159 * @index: ID of RapdiIO interface
160 * @destid: Destination ID of transaction
161 * @hopcount: Number of hops to target device
162 * @offset: Offset into configuration space
163 * @len: Length (in bytes) of the maintenance transaction
164 * @val: Location to be read into
165 *
166 * Generates a MPC85xx read maintenance transaction. Returns %0 on
167 * success or %-EINVAL on failure.
168 */
169static int
170fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
171			u8 hopcount, u32 offset, int len, u32 *val)
172{
173	struct rio_priv *priv = mport->priv;
174	u8 *data;
175	u32 rval, err = 0;
176
177	pr_debug
178		("fsl_rio_config_read:"
179		" index %d destid %d hopcount %d offset %8.8x len %d\n",
180		index, destid, hopcount, offset, len);
181
182	/* 16MB maintenance window possible */
183	/* allow only aligned access to maintenance registers */
184	if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
185		return -EINVAL;
186
187	out_be32(&priv->maint_atmu_regs->rowtar,
188		 (destid << 22) | (hopcount << 12) | (offset >> 12));
189	out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
190
191	data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
192	switch (len) {
193	case 1:
194		__fsl_read_rio_config(rval, data, err, "lbz");
195		break;
196	case 2:
197		__fsl_read_rio_config(rval, data, err, "lhz");
198		break;
199	case 4:
200		__fsl_read_rio_config(rval, data, err, "lwz");
201		break;
202	default:
203		return -EINVAL;
204	}
205
206	if (err) {
207		pr_debug("RIO: cfg_read error %d for %x:%x:%x\n",
208			 err, destid, hopcount, offset);
209	}
210
211	*val = rval;
212
213	return err;
214}
215
216/**
217 * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
218 * @mport: RapidIO master port info
219 * @index: ID of RapdiIO interface
220 * @destid: Destination ID of transaction
221 * @hopcount: Number of hops to target device
222 * @offset: Offset into configuration space
223 * @len: Length (in bytes) of the maintenance transaction
224 * @val: Value to be written
225 *
226 * Generates an MPC85xx write maintenance transaction. Returns %0 on
227 * success or %-EINVAL on failure.
228 */
229static int
230fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
231			u8 hopcount, u32 offset, int len, u32 val)
232{
233	struct rio_priv *priv = mport->priv;
234	u8 *data;
235	pr_debug
236		("fsl_rio_config_write:"
237		" index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
238		index, destid, hopcount, offset, len, val);
239
240	/* 16MB maintenance windows possible */
241	/* allow only aligned access to maintenance registers */
242	if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
243		return -EINVAL;
244
245	out_be32(&priv->maint_atmu_regs->rowtar,
246		 (destid << 22) | (hopcount << 12) | (offset >> 12));
247	out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
248
249	data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
250	switch (len) {
251	case 1:
252		out_8((u8 *) data, val);
253		break;
254	case 2:
255		out_be16((u16 *) data, val);
256		break;
257	case 4:
258		out_be32((u32 *) data, val);
259		break;
260	default:
261		return -EINVAL;
262	}
263
264	return 0;
265}
266
267void fsl_rio_port_error_handler(int offset)
268{
269	/*XXX: Error recovery is not implemented, we just clear errors */
270	out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
271
272	if (offset == 0) {
273		out_be32((u32 *)(rio_regs_win + RIO_PORT1_EDCSR), 0);
274		out_be32((u32 *)(rio_regs_win + RIO_PORT1_IECSR), IECSR_CLEAR);
275		out_be32((u32 *)(rio_regs_win + RIO_ESCSR), ESCSR_CLEAR);
276	} else {
277		out_be32((u32 *)(rio_regs_win + RIO_PORT2_EDCSR), 0);
278		out_be32((u32 *)(rio_regs_win + RIO_PORT2_IECSR), IECSR_CLEAR);
279		out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR);
280	}
281}
282static inline void fsl_rio_info(struct device *dev, u32 ccsr)
283{
284	const char *str;
285	if (ccsr & 1) {
286		/* Serial phy */
287		switch (ccsr >> 30) {
288		case 0:
289			str = "1";
290			break;
291		case 1:
292			str = "4";
293			break;
294		default:
295			str = "Unknown";
296			break;
297		}
298		dev_info(dev, "Hardware port width: %s\n", str);
299
300		switch ((ccsr >> 27) & 7) {
301		case 0:
302			str = "Single-lane 0";
303			break;
304		case 1:
305			str = "Single-lane 2";
306			break;
307		case 2:
308			str = "Four-lane";
309			break;
310		default:
311			str = "Unknown";
312			break;
313		}
314		dev_info(dev, "Training connection status: %s\n", str);
315	} else {
316		/* Parallel phy */
317		if (!(ccsr & 0x80000000))
318			dev_info(dev, "Output port operating in 8-bit mode\n");
319		if (!(ccsr & 0x08000000))
320			dev_info(dev, "Input port operating in 8-bit mode\n");
321	}
322}
323
324/**
325 * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
326 * @dev: platform_device pointer
327 *
328 * Initializes MPC85xx RapidIO hardware interface, configures
329 * master port with system-specific info, and registers the
330 * master port with the RapidIO subsystem.
331 */
332int fsl_rio_setup(struct platform_device *dev)
333{
334	struct rio_ops *ops;
335	struct rio_mport *port;
336	struct rio_priv *priv;
337	int rc = 0;
338	const u32 *dt_range, *cell, *port_index;
339	u32 active_ports = 0;
340	struct resource regs, rmu_regs;
341	struct device_node *np, *rmu_node;
342	int rlen;
343	u32 ccsr;
344	u64 range_start, range_size;
345	int paw, aw, sw;
346	u32 i;
347	static int tmp;
348	struct device_node *rmu_np[MAX_MSG_UNIT_NUM] = {NULL};
349
350	if (!dev->dev.of_node) {
351		dev_err(&dev->dev, "Device OF-Node is NULL");
352		return -ENODEV;
353	}
354
355	rc = of_address_to_resource(dev->dev.of_node, 0, &regs);
356	if (rc) {
357		dev_err(&dev->dev, "Can't get %s property 'reg'\n",
358				dev->dev.of_node->full_name);
359		return -EFAULT;
360	}
361	dev_info(&dev->dev, "Of-device full name %s\n",
362			dev->dev.of_node->full_name);
363	dev_info(&dev->dev, "Regs: %pR\n", &regs);
364
365	rio_regs_win = ioremap(regs.start, resource_size(&regs));
366	if (!rio_regs_win) {
367		dev_err(&dev->dev, "Unable to map rio register window\n");
368		rc = -ENOMEM;
369		goto err_rio_regs;
370	}
371
372	ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
373	if (!ops) {
374		rc = -ENOMEM;
375		goto err_ops;
376	}
377	ops->lcread = fsl_local_config_read;
378	ops->lcwrite = fsl_local_config_write;
379	ops->cread = fsl_rio_config_read;
380	ops->cwrite = fsl_rio_config_write;
381	ops->dsend = fsl_rio_doorbell_send;
382	ops->pwenable = fsl_rio_pw_enable;
383	ops->open_outb_mbox = fsl_open_outb_mbox;
384	ops->open_inb_mbox = fsl_open_inb_mbox;
385	ops->close_outb_mbox = fsl_close_outb_mbox;
386	ops->close_inb_mbox = fsl_close_inb_mbox;
387	ops->add_outb_message = fsl_add_outb_message;
388	ops->add_inb_buffer = fsl_add_inb_buffer;
389	ops->get_inb_message = fsl_get_inb_message;
390
391	rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0);
392	if (!rmu_node)
393		goto err_rmu;
394	rc = of_address_to_resource(rmu_node, 0, &rmu_regs);
395	if (rc) {
396		dev_err(&dev->dev, "Can't get %s property 'reg'\n",
397				rmu_node->full_name);
398		goto err_rmu;
399	}
400	rmu_regs_win = ioremap(rmu_regs.start, resource_size(&rmu_regs));
401	if (!rmu_regs_win) {
402		dev_err(&dev->dev, "Unable to map rmu register window\n");
403		rc = -ENOMEM;
404		goto err_rmu;
405	}
406	for_each_compatible_node(np, NULL, "fsl,srio-msg-unit") {
407		rmu_np[tmp] = np;
408		tmp++;
409	}
410
411	/*set up doobell node*/
412	np = of_find_compatible_node(NULL, NULL, "fsl,srio-dbell-unit");
413	if (!np) {
414		rc = -ENODEV;
415		goto err_dbell;
416	}
417	dbell = kzalloc(sizeof(struct fsl_rio_dbell), GFP_KERNEL);
418	if (!(dbell)) {
419		dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_dbell'\n");
420		rc = -ENOMEM;
421		goto err_dbell;
422	}
423	dbell->dev = &dev->dev;
424	dbell->bellirq = irq_of_parse_and_map(np, 1);
425	dev_info(&dev->dev, "bellirq: %d\n", dbell->bellirq);
426
427	aw = of_n_addr_cells(np);
428	dt_range = of_get_property(np, "reg", &rlen);
429	if (!dt_range) {
430		pr_err("%s: unable to find 'reg' property\n",
431			np->full_name);
432		rc = -ENOMEM;
433		goto err_pw;
434	}
435	range_start = of_read_number(dt_range, aw);
436	dbell->dbell_regs = (struct rio_dbell_regs *)(rmu_regs_win +
437				(u32)range_start);
438
439	/*set up port write node*/
440	np = of_find_compatible_node(NULL, NULL, "fsl,srio-port-write-unit");
441	if (!np) {
442		rc = -ENODEV;
443		goto err_pw;
444	}
445	pw = kzalloc(sizeof(struct fsl_rio_pw), GFP_KERNEL);
446	if (!(pw)) {
447		dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_pw'\n");
448		rc = -ENOMEM;
449		goto err_pw;
450	}
451	pw->dev = &dev->dev;
452	pw->pwirq = irq_of_parse_and_map(np, 0);
453	dev_info(&dev->dev, "pwirq: %d\n", pw->pwirq);
454	aw = of_n_addr_cells(np);
455	dt_range = of_get_property(np, "reg", &rlen);
456	if (!dt_range) {
457		pr_err("%s: unable to find 'reg' property\n",
458			np->full_name);
459		rc = -ENOMEM;
460		goto err;
461	}
462	range_start = of_read_number(dt_range, aw);
463	pw->pw_regs = (struct rio_pw_regs *)(rmu_regs_win + (u32)range_start);
464
465	/*set up ports node*/
466	for_each_child_of_node(dev->dev.of_node, np) {
467		port_index = of_get_property(np, "cell-index", NULL);
468		if (!port_index) {
469			dev_err(&dev->dev, "Can't get %s property 'cell-index'\n",
470					np->full_name);
471			continue;
472		}
473
474		dt_range = of_get_property(np, "ranges", &rlen);
475		if (!dt_range) {
476			dev_err(&dev->dev, "Can't get %s property 'ranges'\n",
477					np->full_name);
478			continue;
479		}
480
481		/* Get node address wide */
482		cell = of_get_property(np, "#address-cells", NULL);
483		if (cell)
484			aw = *cell;
485		else
486			aw = of_n_addr_cells(np);
487		/* Get node size wide */
488		cell = of_get_property(np, "#size-cells", NULL);
489		if (cell)
490			sw = *cell;
491		else
492			sw = of_n_size_cells(np);
493		/* Get parent address wide wide */
494		paw = of_n_addr_cells(np);
495		range_start = of_read_number(dt_range + aw, paw);
496		range_size = of_read_number(dt_range + aw + paw, sw);
497
498		dev_info(&dev->dev, "%s: LAW start 0x%016llx, size 0x%016llx.\n",
499				np->full_name, range_start, range_size);
500
501		port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
502		if (!port)
503			continue;
504
505		i = *port_index - 1;
506		port->index = (unsigned char)i;
507
508		priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
509		if (!priv) {
510			dev_err(&dev->dev, "Can't alloc memory for 'priv'\n");
511			kfree(port);
512			continue;
513		}
514
515		INIT_LIST_HEAD(&port->dbells);
516		port->iores.start = range_start;
517		port->iores.end = port->iores.start + range_size - 1;
518		port->iores.flags = IORESOURCE_MEM;
519		port->iores.name = "rio_io_win";
520
521		if (request_resource(&iomem_resource, &port->iores) < 0) {
522			dev_err(&dev->dev, "RIO: Error requesting master port region"
523				" 0x%016llx-0x%016llx\n",
524				(u64)port->iores.start, (u64)port->iores.end);
525				kfree(priv);
526				kfree(port);
527				continue;
528		}
529		sprintf(port->name, "RIO mport %d", i);
530
531		priv->dev = &dev->dev;
532		port->ops = ops;
533		port->priv = priv;
534		port->phys_efptr = 0x100;
535		priv->regs_win = rio_regs_win;
536
537		/* Probe the master port phy type */
538		ccsr = in_be32(priv->regs_win + RIO_CCSR + i*0x20);
539		port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL;
540		if (port->phy_type == RIO_PHY_PARALLEL) {
541			dev_err(&dev->dev, "RIO: Parallel PHY type, unsupported port type!\n");
542			release_resource(&port->iores);
543			kfree(priv);
544			kfree(port);
545			continue;
546		}
547		dev_info(&dev->dev, "RapidIO PHY type: Serial\n");
548		/* Checking the port training status */
549		if (in_be32((priv->regs_win + RIO_ESCSR + i*0x20)) & 1) {
550			dev_err(&dev->dev, "Port %d is not ready. "
551			"Try to restart connection...\n", i);
552			/* Disable ports */
553			out_be32(priv->regs_win
554				+ RIO_CCSR + i*0x20, 0);
555			/* Set 1x lane */
556			setbits32(priv->regs_win
557				+ RIO_CCSR + i*0x20, 0x02000000);
558			/* Enable ports */
559			setbits32(priv->regs_win
560				+ RIO_CCSR + i*0x20, 0x00600000);
561			msleep(100);
562			if (in_be32((priv->regs_win
563					+ RIO_ESCSR + i*0x20)) & 1) {
564				dev_err(&dev->dev,
565					"Port %d restart failed.\n", i);
566				release_resource(&port->iores);
567				kfree(priv);
568				kfree(port);
569				continue;
570			}
571			dev_info(&dev->dev, "Port %d restart success!\n", i);
572		}
573		fsl_rio_info(&dev->dev, ccsr);
574
575		port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
576					& RIO_PEF_CTLS) >> 4;
577		dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
578				port->sys_size ? 65536 : 256);
579
580		if (rio_register_mport(port)) {
581			release_resource(&port->iores);
582			kfree(priv);
583			kfree(port);
584			continue;
585		}
586		if (port->host_deviceid >= 0)
587			out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST |
588				RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED);
589		else
590			out_be32(priv->regs_win + RIO_GCCSR,
591				RIO_PORT_GEN_MASTER);
592
593		priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
594			+ ((i == 0) ? RIO_ATMU_REGS_PORT1_OFFSET :
595			RIO_ATMU_REGS_PORT2_OFFSET));
596
597		priv->maint_atmu_regs = priv->atmu_regs + 1;
598
599		/* Set to receive any dist ID for serial RapidIO controller. */
600		if (port->phy_type == RIO_PHY_SERIAL)
601			out_be32((priv->regs_win
602				+ RIO_ISR_AACR + i*0x80), RIO_ISR_AACR_AA);
603
604		/* Configure maintenance transaction window */
605		out_be32(&priv->maint_atmu_regs->rowbar,
606			port->iores.start >> 12);
607		out_be32(&priv->maint_atmu_regs->rowar,
608			 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
609
610		priv->maint_win = ioremap(port->iores.start,
611				RIO_MAINT_WIN_SIZE);
612
613		rio_law_start = range_start;
614
615		fsl_rio_setup_rmu(port, rmu_np[i]);
616
617		dbell->mport[i] = port;
618
619		active_ports++;
620	}
621
622	if (!active_ports) {
623		rc = -ENOLINK;
624		goto err;
625	}
626
627	fsl_rio_doorbell_init(dbell);
628	fsl_rio_port_write_init(pw);
629
630	return 0;
631err:
632	kfree(pw);
633err_pw:
634	kfree(dbell);
635err_dbell:
636	iounmap(rmu_regs_win);
637err_rmu:
638	kfree(ops);
639err_ops:
640	iounmap(rio_regs_win);
641err_rio_regs:
642	return rc;
643}
644
645/* The probe function for RapidIO peer-to-peer network.
646 */
647static int __devinit fsl_of_rio_rpn_probe(struct platform_device *dev)
648{
649	printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n",
650			dev->dev.of_node->full_name);
651
652	return fsl_rio_setup(dev);
653};
654
655static const struct of_device_id fsl_of_rio_rpn_ids[] = {
656	{
657		.compatible = "fsl,srio",
658	},
659	{},
660};
661
662static struct platform_driver fsl_of_rio_rpn_driver = {
663	.driver = {
664		.name = "fsl-of-rio",
665		.owner = THIS_MODULE,
666		.of_match_table = fsl_of_rio_rpn_ids,
667	},
668	.probe = fsl_of_rio_rpn_probe,
669};
670
671static __init int fsl_of_rio_rpn_init(void)
672{
673	return platform_driver_register(&fsl_of_rio_rpn_driver);
674}
675
676subsys_initcall(fsl_of_rio_rpn_init);
677