1/*
2 * SH4-202 Setup
3 *
4 *  Copyright (C) 2006  Paul Mundt
5 *  Copyright (C) 2009  Magnus Damm
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License.  See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#include <linux/platform_device.h>
12#include <linux/init.h>
13#include <linux/serial.h>
14#include <linux/serial_sci.h>
15#include <linux/sh_timer.h>
16#include <linux/io.h>
17
18static struct plat_sci_port scif0_platform_data = {
19	.mapbase	= 0xffe80000,
20	.flags		= UPF_BOOT_AUTOCONF,
21	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
22	.scbrr_algo_id	= SCBRR_ALGO_2,
23	.type		= PORT_SCIF,
24	.irqs		= { 40, 41, 43, 42 },
25};
26
27static struct platform_device scif0_device = {
28	.name		= "sh-sci",
29	.id		= 0,
30	.dev		= {
31		.platform_data	= &scif0_platform_data,
32	},
33};
34
35static struct sh_timer_config tmu0_platform_data = {
36	.channel_offset = 0x04,
37	.timer_bit = 0,
38	.clockevent_rating = 200,
39};
40
41static struct resource tmu0_resources[] = {
42	[0] = {
43		.start	= 0xffd80008,
44		.end	= 0xffd80013,
45		.flags	= IORESOURCE_MEM,
46	},
47	[1] = {
48		.start	= 16,
49		.flags	= IORESOURCE_IRQ,
50	},
51};
52
53static struct platform_device tmu0_device = {
54	.name		= "sh_tmu",
55	.id		= 0,
56	.dev = {
57		.platform_data	= &tmu0_platform_data,
58	},
59	.resource	= tmu0_resources,
60	.num_resources	= ARRAY_SIZE(tmu0_resources),
61};
62
63static struct sh_timer_config tmu1_platform_data = {
64	.channel_offset = 0x10,
65	.timer_bit = 1,
66	.clocksource_rating = 200,
67};
68
69static struct resource tmu1_resources[] = {
70	[0] = {
71		.start	= 0xffd80014,
72		.end	= 0xffd8001f,
73		.flags	= IORESOURCE_MEM,
74	},
75	[1] = {
76		.start	= 17,
77		.flags	= IORESOURCE_IRQ,
78	},
79};
80
81static struct platform_device tmu1_device = {
82	.name		= "sh_tmu",
83	.id		= 1,
84	.dev = {
85		.platform_data	= &tmu1_platform_data,
86	},
87	.resource	= tmu1_resources,
88	.num_resources	= ARRAY_SIZE(tmu1_resources),
89};
90
91static struct sh_timer_config tmu2_platform_data = {
92	.channel_offset = 0x1c,
93	.timer_bit = 2,
94};
95
96static struct resource tmu2_resources[] = {
97	[0] = {
98		.start	= 0xffd80020,
99		.end	= 0xffd8002f,
100		.flags	= IORESOURCE_MEM,
101	},
102	[1] = {
103		.start	= 18,
104		.flags	= IORESOURCE_IRQ,
105	},
106};
107
108static struct platform_device tmu2_device = {
109	.name		= "sh_tmu",
110	.id		= 2,
111	.dev = {
112		.platform_data	= &tmu2_platform_data,
113	},
114	.resource	= tmu2_resources,
115	.num_resources	= ARRAY_SIZE(tmu2_resources),
116};
117
118static struct platform_device *sh4202_devices[] __initdata = {
119	&scif0_device,
120	&tmu0_device,
121	&tmu1_device,
122	&tmu2_device,
123};
124
125static int __init sh4202_devices_setup(void)
126{
127	return platform_add_devices(sh4202_devices,
128				    ARRAY_SIZE(sh4202_devices));
129}
130arch_initcall(sh4202_devices_setup);
131
132static struct platform_device *sh4202_early_devices[] __initdata = {
133	&scif0_device,
134	&tmu0_device,
135	&tmu1_device,
136	&tmu2_device,
137};
138
139void __init plat_early_device_setup(void)
140{
141	early_platform_add_devices(sh4202_early_devices,
142				   ARRAY_SIZE(sh4202_early_devices));
143}
144
145enum {
146	UNUSED = 0,
147
148	/* interrupt sources */
149	IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
150	HUDI, TMU0, TMU1, TMU2, RTC, SCIF, WDT,
151};
152
153static struct intc_vect vectors[] __initdata = {
154	INTC_VECT(HUDI, 0x600),
155	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
156	INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
157	INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
158	INTC_VECT(RTC, 0x4c0),
159	INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
160	INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
161	INTC_VECT(WDT, 0x560),
162};
163
164static struct intc_prio_reg prio_registers[] __initdata = {
165	{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
166	{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, 0, 0, 0 } },
167	{ 0xffd0000c, 0, 16, 4, /* IPRC */ { 0, 0, SCIF, HUDI } },
168	{ 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
169};
170
171static DECLARE_INTC_DESC(intc_desc, "sh4-202", vectors, NULL,
172			 NULL, prio_registers, NULL);
173
174static struct intc_vect vectors_irlm[] __initdata = {
175	INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
176	INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
177};
178
179static DECLARE_INTC_DESC(intc_desc_irlm, "sh4-202_irlm", vectors_irlm, NULL,
180			 NULL, prio_registers, NULL);
181
182void __init plat_irq_setup(void)
183{
184	register_intc_controller(&intc_desc);
185}
186
187#define INTC_ICR	0xffd00000UL
188#define INTC_ICR_IRLM   (1<<7)
189
190void __init plat_irq_setup_pins(int mode)
191{
192	switch (mode) {
193	case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
194		__raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
195		register_intc_controller(&intc_desc_irlm);
196		break;
197	default:
198		BUG();
199	}
200}
201