1/*
2 * SH7722 Setup
3 *
4 *  Copyright (C) 2006 - 2008  Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License.  See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/init.h>
11#include <linux/mm.h>
12#include <linux/platform_device.h>
13#include <linux/serial.h>
14#include <linux/serial_sci.h>
15#include <linux/sh_timer.h>
16#include <linux/uio_driver.h>
17#include <linux/usb/m66592.h>
18
19#include <asm/clock.h>
20#include <asm/mmzone.h>
21#include <asm/siu.h>
22
23#include <cpu/dma-register.h>
24#include <cpu/sh7722.h>
25#include <cpu/serial.h>
26
27static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
28	{
29		.slave_id	= SHDMA_SLAVE_SCIF0_TX,
30		.addr		= 0xffe0000c,
31		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
32		.mid_rid	= 0x21,
33	}, {
34		.slave_id	= SHDMA_SLAVE_SCIF0_RX,
35		.addr		= 0xffe00014,
36		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
37		.mid_rid	= 0x22,
38	}, {
39		.slave_id	= SHDMA_SLAVE_SCIF1_TX,
40		.addr		= 0xffe1000c,
41		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
42		.mid_rid	= 0x25,
43	}, {
44		.slave_id	= SHDMA_SLAVE_SCIF1_RX,
45		.addr		= 0xffe10014,
46		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
47		.mid_rid	= 0x26,
48	}, {
49		.slave_id	= SHDMA_SLAVE_SCIF2_TX,
50		.addr		= 0xffe2000c,
51		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
52		.mid_rid	= 0x29,
53	}, {
54		.slave_id	= SHDMA_SLAVE_SCIF2_RX,
55		.addr		= 0xffe20014,
56		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
57		.mid_rid	= 0x2a,
58	}, {
59		.slave_id	= SHDMA_SLAVE_SIUA_TX,
60		.addr		= 0xa454c098,
61		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
62		.mid_rid	= 0xb1,
63	}, {
64		.slave_id	= SHDMA_SLAVE_SIUA_RX,
65		.addr		= 0xa454c090,
66		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
67		.mid_rid	= 0xb2,
68	}, {
69		.slave_id	= SHDMA_SLAVE_SIUB_TX,
70		.addr		= 0xa454c09c,
71		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
72		.mid_rid	= 0xb5,
73	}, {
74		.slave_id	= SHDMA_SLAVE_SIUB_RX,
75		.addr		= 0xa454c094,
76		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
77		.mid_rid	= 0xb6,
78	}, {
79		.slave_id	= SHDMA_SLAVE_SDHI0_TX,
80		.addr		= 0x04ce0030,
81		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
82		.mid_rid	= 0xc1,
83	}, {
84		.slave_id	= SHDMA_SLAVE_SDHI0_RX,
85		.addr		= 0x04ce0030,
86		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
87		.mid_rid	= 0xc2,
88	},
89};
90
91static const struct sh_dmae_channel sh7722_dmae_channels[] = {
92	{
93		.offset = 0,
94		.dmars = 0,
95		.dmars_bit = 0,
96	}, {
97		.offset = 0x10,
98		.dmars = 0,
99		.dmars_bit = 8,
100	}, {
101		.offset = 0x20,
102		.dmars = 4,
103		.dmars_bit = 0,
104	}, {
105		.offset = 0x30,
106		.dmars = 4,
107		.dmars_bit = 8,
108	}, {
109		.offset = 0x50,
110		.dmars = 8,
111		.dmars_bit = 0,
112	}, {
113		.offset = 0x60,
114		.dmars = 8,
115		.dmars_bit = 8,
116	}
117};
118
119static const unsigned int ts_shift[] = TS_SHIFT;
120
121static struct sh_dmae_pdata dma_platform_data = {
122	.slave		= sh7722_dmae_slaves,
123	.slave_num	= ARRAY_SIZE(sh7722_dmae_slaves),
124	.channel	= sh7722_dmae_channels,
125	.channel_num	= ARRAY_SIZE(sh7722_dmae_channels),
126	.ts_low_shift	= CHCR_TS_LOW_SHIFT,
127	.ts_low_mask	= CHCR_TS_LOW_MASK,
128	.ts_high_shift	= CHCR_TS_HIGH_SHIFT,
129	.ts_high_mask	= CHCR_TS_HIGH_MASK,
130	.ts_shift	= ts_shift,
131	.ts_shift_num	= ARRAY_SIZE(ts_shift),
132	.dmaor_init	= DMAOR_INIT,
133};
134
135static struct resource sh7722_dmae_resources[] = {
136	[0] = {
137		/* Channel registers and DMAOR */
138		.start	= 0xfe008020,
139		.end	= 0xfe00808f,
140		.flags	= IORESOURCE_MEM,
141	},
142	[1] = {
143		/* DMARSx */
144		.start	= 0xfe009000,
145		.end	= 0xfe00900b,
146		.flags	= IORESOURCE_MEM,
147	},
148	{
149		.name	= "error_irq",
150		.start	= 78,
151		.end	= 78,
152		.flags	= IORESOURCE_IRQ,
153	},
154	{
155		/* IRQ for channels 0-3 */
156		.start	= 48,
157		.end	= 51,
158		.flags	= IORESOURCE_IRQ,
159	},
160	{
161		/* IRQ for channels 4-5 */
162		.start	= 76,
163		.end	= 77,
164		.flags	= IORESOURCE_IRQ,
165	},
166};
167
168struct platform_device dma_device = {
169	.name		= "sh-dma-engine",
170	.id		= -1,
171	.resource	= sh7722_dmae_resources,
172	.num_resources	= ARRAY_SIZE(sh7722_dmae_resources),
173	.dev		= {
174		.platform_data	= &dma_platform_data,
175	},
176};
177
178/* Serial */
179static struct plat_sci_port scif0_platform_data = {
180	.mapbase        = 0xffe00000,
181	.flags          = UPF_BOOT_AUTOCONF,
182	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
183	.scbrr_algo_id	= SCBRR_ALGO_2,
184	.type           = PORT_SCIF,
185	.irqs           = { 80, 80, 80, 80 },
186	.ops		= &sh7722_sci_port_ops,
187	.regtype	= SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
188};
189
190static struct platform_device scif0_device = {
191	.name		= "sh-sci",
192	.id		= 0,
193	.dev		= {
194		.platform_data	= &scif0_platform_data,
195	},
196};
197
198static struct plat_sci_port scif1_platform_data = {
199	.mapbase        = 0xffe10000,
200	.flags          = UPF_BOOT_AUTOCONF,
201	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
202	.scbrr_algo_id	= SCBRR_ALGO_2,
203	.type           = PORT_SCIF,
204	.irqs           = { 81, 81, 81, 81 },
205	.ops		= &sh7722_sci_port_ops,
206	.regtype	= SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
207};
208
209static struct platform_device scif1_device = {
210	.name		= "sh-sci",
211	.id		= 1,
212	.dev		= {
213		.platform_data	= &scif1_platform_data,
214	},
215};
216
217static struct plat_sci_port scif2_platform_data = {
218	.mapbase        = 0xffe20000,
219	.flags          = UPF_BOOT_AUTOCONF,
220	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
221	.scbrr_algo_id	= SCBRR_ALGO_2,
222	.type           = PORT_SCIF,
223	.irqs           = { 82, 82, 82, 82 },
224	.ops		= &sh7722_sci_port_ops,
225	.regtype	= SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
226};
227
228static struct platform_device scif2_device = {
229	.name		= "sh-sci",
230	.id		= 2,
231	.dev		= {
232		.platform_data	= &scif2_platform_data,
233	},
234};
235
236static struct resource rtc_resources[] = {
237	[0] = {
238		.start	= 0xa465fec0,
239		.end	= 0xa465fec0 + 0x58 - 1,
240		.flags	= IORESOURCE_IO,
241	},
242	[1] = {
243		/* Period IRQ */
244		.start	= 45,
245		.flags	= IORESOURCE_IRQ,
246	},
247	[2] = {
248		/* Carry IRQ */
249		.start	= 46,
250		.flags	= IORESOURCE_IRQ,
251	},
252	[3] = {
253		/* Alarm IRQ */
254		.start	= 44,
255		.flags	= IORESOURCE_IRQ,
256	},
257};
258
259static struct platform_device rtc_device = {
260	.name		= "sh-rtc",
261	.id		= -1,
262	.num_resources	= ARRAY_SIZE(rtc_resources),
263	.resource	= rtc_resources,
264};
265
266static struct m66592_platdata usbf_platdata = {
267	.on_chip = 1,
268};
269
270static struct resource usbf_resources[] = {
271	[0] = {
272		.name	= "USBF",
273		.start	= 0x04480000,
274		.end	= 0x044800FF,
275		.flags	= IORESOURCE_MEM,
276	},
277	[1] = {
278		.start	= 65,
279		.end	= 65,
280		.flags	= IORESOURCE_IRQ,
281	},
282};
283
284static struct platform_device usbf_device = {
285	.name		= "m66592_udc",
286	.id             = 0, /* "usbf0" clock */
287	.dev = {
288		.dma_mask		= NULL,
289		.coherent_dma_mask	= 0xffffffff,
290		.platform_data		= &usbf_platdata,
291	},
292	.num_resources	= ARRAY_SIZE(usbf_resources),
293	.resource	= usbf_resources,
294};
295
296static struct resource iic_resources[] = {
297	[0] = {
298		.name	= "IIC",
299		.start  = 0x04470000,
300		.end    = 0x04470017,
301		.flags  = IORESOURCE_MEM,
302	},
303	[1] = {
304		.start  = 96,
305		.end    = 99,
306		.flags  = IORESOURCE_IRQ,
307       },
308};
309
310static struct platform_device iic_device = {
311	.name           = "i2c-sh_mobile",
312	.id             = 0, /* "i2c0" clock */
313	.num_resources  = ARRAY_SIZE(iic_resources),
314	.resource       = iic_resources,
315};
316
317static struct uio_info vpu_platform_data = {
318	.name = "VPU4",
319	.version = "0",
320	.irq = 60,
321};
322
323static struct resource vpu_resources[] = {
324	[0] = {
325		.name	= "VPU",
326		.start	= 0xfe900000,
327		.end	= 0xfe9022eb,
328		.flags	= IORESOURCE_MEM,
329	},
330	[1] = {
331		/* place holder for contiguous memory */
332	},
333};
334
335static struct platform_device vpu_device = {
336	.name		= "uio_pdrv_genirq",
337	.id		= 0,
338	.dev = {
339		.platform_data	= &vpu_platform_data,
340	},
341	.resource	= vpu_resources,
342	.num_resources	= ARRAY_SIZE(vpu_resources),
343};
344
345static struct uio_info veu_platform_data = {
346	.name = "VEU",
347	.version = "0",
348	.irq = 54,
349};
350
351static struct resource veu_resources[] = {
352	[0] = {
353		.name	= "VEU",
354		.start	= 0xfe920000,
355		.end	= 0xfe9200b7,
356		.flags	= IORESOURCE_MEM,
357	},
358	[1] = {
359		/* place holder for contiguous memory */
360	},
361};
362
363static struct platform_device veu_device = {
364	.name		= "uio_pdrv_genirq",
365	.id		= 1,
366	.dev = {
367		.platform_data	= &veu_platform_data,
368	},
369	.resource	= veu_resources,
370	.num_resources	= ARRAY_SIZE(veu_resources),
371};
372
373static struct uio_info jpu_platform_data = {
374	.name = "JPU",
375	.version = "0",
376	.irq = 27,
377};
378
379static struct resource jpu_resources[] = {
380	[0] = {
381		.name	= "JPU",
382		.start	= 0xfea00000,
383		.end	= 0xfea102d3,
384		.flags	= IORESOURCE_MEM,
385	},
386	[1] = {
387		/* place holder for contiguous memory */
388	},
389};
390
391static struct platform_device jpu_device = {
392	.name		= "uio_pdrv_genirq",
393	.id		= 2,
394	.dev = {
395		.platform_data	= &jpu_platform_data,
396	},
397	.resource	= jpu_resources,
398	.num_resources	= ARRAY_SIZE(jpu_resources),
399};
400
401static struct sh_timer_config cmt_platform_data = {
402	.channel_offset = 0x60,
403	.timer_bit = 5,
404	.clockevent_rating = 125,
405	.clocksource_rating = 125,
406};
407
408static struct resource cmt_resources[] = {
409	[0] = {
410		.start	= 0x044a0060,
411		.end	= 0x044a006b,
412		.flags	= IORESOURCE_MEM,
413	},
414	[1] = {
415		.start	= 104,
416		.flags	= IORESOURCE_IRQ,
417	},
418};
419
420static struct platform_device cmt_device = {
421	.name		= "sh_cmt",
422	.id		= 0,
423	.dev = {
424		.platform_data	= &cmt_platform_data,
425	},
426	.resource	= cmt_resources,
427	.num_resources	= ARRAY_SIZE(cmt_resources),
428};
429
430static struct sh_timer_config tmu0_platform_data = {
431	.channel_offset = 0x04,
432	.timer_bit = 0,
433	.clockevent_rating = 200,
434};
435
436static struct resource tmu0_resources[] = {
437	[0] = {
438		.start	= 0xffd80008,
439		.end	= 0xffd80013,
440		.flags	= IORESOURCE_MEM,
441	},
442	[1] = {
443		.start	= 16,
444		.flags	= IORESOURCE_IRQ,
445	},
446};
447
448static struct platform_device tmu0_device = {
449	.name		= "sh_tmu",
450	.id		= 0,
451	.dev = {
452		.platform_data	= &tmu0_platform_data,
453	},
454	.resource	= tmu0_resources,
455	.num_resources	= ARRAY_SIZE(tmu0_resources),
456};
457
458static struct sh_timer_config tmu1_platform_data = {
459	.channel_offset = 0x10,
460	.timer_bit = 1,
461	.clocksource_rating = 200,
462};
463
464static struct resource tmu1_resources[] = {
465	[0] = {
466		.start	= 0xffd80014,
467		.end	= 0xffd8001f,
468		.flags	= IORESOURCE_MEM,
469	},
470	[1] = {
471		.start	= 17,
472		.flags	= IORESOURCE_IRQ,
473	},
474};
475
476static struct platform_device tmu1_device = {
477	.name		= "sh_tmu",
478	.id		= 1,
479	.dev = {
480		.platform_data	= &tmu1_platform_data,
481	},
482	.resource	= tmu1_resources,
483	.num_resources	= ARRAY_SIZE(tmu1_resources),
484};
485
486static struct sh_timer_config tmu2_platform_data = {
487	.channel_offset = 0x1c,
488	.timer_bit = 2,
489};
490
491static struct resource tmu2_resources[] = {
492	[0] = {
493		.start	= 0xffd80020,
494		.end	= 0xffd8002b,
495		.flags	= IORESOURCE_MEM,
496	},
497	[1] = {
498		.start	= 18,
499		.flags	= IORESOURCE_IRQ,
500	},
501};
502
503static struct platform_device tmu2_device = {
504	.name		= "sh_tmu",
505	.id		= 2,
506	.dev = {
507		.platform_data	= &tmu2_platform_data,
508	},
509	.resource	= tmu2_resources,
510	.num_resources	= ARRAY_SIZE(tmu2_resources),
511};
512
513static struct siu_platform siu_platform_data = {
514	.dma_dev	= &dma_device.dev,
515	.dma_slave_tx_a	= SHDMA_SLAVE_SIUA_TX,
516	.dma_slave_rx_a	= SHDMA_SLAVE_SIUA_RX,
517	.dma_slave_tx_b	= SHDMA_SLAVE_SIUB_TX,
518	.dma_slave_rx_b	= SHDMA_SLAVE_SIUB_RX,
519};
520
521static struct resource siu_resources[] = {
522	[0] = {
523		.start	= 0xa4540000,
524		.end	= 0xa454c10f,
525		.flags	= IORESOURCE_MEM,
526	},
527	[1] = {
528		.start	= 108,
529		.flags	= IORESOURCE_IRQ,
530	},
531};
532
533static struct platform_device siu_device = {
534	.name		= "siu-pcm-audio",
535	.id		= -1,
536	.dev = {
537		.platform_data	= &siu_platform_data,
538	},
539	.resource	= siu_resources,
540	.num_resources	= ARRAY_SIZE(siu_resources),
541};
542
543static struct platform_device *sh7722_devices[] __initdata = {
544	&scif0_device,
545	&scif1_device,
546	&scif2_device,
547	&cmt_device,
548	&tmu0_device,
549	&tmu1_device,
550	&tmu2_device,
551	&rtc_device,
552	&usbf_device,
553	&iic_device,
554	&vpu_device,
555	&veu_device,
556	&jpu_device,
557	&siu_device,
558	&dma_device,
559};
560
561static int __init sh7722_devices_setup(void)
562{
563	platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
564	platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
565	platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
566
567	return platform_add_devices(sh7722_devices,
568				    ARRAY_SIZE(sh7722_devices));
569}
570arch_initcall(sh7722_devices_setup);
571
572static struct platform_device *sh7722_early_devices[] __initdata = {
573	&scif0_device,
574	&scif1_device,
575	&scif2_device,
576	&cmt_device,
577	&tmu0_device,
578	&tmu1_device,
579	&tmu2_device,
580};
581
582void __init plat_early_device_setup(void)
583{
584	early_platform_add_devices(sh7722_early_devices,
585				   ARRAY_SIZE(sh7722_early_devices));
586}
587
588enum {
589	UNUSED=0,
590	ENABLED,
591	DISABLED,
592
593	/* interrupt sources */
594	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
595	HUDI,
596	SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
597	RTC_ATI, RTC_PRI, RTC_CUI,
598	DMAC0, DMAC1, DMAC2, DMAC3,
599	VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
600	VPU, TPU,
601	USB_USBI0, USB_USBI1,
602	DMAC4, DMAC5, DMAC_DADERR,
603	KEYSC,
604	SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
605	FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
606	I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
607	CMT, TSIF, SIU, TWODG,
608	TMU0, TMU1, TMU2,
609	IRDA, JPU, LCDC,
610
611	/* interrupt groups */
612	SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
613};
614
615static struct intc_vect vectors[] __initdata = {
616	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
617	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
618	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
619	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
620	INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
621	INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
622	INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
623	INTC_VECT(RTC_CUI, 0x7c0),
624	INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
625	INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
626	INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
627	INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
628	INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
629	INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
630	INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
631	INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
632	INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
633	INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
634	INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
635	INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
636	INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
637	INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
638	INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
639	INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
640	INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
641	INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
642	INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
643	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
644	INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
645	INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
646};
647
648static struct intc_group groups[] __initdata = {
649	INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
650	INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
651	INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
652	INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
653	INTC_GROUP(USB, USB_USBI0, USB_USBI1),
654	INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
655	INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
656		   FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
657	INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
658};
659
660static struct intc_mask_reg mask_registers[] __initdata = {
661	{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
662	  { } },
663	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
664	  { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
665	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
666	  { 0, 0, 0, VPU, } },
667	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
668	  { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
669	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
670	  { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
671	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
672	  { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
673	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
674	  { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
675	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
676	  { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
677	    FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
678	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
679	  { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
680	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
681	  { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
682	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
683	  { } },
684	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
685	  { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
686	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
687	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
688};
689
690static struct intc_prio_reg prio_registers[] __initdata = {
691	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
692	{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
693	{ 0xa4080008, 0, 16, 4, /* IPRC */ { } },
694	{ 0xa408000c, 0, 16, 4, /* IPRD */ { } },
695	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
696	{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
697	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
698	{ 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
699	{ 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
700	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
701	{ 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
702	{ 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
703	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
704	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
705};
706
707static struct intc_sense_reg sense_registers[] __initdata = {
708	{ 0xa414001c, 16, 2, /* ICR1 */
709	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
710};
711
712static struct intc_mask_reg ack_registers[] __initdata = {
713	{ 0xa4140024, 0, 8, /* INTREQ00 */
714	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
715};
716
717static struct intc_desc intc_desc __initdata = {
718	.name = "sh7722",
719	.force_enable = ENABLED,
720	.force_disable = DISABLED,
721	.hw = INTC_HW_DESC(vectors, groups, mask_registers,
722			   prio_registers, sense_registers, ack_registers),
723};
724
725void __init plat_irq_setup(void)
726{
727	register_intc_controller(&intc_desc);
728}
729
730void __init plat_mem_setup(void)
731{
732	/* Register the URAM space as Node 1 */
733	setup_bootmem_node(1, 0x055f0000, 0x05610000);
734}
735