1/* 2 * sx8.c: Driver for Promise SATA SX8 looks-like-I2O hardware 3 * 4 * Copyright 2004-2005 Red Hat, Inc. 5 * 6 * Author/maintainer: Jeff Garzik <jgarzik@pobox.com> 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 13#include <linux/kernel.h> 14#include <linux/module.h> 15#include <linux/init.h> 16#include <linux/pci.h> 17#include <linux/slab.h> 18#include <linux/spinlock.h> 19#include <linux/blkdev.h> 20#include <linux/sched.h> 21#include <linux/interrupt.h> 22#include <linux/compiler.h> 23#include <linux/workqueue.h> 24#include <linux/bitops.h> 25#include <linux/delay.h> 26#include <linux/time.h> 27#include <linux/hdreg.h> 28#include <linux/dma-mapping.h> 29#include <linux/completion.h> 30#include <linux/scatterlist.h> 31#include <asm/io.h> 32#include <asm/uaccess.h> 33 34#if 0 35#define CARM_DEBUG 36#define CARM_VERBOSE_DEBUG 37#else 38#undef CARM_DEBUG 39#undef CARM_VERBOSE_DEBUG 40#endif 41#undef CARM_NDEBUG 42 43#define DRV_NAME "sx8" 44#define DRV_VERSION "1.0" 45#define PFX DRV_NAME ": " 46 47MODULE_AUTHOR("Jeff Garzik"); 48MODULE_LICENSE("GPL"); 49MODULE_DESCRIPTION("Promise SATA SX8 block driver"); 50MODULE_VERSION(DRV_VERSION); 51 52/* 53 * SX8 hardware has a single message queue for all ATA ports. 54 * When this driver was written, the hardware (firmware?) would 55 * corrupt data eventually, if more than one request was outstanding. 56 * As one can imagine, having 8 ports bottlenecking on a single 57 * command hurts performance. 58 * 59 * Based on user reports, later versions of the hardware (firmware?) 60 * seem to be able to survive with more than one command queued. 61 * 62 * Therefore, we default to the safe option -- 1 command -- but 63 * allow the user to increase this. 64 * 65 * SX8 should be able to support up to ~60 queued commands (CARM_MAX_REQ), 66 * but problems seem to occur when you exceed ~30, even on newer hardware. 67 */ 68static int max_queue = 1; 69module_param(max_queue, int, 0444); 70MODULE_PARM_DESC(max_queue, "Maximum number of queued commands. (min==1, max==30, safe==1)"); 71 72 73#define NEXT_RESP(idx) ((idx + 1) % RMSG_Q_LEN) 74 75/* 0xf is just arbitrary, non-zero noise; this is sorta like poisoning */ 76#define TAG_ENCODE(tag) (((tag) << 16) | 0xf) 77#define TAG_DECODE(tag) (((tag) >> 16) & 0x1f) 78#define TAG_VALID(tag) ((((tag) & 0xf) == 0xf) && (TAG_DECODE(tag) < 32)) 79 80/* note: prints function name for you */ 81#ifdef CARM_DEBUG 82#define DPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args) 83#ifdef CARM_VERBOSE_DEBUG 84#define VPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args) 85#else 86#define VPRINTK(fmt, args...) 87#endif /* CARM_VERBOSE_DEBUG */ 88#else 89#define DPRINTK(fmt, args...) 90#define VPRINTK(fmt, args...) 91#endif /* CARM_DEBUG */ 92 93#ifdef CARM_NDEBUG 94#define assert(expr) 95#else 96#define assert(expr) \ 97 if(unlikely(!(expr))) { \ 98 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \ 99 #expr, __FILE__, __func__, __LINE__); \ 100 } 101#endif 102 103/* defines only for the constants which don't work well as enums */ 104struct carm_host; 105 106enum { 107 /* adapter-wide limits */ 108 CARM_MAX_PORTS = 8, 109 CARM_SHM_SIZE = (4096 << 7), 110 CARM_MINORS_PER_MAJOR = 256 / CARM_MAX_PORTS, 111 CARM_MAX_WAIT_Q = CARM_MAX_PORTS + 1, 112 113 /* command message queue limits */ 114 CARM_MAX_REQ = 64, /* max command msgs per host */ 115 CARM_MSG_LOW_WATER = (CARM_MAX_REQ / 4), /* refill mark */ 116 117 /* S/G limits, host-wide and per-request */ 118 CARM_MAX_REQ_SG = 32, /* max s/g entries per request */ 119 CARM_MAX_HOST_SG = 600, /* max s/g entries per host */ 120 CARM_SG_LOW_WATER = (CARM_MAX_HOST_SG / 4), /* re-fill mark */ 121 122 /* hardware registers */ 123 CARM_IHQP = 0x1c, 124 CARM_INT_STAT = 0x10, /* interrupt status */ 125 CARM_INT_MASK = 0x14, /* interrupt mask */ 126 CARM_HMUC = 0x18, /* host message unit control */ 127 RBUF_ADDR_LO = 0x20, /* response msg DMA buf low 32 bits */ 128 RBUF_ADDR_HI = 0x24, /* response msg DMA buf high 32 bits */ 129 RBUF_BYTE_SZ = 0x28, 130 CARM_RESP_IDX = 0x2c, 131 CARM_CMS0 = 0x30, /* command message size reg 0 */ 132 CARM_LMUC = 0x48, 133 CARM_HMPHA = 0x6c, 134 CARM_INITC = 0xb5, 135 136 /* bits in CARM_INT_{STAT,MASK} */ 137 INT_RESERVED = 0xfffffff0, 138 INT_WATCHDOG = (1 << 3), /* watchdog timer */ 139 INT_Q_OVERFLOW = (1 << 2), /* cmd msg q overflow */ 140 INT_Q_AVAILABLE = (1 << 1), /* cmd msg q has free space */ 141 INT_RESPONSE = (1 << 0), /* response msg available */ 142 INT_ACK_MASK = INT_WATCHDOG | INT_Q_OVERFLOW, 143 INT_DEF_MASK = INT_RESERVED | INT_Q_OVERFLOW | 144 INT_RESPONSE, 145 146 /* command messages, and related register bits */ 147 CARM_HAVE_RESP = 0x01, 148 CARM_MSG_READ = 1, 149 CARM_MSG_WRITE = 2, 150 CARM_MSG_VERIFY = 3, 151 CARM_MSG_GET_CAPACITY = 4, 152 CARM_MSG_FLUSH = 5, 153 CARM_MSG_IOCTL = 6, 154 CARM_MSG_ARRAY = 8, 155 CARM_MSG_MISC = 9, 156 CARM_CME = (1 << 2), 157 CARM_RME = (1 << 1), 158 CARM_WZBC = (1 << 0), 159 CARM_RMI = (1 << 0), 160 CARM_Q_FULL = (1 << 3), 161 CARM_MSG_SIZE = 288, 162 CARM_Q_LEN = 48, 163 164 /* CARM_MSG_IOCTL messages */ 165 CARM_IOC_SCAN_CHAN = 5, /* scan channels for devices */ 166 CARM_IOC_GET_TCQ = 13, /* get tcq/ncq depth */ 167 CARM_IOC_SET_TCQ = 14, /* set tcq/ncq depth */ 168 169 IOC_SCAN_CHAN_NODEV = 0x1f, 170 IOC_SCAN_CHAN_OFFSET = 0x40, 171 172 /* CARM_MSG_ARRAY messages */ 173 CARM_ARRAY_INFO = 0, 174 175 ARRAY_NO_EXIST = (1 << 31), 176 177 /* response messages */ 178 RMSG_SZ = 8, /* sizeof(struct carm_response) */ 179 RMSG_Q_LEN = 48, /* resp. msg list length */ 180 RMSG_OK = 1, /* bit indicating msg was successful */ 181 /* length of entire resp. msg buffer */ 182 RBUF_LEN = RMSG_SZ * RMSG_Q_LEN, 183 184 PDC_SHM_SIZE = (4096 << 7), /* length of entire h/w buffer */ 185 186 /* CARM_MSG_MISC messages */ 187 MISC_GET_FW_VER = 2, 188 MISC_ALLOC_MEM = 3, 189 MISC_SET_TIME = 5, 190 191 /* MISC_GET_FW_VER feature bits */ 192 FW_VER_4PORT = (1 << 2), /* 1=4 ports, 0=8 ports */ 193 FW_VER_NON_RAID = (1 << 1), /* 1=non-RAID firmware, 0=RAID */ 194 FW_VER_ZCR = (1 << 0), /* zero channel RAID (whatever that is) */ 195 196 /* carm_host flags */ 197 FL_NON_RAID = FW_VER_NON_RAID, 198 FL_4PORT = FW_VER_4PORT, 199 FL_FW_VER_MASK = (FW_VER_NON_RAID | FW_VER_4PORT), 200 FL_DAC = (1 << 16), 201 FL_DYN_MAJOR = (1 << 17), 202}; 203 204enum { 205 CARM_SG_BOUNDARY = 0xffffUL, /* s/g segment boundary */ 206}; 207 208enum scatter_gather_types { 209 SGT_32BIT = 0, 210 SGT_64BIT = 1, 211}; 212 213enum host_states { 214 HST_INVALID, /* invalid state; never used */ 215 HST_ALLOC_BUF, /* setting up master SHM area */ 216 HST_ERROR, /* we never leave here */ 217 HST_PORT_SCAN, /* start dev scan */ 218 HST_DEV_SCAN_START, /* start per-device probe */ 219 HST_DEV_SCAN, /* continue per-device probe */ 220 HST_DEV_ACTIVATE, /* activate devices we found */ 221 HST_PROBE_FINISHED, /* probe is complete */ 222 HST_PROBE_START, /* initiate probe */ 223 HST_SYNC_TIME, /* tell firmware what time it is */ 224 HST_GET_FW_VER, /* get firmware version, adapter port cnt */ 225}; 226 227#ifdef CARM_DEBUG 228static const char *state_name[] = { 229 "HST_INVALID", 230 "HST_ALLOC_BUF", 231 "HST_ERROR", 232 "HST_PORT_SCAN", 233 "HST_DEV_SCAN_START", 234 "HST_DEV_SCAN", 235 "HST_DEV_ACTIVATE", 236 "HST_PROBE_FINISHED", 237 "HST_PROBE_START", 238 "HST_SYNC_TIME", 239 "HST_GET_FW_VER", 240}; 241#endif 242 243struct carm_port { 244 unsigned int port_no; 245 struct gendisk *disk; 246 struct carm_host *host; 247 248 /* attached device characteristics */ 249 u64 capacity; 250 char name[41]; 251 u16 dev_geom_head; 252 u16 dev_geom_sect; 253 u16 dev_geom_cyl; 254}; 255 256struct carm_request { 257 unsigned int tag; 258 int n_elem; 259 unsigned int msg_type; 260 unsigned int msg_subtype; 261 unsigned int msg_bucket; 262 struct request *rq; 263 struct carm_port *port; 264 struct scatterlist sg[CARM_MAX_REQ_SG]; 265}; 266 267struct carm_host { 268 unsigned long flags; 269 void __iomem *mmio; 270 void *shm; 271 dma_addr_t shm_dma; 272 273 int major; 274 int id; 275 char name[32]; 276 277 spinlock_t lock; 278 struct pci_dev *pdev; 279 unsigned int state; 280 u32 fw_ver; 281 282 struct request_queue *oob_q; 283 unsigned int n_oob; 284 285 unsigned int hw_sg_used; 286 287 unsigned int resp_idx; 288 289 unsigned int wait_q_prod; 290 unsigned int wait_q_cons; 291 struct request_queue *wait_q[CARM_MAX_WAIT_Q]; 292 293 unsigned int n_msgs; 294 u64 msg_alloc; 295 struct carm_request req[CARM_MAX_REQ]; 296 void *msg_base; 297 dma_addr_t msg_dma; 298 299 int cur_scan_dev; 300 unsigned long dev_active; 301 unsigned long dev_present; 302 struct carm_port port[CARM_MAX_PORTS]; 303 304 struct work_struct fsm_task; 305 306 struct completion probe_comp; 307}; 308 309struct carm_response { 310 __le32 ret_handle; 311 __le32 status; 312} __attribute__((packed)); 313 314struct carm_msg_sg { 315 __le32 start; 316 __le32 len; 317} __attribute__((packed)); 318 319struct carm_msg_rw { 320 u8 type; 321 u8 id; 322 u8 sg_count; 323 u8 sg_type; 324 __le32 handle; 325 __le32 lba; 326 __le16 lba_count; 327 __le16 lba_high; 328 struct carm_msg_sg sg[32]; 329} __attribute__((packed)); 330 331struct carm_msg_allocbuf { 332 u8 type; 333 u8 subtype; 334 u8 n_sg; 335 u8 sg_type; 336 __le32 handle; 337 __le32 addr; 338 __le32 len; 339 __le32 evt_pool; 340 __le32 n_evt; 341 __le32 rbuf_pool; 342 __le32 n_rbuf; 343 __le32 msg_pool; 344 __le32 n_msg; 345 struct carm_msg_sg sg[8]; 346} __attribute__((packed)); 347 348struct carm_msg_ioctl { 349 u8 type; 350 u8 subtype; 351 u8 array_id; 352 u8 reserved1; 353 __le32 handle; 354 __le32 data_addr; 355 u32 reserved2; 356} __attribute__((packed)); 357 358struct carm_msg_sync_time { 359 u8 type; 360 u8 subtype; 361 u16 reserved1; 362 __le32 handle; 363 u32 reserved2; 364 __le32 timestamp; 365} __attribute__((packed)); 366 367struct carm_msg_get_fw_ver { 368 u8 type; 369 u8 subtype; 370 u16 reserved1; 371 __le32 handle; 372 __le32 data_addr; 373 u32 reserved2; 374} __attribute__((packed)); 375 376struct carm_fw_ver { 377 __le32 version; 378 u8 features; 379 u8 reserved1; 380 u16 reserved2; 381} __attribute__((packed)); 382 383struct carm_array_info { 384 __le32 size; 385 386 __le16 size_hi; 387 __le16 stripe_size; 388 389 __le32 mode; 390 391 __le16 stripe_blk_sz; 392 __le16 reserved1; 393 394 __le16 cyl; 395 __le16 head; 396 397 __le16 sect; 398 u8 array_id; 399 u8 reserved2; 400 401 char name[40]; 402 403 __le32 array_status; 404 405 /* device list continues beyond this point? */ 406} __attribute__((packed)); 407 408static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); 409static void carm_remove_one (struct pci_dev *pdev); 410static int carm_bdev_getgeo(struct block_device *bdev, struct hd_geometry *geo); 411 412static const struct pci_device_id carm_pci_tbl[] = { 413 { PCI_VENDOR_ID_PROMISE, 0x8000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, 414 { PCI_VENDOR_ID_PROMISE, 0x8002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, 415 { } /* terminate list */ 416}; 417MODULE_DEVICE_TABLE(pci, carm_pci_tbl); 418 419static struct pci_driver carm_driver = { 420 .name = DRV_NAME, 421 .id_table = carm_pci_tbl, 422 .probe = carm_init_one, 423 .remove = carm_remove_one, 424}; 425 426static const struct block_device_operations carm_bd_ops = { 427 .owner = THIS_MODULE, 428 .getgeo = carm_bdev_getgeo, 429}; 430 431static unsigned int carm_host_id; 432static unsigned long carm_major_alloc; 433 434 435 436static int carm_bdev_getgeo(struct block_device *bdev, struct hd_geometry *geo) 437{ 438 struct carm_port *port = bdev->bd_disk->private_data; 439 440 geo->heads = (u8) port->dev_geom_head; 441 geo->sectors = (u8) port->dev_geom_sect; 442 geo->cylinders = port->dev_geom_cyl; 443 return 0; 444} 445 446static const u32 msg_sizes[] = { 32, 64, 128, CARM_MSG_SIZE }; 447 448static inline int carm_lookup_bucket(u32 msg_size) 449{ 450 int i; 451 452 for (i = 0; i < ARRAY_SIZE(msg_sizes); i++) 453 if (msg_size <= msg_sizes[i]) 454 return i; 455 456 return -ENOENT; 457} 458 459static void carm_init_buckets(void __iomem *mmio) 460{ 461 unsigned int i; 462 463 for (i = 0; i < ARRAY_SIZE(msg_sizes); i++) 464 writel(msg_sizes[i], mmio + CARM_CMS0 + (4 * i)); 465} 466 467static inline void *carm_ref_msg(struct carm_host *host, 468 unsigned int msg_idx) 469{ 470 return host->msg_base + (msg_idx * CARM_MSG_SIZE); 471} 472 473static inline dma_addr_t carm_ref_msg_dma(struct carm_host *host, 474 unsigned int msg_idx) 475{ 476 return host->msg_dma + (msg_idx * CARM_MSG_SIZE); 477} 478 479static int carm_send_msg(struct carm_host *host, 480 struct carm_request *crq) 481{ 482 void __iomem *mmio = host->mmio; 483 u32 msg = (u32) carm_ref_msg_dma(host, crq->tag); 484 u32 cm_bucket = crq->msg_bucket; 485 u32 tmp; 486 int rc = 0; 487 488 VPRINTK("ENTER\n"); 489 490 tmp = readl(mmio + CARM_HMUC); 491 if (tmp & CARM_Q_FULL) { 492#if 0 493 tmp = readl(mmio + CARM_INT_MASK); 494 tmp |= INT_Q_AVAILABLE; 495 writel(tmp, mmio + CARM_INT_MASK); 496 readl(mmio + CARM_INT_MASK); /* flush */ 497#endif 498 DPRINTK("host msg queue full\n"); 499 rc = -EBUSY; 500 } else { 501 writel(msg | (cm_bucket << 1), mmio + CARM_IHQP); 502 readl(mmio + CARM_IHQP); /* flush */ 503 } 504 505 return rc; 506} 507 508static struct carm_request *carm_get_request(struct carm_host *host) 509{ 510 unsigned int i; 511 512 /* obey global hardware limit on S/G entries */ 513 if (host->hw_sg_used >= (CARM_MAX_HOST_SG - CARM_MAX_REQ_SG)) 514 return NULL; 515 516 for (i = 0; i < max_queue; i++) 517 if ((host->msg_alloc & (1ULL << i)) == 0) { 518 struct carm_request *crq = &host->req[i]; 519 crq->port = NULL; 520 crq->n_elem = 0; 521 522 host->msg_alloc |= (1ULL << i); 523 host->n_msgs++; 524 525 assert(host->n_msgs <= CARM_MAX_REQ); 526 sg_init_table(crq->sg, CARM_MAX_REQ_SG); 527 return crq; 528 } 529 530 DPRINTK("no request available, returning NULL\n"); 531 return NULL; 532} 533 534static int carm_put_request(struct carm_host *host, struct carm_request *crq) 535{ 536 assert(crq->tag < max_queue); 537 538 if (unlikely((host->msg_alloc & (1ULL << crq->tag)) == 0)) 539 return -EINVAL; /* tried to clear a tag that was not active */ 540 541 assert(host->hw_sg_used >= crq->n_elem); 542 543 host->msg_alloc &= ~(1ULL << crq->tag); 544 host->hw_sg_used -= crq->n_elem; 545 host->n_msgs--; 546 547 return 0; 548} 549 550static struct carm_request *carm_get_special(struct carm_host *host) 551{ 552 unsigned long flags; 553 struct carm_request *crq = NULL; 554 struct request *rq; 555 int tries = 5000; 556 557 while (tries-- > 0) { 558 spin_lock_irqsave(&host->lock, flags); 559 crq = carm_get_request(host); 560 spin_unlock_irqrestore(&host->lock, flags); 561 562 if (crq) 563 break; 564 msleep(10); 565 } 566 567 if (!crq) 568 return NULL; 569 570 rq = blk_get_request(host->oob_q, WRITE /* bogus */, GFP_KERNEL); 571 if (!rq) { 572 spin_lock_irqsave(&host->lock, flags); 573 carm_put_request(host, crq); 574 spin_unlock_irqrestore(&host->lock, flags); 575 return NULL; 576 } 577 578 crq->rq = rq; 579 return crq; 580} 581 582static int carm_array_info (struct carm_host *host, unsigned int array_idx) 583{ 584 struct carm_msg_ioctl *ioc; 585 unsigned int idx; 586 u32 msg_data; 587 dma_addr_t msg_dma; 588 struct carm_request *crq; 589 int rc; 590 591 crq = carm_get_special(host); 592 if (!crq) { 593 rc = -ENOMEM; 594 goto err_out; 595 } 596 597 idx = crq->tag; 598 599 ioc = carm_ref_msg(host, idx); 600 msg_dma = carm_ref_msg_dma(host, idx); 601 msg_data = (u32) (msg_dma + sizeof(struct carm_array_info)); 602 603 crq->msg_type = CARM_MSG_ARRAY; 604 crq->msg_subtype = CARM_ARRAY_INFO; 605 rc = carm_lookup_bucket(sizeof(struct carm_msg_ioctl) + 606 sizeof(struct carm_array_info)); 607 BUG_ON(rc < 0); 608 crq->msg_bucket = (u32) rc; 609 610 memset(ioc, 0, sizeof(*ioc)); 611 ioc->type = CARM_MSG_ARRAY; 612 ioc->subtype = CARM_ARRAY_INFO; 613 ioc->array_id = (u8) array_idx; 614 ioc->handle = cpu_to_le32(TAG_ENCODE(idx)); 615 ioc->data_addr = cpu_to_le32(msg_data); 616 617 spin_lock_irq(&host->lock); 618 assert(host->state == HST_DEV_SCAN_START || 619 host->state == HST_DEV_SCAN); 620 spin_unlock_irq(&host->lock); 621 622 DPRINTK("blk_execute_rq_nowait, tag == %u\n", idx); 623 crq->rq->cmd_type = REQ_TYPE_SPECIAL; 624 crq->rq->special = crq; 625 blk_execute_rq_nowait(host->oob_q, NULL, crq->rq, true, NULL); 626 627 return 0; 628 629err_out: 630 spin_lock_irq(&host->lock); 631 host->state = HST_ERROR; 632 spin_unlock_irq(&host->lock); 633 return rc; 634} 635 636typedef unsigned int (*carm_sspc_t)(struct carm_host *, unsigned int, void *); 637 638static int carm_send_special (struct carm_host *host, carm_sspc_t func) 639{ 640 struct carm_request *crq; 641 struct carm_msg_ioctl *ioc; 642 void *mem; 643 unsigned int idx, msg_size; 644 int rc; 645 646 crq = carm_get_special(host); 647 if (!crq) 648 return -ENOMEM; 649 650 idx = crq->tag; 651 652 mem = carm_ref_msg(host, idx); 653 654 msg_size = func(host, idx, mem); 655 656 ioc = mem; 657 crq->msg_type = ioc->type; 658 crq->msg_subtype = ioc->subtype; 659 rc = carm_lookup_bucket(msg_size); 660 BUG_ON(rc < 0); 661 crq->msg_bucket = (u32) rc; 662 663 DPRINTK("blk_execute_rq_nowait, tag == %u\n", idx); 664 crq->rq->cmd_type = REQ_TYPE_SPECIAL; 665 crq->rq->special = crq; 666 blk_execute_rq_nowait(host->oob_q, NULL, crq->rq, true, NULL); 667 668 return 0; 669} 670 671static unsigned int carm_fill_sync_time(struct carm_host *host, 672 unsigned int idx, void *mem) 673{ 674 struct timeval tv; 675 struct carm_msg_sync_time *st = mem; 676 677 do_gettimeofday(&tv); 678 679 memset(st, 0, sizeof(*st)); 680 st->type = CARM_MSG_MISC; 681 st->subtype = MISC_SET_TIME; 682 st->handle = cpu_to_le32(TAG_ENCODE(idx)); 683 st->timestamp = cpu_to_le32(tv.tv_sec); 684 685 return sizeof(struct carm_msg_sync_time); 686} 687 688static unsigned int carm_fill_alloc_buf(struct carm_host *host, 689 unsigned int idx, void *mem) 690{ 691 struct carm_msg_allocbuf *ab = mem; 692 693 memset(ab, 0, sizeof(*ab)); 694 ab->type = CARM_MSG_MISC; 695 ab->subtype = MISC_ALLOC_MEM; 696 ab->handle = cpu_to_le32(TAG_ENCODE(idx)); 697 ab->n_sg = 1; 698 ab->sg_type = SGT_32BIT; 699 ab->addr = cpu_to_le32(host->shm_dma + (PDC_SHM_SIZE >> 1)); 700 ab->len = cpu_to_le32(PDC_SHM_SIZE >> 1); 701 ab->evt_pool = cpu_to_le32(host->shm_dma + (16 * 1024)); 702 ab->n_evt = cpu_to_le32(1024); 703 ab->rbuf_pool = cpu_to_le32(host->shm_dma); 704 ab->n_rbuf = cpu_to_le32(RMSG_Q_LEN); 705 ab->msg_pool = cpu_to_le32(host->shm_dma + RBUF_LEN); 706 ab->n_msg = cpu_to_le32(CARM_Q_LEN); 707 ab->sg[0].start = cpu_to_le32(host->shm_dma + (PDC_SHM_SIZE >> 1)); 708 ab->sg[0].len = cpu_to_le32(65536); 709 710 return sizeof(struct carm_msg_allocbuf); 711} 712 713static unsigned int carm_fill_scan_channels(struct carm_host *host, 714 unsigned int idx, void *mem) 715{ 716 struct carm_msg_ioctl *ioc = mem; 717 u32 msg_data = (u32) (carm_ref_msg_dma(host, idx) + 718 IOC_SCAN_CHAN_OFFSET); 719 720 memset(ioc, 0, sizeof(*ioc)); 721 ioc->type = CARM_MSG_IOCTL; 722 ioc->subtype = CARM_IOC_SCAN_CHAN; 723 ioc->handle = cpu_to_le32(TAG_ENCODE(idx)); 724 ioc->data_addr = cpu_to_le32(msg_data); 725 726 /* fill output data area with "no device" default values */ 727 mem += IOC_SCAN_CHAN_OFFSET; 728 memset(mem, IOC_SCAN_CHAN_NODEV, CARM_MAX_PORTS); 729 730 return IOC_SCAN_CHAN_OFFSET + CARM_MAX_PORTS; 731} 732 733static unsigned int carm_fill_get_fw_ver(struct carm_host *host, 734 unsigned int idx, void *mem) 735{ 736 struct carm_msg_get_fw_ver *ioc = mem; 737 u32 msg_data = (u32) (carm_ref_msg_dma(host, idx) + sizeof(*ioc)); 738 739 memset(ioc, 0, sizeof(*ioc)); 740 ioc->type = CARM_MSG_MISC; 741 ioc->subtype = MISC_GET_FW_VER; 742 ioc->handle = cpu_to_le32(TAG_ENCODE(idx)); 743 ioc->data_addr = cpu_to_le32(msg_data); 744 745 return sizeof(struct carm_msg_get_fw_ver) + 746 sizeof(struct carm_fw_ver); 747} 748 749static inline void carm_end_request_queued(struct carm_host *host, 750 struct carm_request *crq, 751 int error) 752{ 753 struct request *req = crq->rq; 754 int rc; 755 756 __blk_end_request_all(req, error); 757 758 rc = carm_put_request(host, crq); 759 assert(rc == 0); 760} 761 762static inline void carm_push_q (struct carm_host *host, struct request_queue *q) 763{ 764 unsigned int idx = host->wait_q_prod % CARM_MAX_WAIT_Q; 765 766 blk_stop_queue(q); 767 VPRINTK("STOPPED QUEUE %p\n", q); 768 769 host->wait_q[idx] = q; 770 host->wait_q_prod++; 771 BUG_ON(host->wait_q_prod == host->wait_q_cons); /* overrun */ 772} 773 774static inline struct request_queue *carm_pop_q(struct carm_host *host) 775{ 776 unsigned int idx; 777 778 if (host->wait_q_prod == host->wait_q_cons) 779 return NULL; 780 781 idx = host->wait_q_cons % CARM_MAX_WAIT_Q; 782 host->wait_q_cons++; 783 784 return host->wait_q[idx]; 785} 786 787static inline void carm_round_robin(struct carm_host *host) 788{ 789 struct request_queue *q = carm_pop_q(host); 790 if (q) { 791 blk_start_queue(q); 792 VPRINTK("STARTED QUEUE %p\n", q); 793 } 794} 795 796static inline void carm_end_rq(struct carm_host *host, struct carm_request *crq, 797 int error) 798{ 799 carm_end_request_queued(host, crq, error); 800 if (max_queue == 1) 801 carm_round_robin(host); 802 else if ((host->n_msgs <= CARM_MSG_LOW_WATER) && 803 (host->hw_sg_used <= CARM_SG_LOW_WATER)) { 804 carm_round_robin(host); 805 } 806} 807 808static void carm_oob_rq_fn(struct request_queue *q) 809{ 810 struct carm_host *host = q->queuedata; 811 struct carm_request *crq; 812 struct request *rq; 813 int rc; 814 815 while (1) { 816 DPRINTK("get req\n"); 817 rq = blk_fetch_request(q); 818 if (!rq) 819 break; 820 821 crq = rq->special; 822 assert(crq != NULL); 823 assert(crq->rq == rq); 824 825 crq->n_elem = 0; 826 827 DPRINTK("send req\n"); 828 rc = carm_send_msg(host, crq); 829 if (rc) { 830 blk_requeue_request(q, rq); 831 carm_push_q(host, q); 832 return; /* call us again later, eventually */ 833 } 834 } 835} 836 837static void carm_rq_fn(struct request_queue *q) 838{ 839 struct carm_port *port = q->queuedata; 840 struct carm_host *host = port->host; 841 struct carm_msg_rw *msg; 842 struct carm_request *crq; 843 struct request *rq; 844 struct scatterlist *sg; 845 int writing = 0, pci_dir, i, n_elem, rc; 846 u32 tmp; 847 unsigned int msg_size; 848 849queue_one_request: 850 VPRINTK("get req\n"); 851 rq = blk_peek_request(q); 852 if (!rq) 853 return; 854 855 crq = carm_get_request(host); 856 if (!crq) { 857 carm_push_q(host, q); 858 return; /* call us again later, eventually */ 859 } 860 crq->rq = rq; 861 862 blk_start_request(rq); 863 864 if (rq_data_dir(rq) == WRITE) { 865 writing = 1; 866 pci_dir = PCI_DMA_TODEVICE; 867 } else { 868 pci_dir = PCI_DMA_FROMDEVICE; 869 } 870 871 /* get scatterlist from block layer */ 872 sg = &crq->sg[0]; 873 n_elem = blk_rq_map_sg(q, rq, sg); 874 if (n_elem <= 0) { 875 carm_end_rq(host, crq, -EIO); 876 return; /* request with no s/g entries? */ 877 } 878 879 /* map scatterlist to PCI bus addresses */ 880 n_elem = pci_map_sg(host->pdev, sg, n_elem, pci_dir); 881 if (n_elem <= 0) { 882 carm_end_rq(host, crq, -EIO); 883 return; /* request with no s/g entries? */ 884 } 885 crq->n_elem = n_elem; 886 crq->port = port; 887 host->hw_sg_used += n_elem; 888 889 /* 890 * build read/write message 891 */ 892 893 VPRINTK("build msg\n"); 894 msg = (struct carm_msg_rw *) carm_ref_msg(host, crq->tag); 895 896 if (writing) { 897 msg->type = CARM_MSG_WRITE; 898 crq->msg_type = CARM_MSG_WRITE; 899 } else { 900 msg->type = CARM_MSG_READ; 901 crq->msg_type = CARM_MSG_READ; 902 } 903 904 msg->id = port->port_no; 905 msg->sg_count = n_elem; 906 msg->sg_type = SGT_32BIT; 907 msg->handle = cpu_to_le32(TAG_ENCODE(crq->tag)); 908 msg->lba = cpu_to_le32(blk_rq_pos(rq) & 0xffffffff); 909 tmp = (blk_rq_pos(rq) >> 16) >> 16; 910 msg->lba_high = cpu_to_le16( (u16) tmp ); 911 msg->lba_count = cpu_to_le16(blk_rq_sectors(rq)); 912 913 msg_size = sizeof(struct carm_msg_rw) - sizeof(msg->sg); 914 for (i = 0; i < n_elem; i++) { 915 struct carm_msg_sg *carm_sg = &msg->sg[i]; 916 carm_sg->start = cpu_to_le32(sg_dma_address(&crq->sg[i])); 917 carm_sg->len = cpu_to_le32(sg_dma_len(&crq->sg[i])); 918 msg_size += sizeof(struct carm_msg_sg); 919 } 920 921 rc = carm_lookup_bucket(msg_size); 922 BUG_ON(rc < 0); 923 crq->msg_bucket = (u32) rc; 924 925 /* 926 * queue read/write message to hardware 927 */ 928 929 VPRINTK("send msg, tag == %u\n", crq->tag); 930 rc = carm_send_msg(host, crq); 931 if (rc) { 932 carm_put_request(host, crq); 933 blk_requeue_request(q, rq); 934 carm_push_q(host, q); 935 return; /* call us again later, eventually */ 936 } 937 938 goto queue_one_request; 939} 940 941static void carm_handle_array_info(struct carm_host *host, 942 struct carm_request *crq, u8 *mem, 943 int error) 944{ 945 struct carm_port *port; 946 u8 *msg_data = mem + sizeof(struct carm_array_info); 947 struct carm_array_info *desc = (struct carm_array_info *) msg_data; 948 u64 lo, hi; 949 int cur_port; 950 size_t slen; 951 952 DPRINTK("ENTER\n"); 953 954 carm_end_rq(host, crq, error); 955 956 if (error) 957 goto out; 958 if (le32_to_cpu(desc->array_status) & ARRAY_NO_EXIST) 959 goto out; 960 961 cur_port = host->cur_scan_dev; 962 963 /* should never occur */ 964 if ((cur_port < 0) || (cur_port >= CARM_MAX_PORTS)) { 965 printk(KERN_ERR PFX "BUG: cur_scan_dev==%d, array_id==%d\n", 966 cur_port, (int) desc->array_id); 967 goto out; 968 } 969 970 port = &host->port[cur_port]; 971 972 lo = (u64) le32_to_cpu(desc->size); 973 hi = (u64) le16_to_cpu(desc->size_hi); 974 975 port->capacity = lo | (hi << 32); 976 port->dev_geom_head = le16_to_cpu(desc->head); 977 port->dev_geom_sect = le16_to_cpu(desc->sect); 978 port->dev_geom_cyl = le16_to_cpu(desc->cyl); 979 980 host->dev_active |= (1 << cur_port); 981 982 strncpy(port->name, desc->name, sizeof(port->name)); 983 port->name[sizeof(port->name) - 1] = 0; 984 slen = strlen(port->name); 985 while (slen && (port->name[slen - 1] == ' ')) { 986 port->name[slen - 1] = 0; 987 slen--; 988 } 989 990 printk(KERN_INFO DRV_NAME "(%s): port %u device %Lu sectors\n", 991 pci_name(host->pdev), port->port_no, 992 (unsigned long long) port->capacity); 993 printk(KERN_INFO DRV_NAME "(%s): port %u device \"%s\"\n", 994 pci_name(host->pdev), port->port_no, port->name); 995 996out: 997 assert(host->state == HST_DEV_SCAN); 998 schedule_work(&host->fsm_task); 999} 1000 1001static void carm_handle_scan_chan(struct carm_host *host, 1002 struct carm_request *crq, u8 *mem, 1003 int error) 1004{ 1005 u8 *msg_data = mem + IOC_SCAN_CHAN_OFFSET; 1006 unsigned int i, dev_count = 0; 1007 int new_state = HST_DEV_SCAN_START; 1008 1009 DPRINTK("ENTER\n"); 1010 1011 carm_end_rq(host, crq, error); 1012 1013 if (error) { 1014 new_state = HST_ERROR; 1015 goto out; 1016 } 1017 1018 /* TODO: scan and support non-disk devices */ 1019 for (i = 0; i < 8; i++) 1020 if (msg_data[i] == 0) { /* direct-access device (disk) */ 1021 host->dev_present |= (1 << i); 1022 dev_count++; 1023 } 1024 1025 printk(KERN_INFO DRV_NAME "(%s): found %u interesting devices\n", 1026 pci_name(host->pdev), dev_count); 1027 1028out: 1029 assert(host->state == HST_PORT_SCAN); 1030 host->state = new_state; 1031 schedule_work(&host->fsm_task); 1032} 1033 1034static void carm_handle_generic(struct carm_host *host, 1035 struct carm_request *crq, int error, 1036 int cur_state, int next_state) 1037{ 1038 DPRINTK("ENTER\n"); 1039 1040 carm_end_rq(host, crq, error); 1041 1042 assert(host->state == cur_state); 1043 if (error) 1044 host->state = HST_ERROR; 1045 else 1046 host->state = next_state; 1047 schedule_work(&host->fsm_task); 1048} 1049 1050static inline void carm_handle_rw(struct carm_host *host, 1051 struct carm_request *crq, int error) 1052{ 1053 int pci_dir; 1054 1055 VPRINTK("ENTER\n"); 1056 1057 if (rq_data_dir(crq->rq) == WRITE) 1058 pci_dir = PCI_DMA_TODEVICE; 1059 else 1060 pci_dir = PCI_DMA_FROMDEVICE; 1061 1062 pci_unmap_sg(host->pdev, &crq->sg[0], crq->n_elem, pci_dir); 1063 1064 carm_end_rq(host, crq, error); 1065} 1066 1067static inline void carm_handle_resp(struct carm_host *host, 1068 __le32 ret_handle_le, u32 status) 1069{ 1070 u32 handle = le32_to_cpu(ret_handle_le); 1071 unsigned int msg_idx; 1072 struct carm_request *crq; 1073 int error = (status == RMSG_OK) ? 0 : -EIO; 1074 u8 *mem; 1075 1076 VPRINTK("ENTER, handle == 0x%x\n", handle); 1077 1078 if (unlikely(!TAG_VALID(handle))) { 1079 printk(KERN_ERR DRV_NAME "(%s): BUG: invalid tag 0x%x\n", 1080 pci_name(host->pdev), handle); 1081 return; 1082 } 1083 1084 msg_idx = TAG_DECODE(handle); 1085 VPRINTK("tag == %u\n", msg_idx); 1086 1087 crq = &host->req[msg_idx]; 1088 1089 /* fast path */ 1090 if (likely(crq->msg_type == CARM_MSG_READ || 1091 crq->msg_type == CARM_MSG_WRITE)) { 1092 carm_handle_rw(host, crq, error); 1093 return; 1094 } 1095 1096 mem = carm_ref_msg(host, msg_idx); 1097 1098 switch (crq->msg_type) { 1099 case CARM_MSG_IOCTL: { 1100 switch (crq->msg_subtype) { 1101 case CARM_IOC_SCAN_CHAN: 1102 carm_handle_scan_chan(host, crq, mem, error); 1103 break; 1104 default: 1105 /* unknown / invalid response */ 1106 goto err_out; 1107 } 1108 break; 1109 } 1110 1111 case CARM_MSG_MISC: { 1112 switch (crq->msg_subtype) { 1113 case MISC_ALLOC_MEM: 1114 carm_handle_generic(host, crq, error, 1115 HST_ALLOC_BUF, HST_SYNC_TIME); 1116 break; 1117 case MISC_SET_TIME: 1118 carm_handle_generic(host, crq, error, 1119 HST_SYNC_TIME, HST_GET_FW_VER); 1120 break; 1121 case MISC_GET_FW_VER: { 1122 struct carm_fw_ver *ver = (struct carm_fw_ver *) 1123 (mem + sizeof(struct carm_msg_get_fw_ver)); 1124 if (!error) { 1125 host->fw_ver = le32_to_cpu(ver->version); 1126 host->flags |= (ver->features & FL_FW_VER_MASK); 1127 } 1128 carm_handle_generic(host, crq, error, 1129 HST_GET_FW_VER, HST_PORT_SCAN); 1130 break; 1131 } 1132 default: 1133 /* unknown / invalid response */ 1134 goto err_out; 1135 } 1136 break; 1137 } 1138 1139 case CARM_MSG_ARRAY: { 1140 switch (crq->msg_subtype) { 1141 case CARM_ARRAY_INFO: 1142 carm_handle_array_info(host, crq, mem, error); 1143 break; 1144 default: 1145 /* unknown / invalid response */ 1146 goto err_out; 1147 } 1148 break; 1149 } 1150 1151 default: 1152 /* unknown / invalid response */ 1153 goto err_out; 1154 } 1155 1156 return; 1157 1158err_out: 1159 printk(KERN_WARNING DRV_NAME "(%s): BUG: unhandled message type %d/%d\n", 1160 pci_name(host->pdev), crq->msg_type, crq->msg_subtype); 1161 carm_end_rq(host, crq, -EIO); 1162} 1163 1164static inline void carm_handle_responses(struct carm_host *host) 1165{ 1166 void __iomem *mmio = host->mmio; 1167 struct carm_response *resp = (struct carm_response *) host->shm; 1168 unsigned int work = 0; 1169 unsigned int idx = host->resp_idx % RMSG_Q_LEN; 1170 1171 while (1) { 1172 u32 status = le32_to_cpu(resp[idx].status); 1173 1174 if (status == 0xffffffff) { 1175 VPRINTK("ending response on index %u\n", idx); 1176 writel(idx << 3, mmio + CARM_RESP_IDX); 1177 break; 1178 } 1179 1180 /* response to a message we sent */ 1181 else if ((status & (1 << 31)) == 0) { 1182 VPRINTK("handling msg response on index %u\n", idx); 1183 carm_handle_resp(host, resp[idx].ret_handle, status); 1184 resp[idx].status = cpu_to_le32(0xffffffff); 1185 } 1186 1187 /* asynchronous events the hardware throws our way */ 1188 else if ((status & 0xff000000) == (1 << 31)) { 1189 u8 *evt_type_ptr = (u8 *) &resp[idx]; 1190 u8 evt_type = *evt_type_ptr; 1191 printk(KERN_WARNING DRV_NAME "(%s): unhandled event type %d\n", 1192 pci_name(host->pdev), (int) evt_type); 1193 resp[idx].status = cpu_to_le32(0xffffffff); 1194 } 1195 1196 idx = NEXT_RESP(idx); 1197 work++; 1198 } 1199 1200 VPRINTK("EXIT, work==%u\n", work); 1201 host->resp_idx += work; 1202} 1203 1204static irqreturn_t carm_interrupt(int irq, void *__host) 1205{ 1206 struct carm_host *host = __host; 1207 void __iomem *mmio; 1208 u32 mask; 1209 int handled = 0; 1210 unsigned long flags; 1211 1212 if (!host) { 1213 VPRINTK("no host\n"); 1214 return IRQ_NONE; 1215 } 1216 1217 spin_lock_irqsave(&host->lock, flags); 1218 1219 mmio = host->mmio; 1220 1221 /* reading should also clear interrupts */ 1222 mask = readl(mmio + CARM_INT_STAT); 1223 1224 if (mask == 0 || mask == 0xffffffff) { 1225 VPRINTK("no work, mask == 0x%x\n", mask); 1226 goto out; 1227 } 1228 1229 if (mask & INT_ACK_MASK) 1230 writel(mask, mmio + CARM_INT_STAT); 1231 1232 if (unlikely(host->state == HST_INVALID)) { 1233 VPRINTK("not initialized yet, mask = 0x%x\n", mask); 1234 goto out; 1235 } 1236 1237 if (mask & CARM_HAVE_RESP) { 1238 handled = 1; 1239 carm_handle_responses(host); 1240 } 1241 1242out: 1243 spin_unlock_irqrestore(&host->lock, flags); 1244 VPRINTK("EXIT\n"); 1245 return IRQ_RETVAL(handled); 1246} 1247 1248static void carm_fsm_task (struct work_struct *work) 1249{ 1250 struct carm_host *host = 1251 container_of(work, struct carm_host, fsm_task); 1252 unsigned long flags; 1253 unsigned int state; 1254 int rc, i, next_dev; 1255 int reschedule = 0; 1256 int new_state = HST_INVALID; 1257 1258 spin_lock_irqsave(&host->lock, flags); 1259 state = host->state; 1260 spin_unlock_irqrestore(&host->lock, flags); 1261 1262 DPRINTK("ENTER, state == %s\n", state_name[state]); 1263 1264 switch (state) { 1265 case HST_PROBE_START: 1266 new_state = HST_ALLOC_BUF; 1267 reschedule = 1; 1268 break; 1269 1270 case HST_ALLOC_BUF: 1271 rc = carm_send_special(host, carm_fill_alloc_buf); 1272 if (rc) { 1273 new_state = HST_ERROR; 1274 reschedule = 1; 1275 } 1276 break; 1277 1278 case HST_SYNC_TIME: 1279 rc = carm_send_special(host, carm_fill_sync_time); 1280 if (rc) { 1281 new_state = HST_ERROR; 1282 reschedule = 1; 1283 } 1284 break; 1285 1286 case HST_GET_FW_VER: 1287 rc = carm_send_special(host, carm_fill_get_fw_ver); 1288 if (rc) { 1289 new_state = HST_ERROR; 1290 reschedule = 1; 1291 } 1292 break; 1293 1294 case HST_PORT_SCAN: 1295 rc = carm_send_special(host, carm_fill_scan_channels); 1296 if (rc) { 1297 new_state = HST_ERROR; 1298 reschedule = 1; 1299 } 1300 break; 1301 1302 case HST_DEV_SCAN_START: 1303 host->cur_scan_dev = -1; 1304 new_state = HST_DEV_SCAN; 1305 reschedule = 1; 1306 break; 1307 1308 case HST_DEV_SCAN: 1309 next_dev = -1; 1310 for (i = host->cur_scan_dev + 1; i < CARM_MAX_PORTS; i++) 1311 if (host->dev_present & (1 << i)) { 1312 next_dev = i; 1313 break; 1314 } 1315 1316 if (next_dev >= 0) { 1317 host->cur_scan_dev = next_dev; 1318 rc = carm_array_info(host, next_dev); 1319 if (rc) { 1320 new_state = HST_ERROR; 1321 reschedule = 1; 1322 } 1323 } else { 1324 new_state = HST_DEV_ACTIVATE; 1325 reschedule = 1; 1326 } 1327 break; 1328 1329 case HST_DEV_ACTIVATE: { 1330 int activated = 0; 1331 for (i = 0; i < CARM_MAX_PORTS; i++) 1332 if (host->dev_active & (1 << i)) { 1333 struct carm_port *port = &host->port[i]; 1334 struct gendisk *disk = port->disk; 1335 1336 set_capacity(disk, port->capacity); 1337 add_disk(disk); 1338 activated++; 1339 } 1340 1341 printk(KERN_INFO DRV_NAME "(%s): %d ports activated\n", 1342 pci_name(host->pdev), activated); 1343 1344 new_state = HST_PROBE_FINISHED; 1345 reschedule = 1; 1346 break; 1347 } 1348 1349 case HST_PROBE_FINISHED: 1350 complete(&host->probe_comp); 1351 break; 1352 1353 case HST_ERROR: 1354 /* FIXME: TODO */ 1355 break; 1356 1357 default: 1358 /* should never occur */ 1359 printk(KERN_ERR PFX "BUG: unknown state %d\n", state); 1360 assert(0); 1361 break; 1362 } 1363 1364 if (new_state != HST_INVALID) { 1365 spin_lock_irqsave(&host->lock, flags); 1366 host->state = new_state; 1367 spin_unlock_irqrestore(&host->lock, flags); 1368 } 1369 if (reschedule) 1370 schedule_work(&host->fsm_task); 1371} 1372 1373static int carm_init_wait(void __iomem *mmio, u32 bits, unsigned int test_bit) 1374{ 1375 unsigned int i; 1376 1377 for (i = 0; i < 50000; i++) { 1378 u32 tmp = readl(mmio + CARM_LMUC); 1379 udelay(100); 1380 1381 if (test_bit) { 1382 if ((tmp & bits) == bits) 1383 return 0; 1384 } else { 1385 if ((tmp & bits) == 0) 1386 return 0; 1387 } 1388 1389 cond_resched(); 1390 } 1391 1392 printk(KERN_ERR PFX "carm_init_wait timeout, bits == 0x%x, test_bit == %s\n", 1393 bits, test_bit ? "yes" : "no"); 1394 return -EBUSY; 1395} 1396 1397static void carm_init_responses(struct carm_host *host) 1398{ 1399 void __iomem *mmio = host->mmio; 1400 unsigned int i; 1401 struct carm_response *resp = (struct carm_response *) host->shm; 1402 1403 for (i = 0; i < RMSG_Q_LEN; i++) 1404 resp[i].status = cpu_to_le32(0xffffffff); 1405 1406 writel(0, mmio + CARM_RESP_IDX); 1407} 1408 1409static int carm_init_host(struct carm_host *host) 1410{ 1411 void __iomem *mmio = host->mmio; 1412 u32 tmp; 1413 u8 tmp8; 1414 int rc; 1415 1416 DPRINTK("ENTER\n"); 1417 1418 writel(0, mmio + CARM_INT_MASK); 1419 1420 tmp8 = readb(mmio + CARM_INITC); 1421 if (tmp8 & 0x01) { 1422 tmp8 &= ~0x01; 1423 writeb(tmp8, mmio + CARM_INITC); 1424 readb(mmio + CARM_INITC); /* flush */ 1425 1426 DPRINTK("snooze...\n"); 1427 msleep(5000); 1428 } 1429 1430 tmp = readl(mmio + CARM_HMUC); 1431 if (tmp & CARM_CME) { 1432 DPRINTK("CME bit present, waiting\n"); 1433 rc = carm_init_wait(mmio, CARM_CME, 1); 1434 if (rc) { 1435 DPRINTK("EXIT, carm_init_wait 1 failed\n"); 1436 return rc; 1437 } 1438 } 1439 if (tmp & CARM_RME) { 1440 DPRINTK("RME bit present, waiting\n"); 1441 rc = carm_init_wait(mmio, CARM_RME, 1); 1442 if (rc) { 1443 DPRINTK("EXIT, carm_init_wait 2 failed\n"); 1444 return rc; 1445 } 1446 } 1447 1448 tmp &= ~(CARM_RME | CARM_CME); 1449 writel(tmp, mmio + CARM_HMUC); 1450 readl(mmio + CARM_HMUC); /* flush */ 1451 1452 rc = carm_init_wait(mmio, CARM_RME | CARM_CME, 0); 1453 if (rc) { 1454 DPRINTK("EXIT, carm_init_wait 3 failed\n"); 1455 return rc; 1456 } 1457 1458 carm_init_buckets(mmio); 1459 1460 writel(host->shm_dma & 0xffffffff, mmio + RBUF_ADDR_LO); 1461 writel((host->shm_dma >> 16) >> 16, mmio + RBUF_ADDR_HI); 1462 writel(RBUF_LEN, mmio + RBUF_BYTE_SZ); 1463 1464 tmp = readl(mmio + CARM_HMUC); 1465 tmp |= (CARM_RME | CARM_CME | CARM_WZBC); 1466 writel(tmp, mmio + CARM_HMUC); 1467 readl(mmio + CARM_HMUC); /* flush */ 1468 1469 rc = carm_init_wait(mmio, CARM_RME | CARM_CME, 1); 1470 if (rc) { 1471 DPRINTK("EXIT, carm_init_wait 4 failed\n"); 1472 return rc; 1473 } 1474 1475 writel(0, mmio + CARM_HMPHA); 1476 writel(INT_DEF_MASK, mmio + CARM_INT_MASK); 1477 1478 carm_init_responses(host); 1479 1480 /* start initialization, probing state machine */ 1481 spin_lock_irq(&host->lock); 1482 assert(host->state == HST_INVALID); 1483 host->state = HST_PROBE_START; 1484 spin_unlock_irq(&host->lock); 1485 schedule_work(&host->fsm_task); 1486 1487 DPRINTK("EXIT\n"); 1488 return 0; 1489} 1490 1491static int carm_init_disks(struct carm_host *host) 1492{ 1493 unsigned int i; 1494 int rc = 0; 1495 1496 for (i = 0; i < CARM_MAX_PORTS; i++) { 1497 struct gendisk *disk; 1498 struct request_queue *q; 1499 struct carm_port *port; 1500 1501 port = &host->port[i]; 1502 port->host = host; 1503 port->port_no = i; 1504 1505 disk = alloc_disk(CARM_MINORS_PER_MAJOR); 1506 if (!disk) { 1507 rc = -ENOMEM; 1508 break; 1509 } 1510 1511 port->disk = disk; 1512 sprintf(disk->disk_name, DRV_NAME "/%u", 1513 (unsigned int) (host->id * CARM_MAX_PORTS) + i); 1514 disk->major = host->major; 1515 disk->first_minor = i * CARM_MINORS_PER_MAJOR; 1516 disk->fops = &carm_bd_ops; 1517 disk->private_data = port; 1518 1519 q = blk_init_queue(carm_rq_fn, &host->lock); 1520 if (!q) { 1521 rc = -ENOMEM; 1522 break; 1523 } 1524 disk->queue = q; 1525 blk_queue_max_segments(q, CARM_MAX_REQ_SG); 1526 blk_queue_segment_boundary(q, CARM_SG_BOUNDARY); 1527 1528 q->queuedata = port; 1529 } 1530 1531 return rc; 1532} 1533 1534static void carm_free_disks(struct carm_host *host) 1535{ 1536 unsigned int i; 1537 1538 for (i = 0; i < CARM_MAX_PORTS; i++) { 1539 struct gendisk *disk = host->port[i].disk; 1540 if (disk) { 1541 struct request_queue *q = disk->queue; 1542 1543 if (disk->flags & GENHD_FL_UP) 1544 del_gendisk(disk); 1545 if (q) 1546 blk_cleanup_queue(q); 1547 put_disk(disk); 1548 } 1549 } 1550} 1551 1552static int carm_init_shm(struct carm_host *host) 1553{ 1554 host->shm = pci_alloc_consistent(host->pdev, CARM_SHM_SIZE, 1555 &host->shm_dma); 1556 if (!host->shm) 1557 return -ENOMEM; 1558 1559 host->msg_base = host->shm + RBUF_LEN; 1560 host->msg_dma = host->shm_dma + RBUF_LEN; 1561 1562 memset(host->shm, 0xff, RBUF_LEN); 1563 memset(host->msg_base, 0, PDC_SHM_SIZE - RBUF_LEN); 1564 1565 return 0; 1566} 1567 1568static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 1569{ 1570 struct carm_host *host; 1571 unsigned int pci_dac; 1572 int rc; 1573 struct request_queue *q; 1574 unsigned int i; 1575 1576 printk_once(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n"); 1577 1578 rc = pci_enable_device(pdev); 1579 if (rc) 1580 return rc; 1581 1582 rc = pci_request_regions(pdev, DRV_NAME); 1583 if (rc) 1584 goto err_out; 1585 1586#ifdef IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */ 1587 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 1588 if (!rc) { 1589 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 1590 if (rc) { 1591 printk(KERN_ERR DRV_NAME "(%s): consistent DMA mask failure\n", 1592 pci_name(pdev)); 1593 goto err_out_regions; 1594 } 1595 pci_dac = 1; 1596 } else { 1597#endif 1598 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 1599 if (rc) { 1600 printk(KERN_ERR DRV_NAME "(%s): DMA mask failure\n", 1601 pci_name(pdev)); 1602 goto err_out_regions; 1603 } 1604 pci_dac = 0; 1605#ifdef IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */ 1606 } 1607#endif 1608 1609 host = kzalloc(sizeof(*host), GFP_KERNEL); 1610 if (!host) { 1611 printk(KERN_ERR DRV_NAME "(%s): memory alloc failure\n", 1612 pci_name(pdev)); 1613 rc = -ENOMEM; 1614 goto err_out_regions; 1615 } 1616 1617 host->pdev = pdev; 1618 host->flags = pci_dac ? FL_DAC : 0; 1619 spin_lock_init(&host->lock); 1620 INIT_WORK(&host->fsm_task, carm_fsm_task); 1621 init_completion(&host->probe_comp); 1622 1623 for (i = 0; i < ARRAY_SIZE(host->req); i++) 1624 host->req[i].tag = i; 1625 1626 host->mmio = ioremap(pci_resource_start(pdev, 0), 1627 pci_resource_len(pdev, 0)); 1628 if (!host->mmio) { 1629 printk(KERN_ERR DRV_NAME "(%s): MMIO alloc failure\n", 1630 pci_name(pdev)); 1631 rc = -ENOMEM; 1632 goto err_out_kfree; 1633 } 1634 1635 rc = carm_init_shm(host); 1636 if (rc) { 1637 printk(KERN_ERR DRV_NAME "(%s): DMA SHM alloc failure\n", 1638 pci_name(pdev)); 1639 goto err_out_iounmap; 1640 } 1641 1642 q = blk_init_queue(carm_oob_rq_fn, &host->lock); 1643 if (!q) { 1644 printk(KERN_ERR DRV_NAME "(%s): OOB queue alloc failure\n", 1645 pci_name(pdev)); 1646 rc = -ENOMEM; 1647 goto err_out_pci_free; 1648 } 1649 host->oob_q = q; 1650 q->queuedata = host; 1651 1652 /* 1653 * Figure out which major to use: 160, 161, or dynamic 1654 */ 1655 if (!test_and_set_bit(0, &carm_major_alloc)) 1656 host->major = 160; 1657 else if (!test_and_set_bit(1, &carm_major_alloc)) 1658 host->major = 161; 1659 else 1660 host->flags |= FL_DYN_MAJOR; 1661 1662 host->id = carm_host_id; 1663 sprintf(host->name, DRV_NAME "%d", carm_host_id); 1664 1665 rc = register_blkdev(host->major, host->name); 1666 if (rc < 0) 1667 goto err_out_free_majors; 1668 if (host->flags & FL_DYN_MAJOR) 1669 host->major = rc; 1670 1671 rc = carm_init_disks(host); 1672 if (rc) 1673 goto err_out_blkdev_disks; 1674 1675 pci_set_master(pdev); 1676 1677 rc = request_irq(pdev->irq, carm_interrupt, IRQF_SHARED, DRV_NAME, host); 1678 if (rc) { 1679 printk(KERN_ERR DRV_NAME "(%s): irq alloc failure\n", 1680 pci_name(pdev)); 1681 goto err_out_blkdev_disks; 1682 } 1683 1684 rc = carm_init_host(host); 1685 if (rc) 1686 goto err_out_free_irq; 1687 1688 DPRINTK("waiting for probe_comp\n"); 1689 wait_for_completion(&host->probe_comp); 1690 1691 printk(KERN_INFO "%s: pci %s, ports %d, io %llx, irq %u, major %d\n", 1692 host->name, pci_name(pdev), (int) CARM_MAX_PORTS, 1693 (unsigned long long)pci_resource_start(pdev, 0), 1694 pdev->irq, host->major); 1695 1696 carm_host_id++; 1697 pci_set_drvdata(pdev, host); 1698 return 0; 1699 1700err_out_free_irq: 1701 free_irq(pdev->irq, host); 1702err_out_blkdev_disks: 1703 carm_free_disks(host); 1704 unregister_blkdev(host->major, host->name); 1705err_out_free_majors: 1706 if (host->major == 160) 1707 clear_bit(0, &carm_major_alloc); 1708 else if (host->major == 161) 1709 clear_bit(1, &carm_major_alloc); 1710 blk_cleanup_queue(host->oob_q); 1711err_out_pci_free: 1712 pci_free_consistent(pdev, CARM_SHM_SIZE, host->shm, host->shm_dma); 1713err_out_iounmap: 1714 iounmap(host->mmio); 1715err_out_kfree: 1716 kfree(host); 1717err_out_regions: 1718 pci_release_regions(pdev); 1719err_out: 1720 pci_disable_device(pdev); 1721 return rc; 1722} 1723 1724static void carm_remove_one (struct pci_dev *pdev) 1725{ 1726 struct carm_host *host = pci_get_drvdata(pdev); 1727 1728 if (!host) { 1729 printk(KERN_ERR PFX "BUG: no host data for PCI(%s)\n", 1730 pci_name(pdev)); 1731 return; 1732 } 1733 1734 free_irq(pdev->irq, host); 1735 carm_free_disks(host); 1736 unregister_blkdev(host->major, host->name); 1737 if (host->major == 160) 1738 clear_bit(0, &carm_major_alloc); 1739 else if (host->major == 161) 1740 clear_bit(1, &carm_major_alloc); 1741 blk_cleanup_queue(host->oob_q); 1742 pci_free_consistent(pdev, CARM_SHM_SIZE, host->shm, host->shm_dma); 1743 iounmap(host->mmio); 1744 kfree(host); 1745 pci_release_regions(pdev); 1746 pci_disable_device(pdev); 1747 pci_set_drvdata(pdev, NULL); 1748} 1749 1750static int __init carm_init(void) 1751{ 1752 return pci_register_driver(&carm_driver); 1753} 1754 1755static void __exit carm_exit(void) 1756{ 1757 pci_unregister_driver(&carm_driver); 1758} 1759 1760module_init(carm_init); 1761module_exit(carm_exit); 1762 1763 1764