1/* 2 * Header file for the Atmel AHB DMA Controller driver 3 * 4 * Copyright (C) 2008 Atmel Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11#ifndef AT_HDMAC_REGS_H 12#define AT_HDMAC_REGS_H 13 14#include <mach/at_hdmac.h> 15 16#define AT_DMA_MAX_NR_CHANNELS 8 17 18 19#define AT_DMA_GCFG 0x00 /* Global Configuration Register */ 20#define AT_DMA_IF_BIGEND(i) (0x1 << (i)) /* AHB-Lite Interface i in Big-endian mode */ 21#define AT_DMA_ARB_CFG (0x1 << 4) /* Arbiter mode. */ 22#define AT_DMA_ARB_CFG_FIXED (0x0 << 4) 23#define AT_DMA_ARB_CFG_ROUND_ROBIN (0x1 << 4) 24 25#define AT_DMA_EN 0x04 /* Controller Enable Register */ 26#define AT_DMA_ENABLE (0x1 << 0) 27 28#define AT_DMA_SREQ 0x08 /* Software Single Request Register */ 29#define AT_DMA_SSREQ(x) (0x1 << ((x) << 1)) /* Request a source single transfer on channel x */ 30#define AT_DMA_DSREQ(x) (0x1 << (1 + ((x) << 1))) /* Request a destination single transfer on channel x */ 31 32#define AT_DMA_CREQ 0x0C /* Software Chunk Transfer Request Register */ 33#define AT_DMA_SCREQ(x) (0x1 << ((x) << 1)) /* Request a source chunk transfer on channel x */ 34#define AT_DMA_DCREQ(x) (0x1 << (1 + ((x) << 1))) /* Request a destination chunk transfer on channel x */ 35 36#define AT_DMA_LAST 0x10 /* Software Last Transfer Flag Register */ 37#define AT_DMA_SLAST(x) (0x1 << ((x) << 1)) /* This src rq is last tx of buffer on channel x */ 38#define AT_DMA_DLAST(x) (0x1 << (1 + ((x) << 1))) /* This dst rq is last tx of buffer on channel x */ 39 40#define AT_DMA_SYNC 0x14 /* Request Synchronization Register */ 41#define AT_DMA_SYR(h) (0x1 << (h)) /* Synchronize handshake line h */ 42 43/* Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt registers */ 44#define AT_DMA_EBCIER 0x18 /* Enable register */ 45#define AT_DMA_EBCIDR 0x1C /* Disable register */ 46#define AT_DMA_EBCIMR 0x20 /* Mask Register */ 47#define AT_DMA_EBCISR 0x24 /* Status Register */ 48#define AT_DMA_CBTC_OFFSET 8 49#define AT_DMA_ERR_OFFSET 16 50#define AT_DMA_BTC(x) (0x1 << (x)) 51#define AT_DMA_CBTC(x) (0x1 << (AT_DMA_CBTC_OFFSET + (x))) 52#define AT_DMA_ERR(x) (0x1 << (AT_DMA_ERR_OFFSET + (x))) 53 54#define AT_DMA_CHER 0x28 /* Channel Handler Enable Register */ 55#define AT_DMA_ENA(x) (0x1 << (x)) 56#define AT_DMA_SUSP(x) (0x1 << ( 8 + (x))) 57#define AT_DMA_KEEP(x) (0x1 << (24 + (x))) 58 59#define AT_DMA_CHDR 0x2C /* Channel Handler Disable Register */ 60#define AT_DMA_DIS(x) (0x1 << (x)) 61#define AT_DMA_RES(x) (0x1 << ( 8 + (x))) 62 63#define AT_DMA_CHSR 0x30 /* Channel Handler Status Register */ 64#define AT_DMA_EMPT(x) (0x1 << (16 + (x))) 65#define AT_DMA_STAL(x) (0x1 << (24 + (x))) 66 67 68#define AT_DMA_CH_REGS_BASE 0x3C /* Channel registers base address */ 69#define ch_regs(x) (AT_DMA_CH_REGS_BASE + (x) * 0x28) /* Channel x base addr */ 70 71/* Hardware register offset for each channel */ 72#define ATC_SADDR_OFFSET 0x00 /* Source Address Register */ 73#define ATC_DADDR_OFFSET 0x04 /* Destination Address Register */ 74#define ATC_DSCR_OFFSET 0x08 /* Descriptor Address Register */ 75#define ATC_CTRLA_OFFSET 0x0C /* Control A Register */ 76#define ATC_CTRLB_OFFSET 0x10 /* Control B Register */ 77#define ATC_CFG_OFFSET 0x14 /* Configuration Register */ 78#define ATC_SPIP_OFFSET 0x18 /* Src PIP Configuration Register */ 79#define ATC_DPIP_OFFSET 0x1C /* Dst PIP Configuration Register */ 80 81 82/* Bitfield definitions */ 83 84/* Bitfields in DSCR */ 85#define ATC_DSCR_IF(i) (0x3 & (i)) /* Dsc feched via AHB-Lite Interface i */ 86 87/* Bitfields in CTRLA */ 88#define ATC_BTSIZE_MAX 0xFFFFUL /* Maximum Buffer Transfer Size */ 89#define ATC_BTSIZE(x) (ATC_BTSIZE_MAX & (x)) /* Buffer Transfer Size */ 90/* Chunck Tranfer size definitions are in at_hdmac.h */ 91#define ATC_SRC_WIDTH_MASK (0x3 << 24) /* Source Single Transfer Size */ 92#define ATC_SRC_WIDTH(x) ((x) << 24) 93#define ATC_SRC_WIDTH_BYTE (0x0 << 24) 94#define ATC_SRC_WIDTH_HALFWORD (0x1 << 24) 95#define ATC_SRC_WIDTH_WORD (0x2 << 24) 96#define ATC_DST_WIDTH_MASK (0x3 << 28) /* Destination Single Transfer Size */ 97#define ATC_DST_WIDTH(x) ((x) << 28) 98#define ATC_DST_WIDTH_BYTE (0x0 << 28) 99#define ATC_DST_WIDTH_HALFWORD (0x1 << 28) 100#define ATC_DST_WIDTH_WORD (0x2 << 28) 101#define ATC_DONE (0x1 << 31) /* Tx Done (only written back in descriptor) */ 102 103/* Bitfields in CTRLB */ 104#define ATC_SIF(i) (0x3 & (i)) /* Src tx done via AHB-Lite Interface i */ 105#define ATC_DIF(i) ((0x3 & (i)) << 4) /* Dst tx done via AHB-Lite Interface i */ 106 /* Specify AHB interfaces */ 107#define AT_DMA_MEM_IF 0 /* interface 0 as memory interface */ 108#define AT_DMA_PER_IF 1 /* interface 1 as peripheral interface */ 109 110#define ATC_SRC_PIP (0x1 << 8) /* Source Picture-in-Picture enabled */ 111#define ATC_DST_PIP (0x1 << 12) /* Destination Picture-in-Picture enabled */ 112#define ATC_SRC_DSCR_DIS (0x1 << 16) /* Src Descriptor fetch disable */ 113#define ATC_DST_DSCR_DIS (0x1 << 20) /* Dst Descriptor fetch disable */ 114#define ATC_FC_MASK (0x7 << 21) /* Choose Flow Controller */ 115#define ATC_FC_MEM2MEM (0x0 << 21) /* Mem-to-Mem (DMA) */ 116#define ATC_FC_MEM2PER (0x1 << 21) /* Mem-to-Periph (DMA) */ 117#define ATC_FC_PER2MEM (0x2 << 21) /* Periph-to-Mem (DMA) */ 118#define ATC_FC_PER2PER (0x3 << 21) /* Periph-to-Periph (DMA) */ 119#define ATC_FC_PER2MEM_PER (0x4 << 21) /* Periph-to-Mem (Peripheral) */ 120#define ATC_FC_MEM2PER_PER (0x5 << 21) /* Mem-to-Periph (Peripheral) */ 121#define ATC_FC_PER2PER_SRCPER (0x6 << 21) /* Periph-to-Periph (Src Peripheral) */ 122#define ATC_FC_PER2PER_DSTPER (0x7 << 21) /* Periph-to-Periph (Dst Peripheral) */ 123#define ATC_SRC_ADDR_MODE_MASK (0x3 << 24) 124#define ATC_SRC_ADDR_MODE_INCR (0x0 << 24) /* Incrementing Mode */ 125#define ATC_SRC_ADDR_MODE_DECR (0x1 << 24) /* Decrementing Mode */ 126#define ATC_SRC_ADDR_MODE_FIXED (0x2 << 24) /* Fixed Mode */ 127#define ATC_DST_ADDR_MODE_MASK (0x3 << 28) 128#define ATC_DST_ADDR_MODE_INCR (0x0 << 28) /* Incrementing Mode */ 129#define ATC_DST_ADDR_MODE_DECR (0x1 << 28) /* Decrementing Mode */ 130#define ATC_DST_ADDR_MODE_FIXED (0x2 << 28) /* Fixed Mode */ 131#define ATC_IEN (0x1 << 30) /* BTC interrupt enable (active low) */ 132#define ATC_AUTO (0x1 << 31) /* Auto multiple buffer tx enable */ 133 134/* Bitfields in CFG */ 135/* are in at_hdmac.h */ 136 137/* Bitfields in SPIP */ 138#define ATC_SPIP_HOLE(x) (0xFFFFU & (x)) 139#define ATC_SPIP_BOUNDARY(x) ((0x3FF & (x)) << 16) 140 141/* Bitfields in DPIP */ 142#define ATC_DPIP_HOLE(x) (0xFFFFU & (x)) 143#define ATC_DPIP_BOUNDARY(x) ((0x3FF & (x)) << 16) 144 145 146/*-- descriptors -----------------------------------------------------*/ 147 148/* LLI == Linked List Item; aka DMA buffer descriptor */ 149struct at_lli { 150 /* values that are not changed by hardware */ 151 dma_addr_t saddr; 152 dma_addr_t daddr; 153 /* value that may get written back: */ 154 u32 ctrla; 155 /* more values that are not changed by hardware */ 156 u32 ctrlb; 157 dma_addr_t dscr; /* chain to next lli */ 158}; 159 160/** 161 * struct at_desc - software descriptor 162 * @at_lli: hardware lli structure 163 * @txd: support for the async_tx api 164 * @desc_node: node on the channed descriptors list 165 * @len: total transaction bytecount 166 */ 167struct at_desc { 168 /* FIRST values the hardware uses */ 169 struct at_lli lli; 170 171 /* THEN values for driver housekeeping */ 172 struct list_head tx_list; 173 struct dma_async_tx_descriptor txd; 174 struct list_head desc_node; 175 size_t len; 176}; 177 178static inline struct at_desc * 179txd_to_at_desc(struct dma_async_tx_descriptor *txd) 180{ 181 return container_of(txd, struct at_desc, txd); 182} 183 184 185/*-- Channels --------------------------------------------------------*/ 186 187/** 188 * atc_status - information bits stored in channel status flag 189 * 190 * Manipulated with atomic operations. 191 */ 192enum atc_status { 193 ATC_IS_ERROR = 0, 194 ATC_IS_PAUSED = 1, 195 ATC_IS_CYCLIC = 24, 196}; 197 198/** 199 * struct at_dma_chan - internal representation of an Atmel HDMAC channel 200 * @chan_common: common dmaengine channel object members 201 * @device: parent device 202 * @ch_regs: memory mapped register base 203 * @mask: channel index in a mask 204 * @status: transmit status information from irq/prep* functions 205 * to tasklet (use atomic operations) 206 * @tasklet: bottom half to finish transaction work 207 * @save_cfg: configuration register that is saved on suspend/resume cycle 208 * @save_dscr: for cyclic operations, preserve next descriptor address in 209 * the cyclic list on suspend/resume cycle 210 * @dma_sconfig: configuration for slave transfers, passed via DMA_SLAVE_CONFIG 211 * @lock: serializes enqueue/dequeue operations to descriptors lists 212 * @active_list: list of descriptors dmaengine is being running on 213 * @queue: list of descriptors ready to be submitted to engine 214 * @free_list: list of descriptors usable by the channel 215 * @descs_allocated: records the actual size of the descriptor pool 216 */ 217struct at_dma_chan { 218 struct dma_chan chan_common; 219 struct at_dma *device; 220 void __iomem *ch_regs; 221 u8 mask; 222 unsigned long status; 223 struct tasklet_struct tasklet; 224 u32 save_cfg; 225 u32 save_dscr; 226 struct dma_slave_config dma_sconfig; 227 228 spinlock_t lock; 229 230 /* these other elements are all protected by lock */ 231 struct list_head active_list; 232 struct list_head queue; 233 struct list_head free_list; 234 unsigned int descs_allocated; 235}; 236 237#define channel_readl(atchan, name) \ 238 __raw_readl((atchan)->ch_regs + ATC_##name##_OFFSET) 239 240#define channel_writel(atchan, name, val) \ 241 __raw_writel((val), (atchan)->ch_regs + ATC_##name##_OFFSET) 242 243static inline struct at_dma_chan *to_at_dma_chan(struct dma_chan *dchan) 244{ 245 return container_of(dchan, struct at_dma_chan, chan_common); 246} 247 248/* 249 * Fix sconfig's burst size according to at_hdmac. We need to convert them as: 250 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3, 32 -> 4, 64 -> 5, 128 -> 6, 256 -> 7. 251 * 252 * This can be done by finding most significant bit set. 253 */ 254static inline void convert_burst(u32 *maxburst) 255{ 256 if (*maxburst > 1) 257 *maxburst = fls(*maxburst) - 2; 258 else 259 *maxburst = 0; 260} 261 262/* 263 * Fix sconfig's bus width according to at_hdmac. 264 * 1 byte -> 0, 2 bytes -> 1, 4 bytes -> 2. 265 */ 266static inline u8 convert_buswidth(enum dma_slave_buswidth addr_width) 267{ 268 switch (addr_width) { 269 case DMA_SLAVE_BUSWIDTH_2_BYTES: 270 return 1; 271 case DMA_SLAVE_BUSWIDTH_4_BYTES: 272 return 2; 273 default: 274 /* For 1 byte width or fallback */ 275 return 0; 276 } 277} 278 279/*-- Controller ------------------------------------------------------*/ 280 281/** 282 * struct at_dma - internal representation of an Atmel HDMA Controller 283 * @chan_common: common dmaengine dma_device object members 284 * @atdma_devtype: identifier of DMA controller compatibility 285 * @ch_regs: memory mapped register base 286 * @clk: dma controller clock 287 * @save_imr: interrupt mask register that is saved on suspend/resume cycle 288 * @all_chan_mask: all channels availlable in a mask 289 * @dma_desc_pool: base of DMA descriptor region (DMA address) 290 * @chan: channels table to store at_dma_chan structures 291 */ 292struct at_dma { 293 struct dma_device dma_common; 294 void __iomem *regs; 295 struct clk *clk; 296 u32 save_imr; 297 298 u8 all_chan_mask; 299 300 struct dma_pool *dma_desc_pool; 301 /* AT THE END channels table */ 302 struct at_dma_chan chan[0]; 303}; 304 305#define dma_readl(atdma, name) \ 306 __raw_readl((atdma)->regs + AT_DMA_##name) 307#define dma_writel(atdma, name, val) \ 308 __raw_writel((val), (atdma)->regs + AT_DMA_##name) 309 310static inline struct at_dma *to_at_dma(struct dma_device *ddev) 311{ 312 return container_of(ddev, struct at_dma, dma_common); 313} 314 315 316/*-- Helper functions ------------------------------------------------*/ 317 318static struct device *chan2dev(struct dma_chan *chan) 319{ 320 return &chan->dev->device; 321} 322static struct device *chan2parent(struct dma_chan *chan) 323{ 324 return chan->dev->device.parent; 325} 326 327#if defined(VERBOSE_DEBUG) 328static void vdbg_dump_regs(struct at_dma_chan *atchan) 329{ 330 struct at_dma *atdma = to_at_dma(atchan->chan_common.device); 331 332 dev_err(chan2dev(&atchan->chan_common), 333 " channel %d : imr = 0x%x, chsr = 0x%x\n", 334 atchan->chan_common.chan_id, 335 dma_readl(atdma, EBCIMR), 336 dma_readl(atdma, CHSR)); 337 338 dev_err(chan2dev(&atchan->chan_common), 339 " channel: s0x%x d0x%x ctrl0x%x:0x%x cfg0x%x l0x%x\n", 340 channel_readl(atchan, SADDR), 341 channel_readl(atchan, DADDR), 342 channel_readl(atchan, CTRLA), 343 channel_readl(atchan, CTRLB), 344 channel_readl(atchan, CFG), 345 channel_readl(atchan, DSCR)); 346} 347#else 348static void vdbg_dump_regs(struct at_dma_chan *atchan) {} 349#endif 350 351static void atc_dump_lli(struct at_dma_chan *atchan, struct at_lli *lli) 352{ 353 dev_printk(KERN_CRIT, chan2dev(&atchan->chan_common), 354 " desc: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n", 355 lli->saddr, lli->daddr, 356 lli->ctrla, lli->ctrlb, lli->dscr); 357} 358 359 360static void atc_setup_irq(struct at_dma *atdma, int chan_id, int on) 361{ 362 u32 ebci; 363 364 /* enable interrupts on buffer transfer completion & error */ 365 ebci = AT_DMA_BTC(chan_id) 366 | AT_DMA_ERR(chan_id); 367 if (on) 368 dma_writel(atdma, EBCIER, ebci); 369 else 370 dma_writel(atdma, EBCIDR, ebci); 371} 372 373static void atc_enable_chan_irq(struct at_dma *atdma, int chan_id) 374{ 375 atc_setup_irq(atdma, chan_id, 1); 376} 377 378static void atc_disable_chan_irq(struct at_dma *atdma, int chan_id) 379{ 380 atc_setup_irq(atdma, chan_id, 0); 381} 382 383 384/** 385 * atc_chan_is_enabled - test if given channel is enabled 386 * @atchan: channel we want to test status 387 */ 388static inline int atc_chan_is_enabled(struct at_dma_chan *atchan) 389{ 390 struct at_dma *atdma = to_at_dma(atchan->chan_common.device); 391 392 return !!(dma_readl(atdma, CHSR) & atchan->mask); 393} 394 395/** 396 * atc_chan_is_paused - test channel pause/resume status 397 * @atchan: channel we want to test status 398 */ 399static inline int atc_chan_is_paused(struct at_dma_chan *atchan) 400{ 401 return test_bit(ATC_IS_PAUSED, &atchan->status); 402} 403 404/** 405 * atc_chan_is_cyclic - test if given channel has cyclic property set 406 * @atchan: channel we want to test status 407 */ 408static inline int atc_chan_is_cyclic(struct at_dma_chan *atchan) 409{ 410 return test_bit(ATC_IS_CYCLIC, &atchan->status); 411} 412 413/** 414 * set_desc_eol - set end-of-link to descriptor so it will end transfer 415 * @desc: descriptor, signle or at the end of a chain, to end chain on 416 */ 417static void set_desc_eol(struct at_desc *desc) 418{ 419 u32 ctrlb = desc->lli.ctrlb; 420 421 ctrlb &= ~ATC_IEN; 422 ctrlb |= ATC_SRC_DSCR_DIS | ATC_DST_DSCR_DIS; 423 424 desc->lli.ctrlb = ctrlb; 425 desc->lli.dscr = 0; 426} 427 428#endif /* AT_HDMAC_REGS_H */ 429