1dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre/* 2dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * Header file for the Atmel AHB DMA Controller driver 3dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * 4dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * Copyright (C) 2008 Atmel Corporation 5dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * 6dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * This program is free software; you can redistribute it and/or modify 7dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * it under the terms of the GNU General Public License as published by 8dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * the Free Software Foundation; either version 2 of the License, or 9dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * (at your option) any later version. 10dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre */ 11dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#ifndef AT_HDMAC_REGS_H 12dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_HDMAC_REGS_H 13dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 14dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#include <mach/at_hdmac.h> 15dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 16dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_MAX_NR_CHANNELS 8 17dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 18dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 19dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_GCFG 0x00 /* Global Configuration Register */ 20dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_IF_BIGEND(i) (0x1 << (i)) /* AHB-Lite Interface i in Big-endian mode */ 21dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_ARB_CFG (0x1 << 4) /* Arbiter mode. */ 22dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_ARB_CFG_FIXED (0x0 << 4) 23dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_ARB_CFG_ROUND_ROBIN (0x1 << 4) 24dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 25dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_EN 0x04 /* Controller Enable Register */ 26dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_ENABLE (0x1 << 0) 27dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 28dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_SREQ 0x08 /* Software Single Request Register */ 29dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_SSREQ(x) (0x1 << ((x) << 1)) /* Request a source single transfer on channel x */ 30dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_DSREQ(x) (0x1 << (1 + ((x) << 1))) /* Request a destination single transfer on channel x */ 31dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 32dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_CREQ 0x0C /* Software Chunk Transfer Request Register */ 33dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_SCREQ(x) (0x1 << ((x) << 1)) /* Request a source chunk transfer on channel x */ 34dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_DCREQ(x) (0x1 << (1 + ((x) << 1))) /* Request a destination chunk transfer on channel x */ 35dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 36dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_LAST 0x10 /* Software Last Transfer Flag Register */ 37dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_SLAST(x) (0x1 << ((x) << 1)) /* This src rq is last tx of buffer on channel x */ 38dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_DLAST(x) (0x1 << (1 + ((x) << 1))) /* This dst rq is last tx of buffer on channel x */ 39dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 40dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_SYNC 0x14 /* Request Synchronization Register */ 41dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_SYR(h) (0x1 << (h)) /* Synchronize handshake line h */ 42dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 43dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre/* Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt registers */ 44dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_EBCIER 0x18 /* Enable register */ 45dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_EBCIDR 0x1C /* Disable register */ 46dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_EBCIMR 0x20 /* Mask Register */ 47dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_EBCISR 0x24 /* Status Register */ 48dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_CBTC_OFFSET 8 49dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_ERR_OFFSET 16 50dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_BTC(x) (0x1 << (x)) 51dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_CBTC(x) (0x1 << (AT_DMA_CBTC_OFFSET + (x))) 52dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_ERR(x) (0x1 << (AT_DMA_ERR_OFFSET + (x))) 53dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 54dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_CHER 0x28 /* Channel Handler Enable Register */ 55dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_ENA(x) (0x1 << (x)) 56dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_SUSP(x) (0x1 << ( 8 + (x))) 57dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_KEEP(x) (0x1 << (24 + (x))) 58dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 59dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_CHDR 0x2C /* Channel Handler Disable Register */ 60dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_DIS(x) (0x1 << (x)) 61dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_RES(x) (0x1 << ( 8 + (x))) 62dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 63dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_CHSR 0x30 /* Channel Handler Status Register */ 64dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_EMPT(x) (0x1 << (16 + (x))) 65dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_STAL(x) (0x1 << (24 + (x))) 66dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 67dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 68dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define AT_DMA_CH_REGS_BASE 0x3C /* Channel registers base address */ 69dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ch_regs(x) (AT_DMA_CH_REGS_BASE + (x) * 0x28) /* Channel x base addr */ 70dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 71dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre/* Hardware register offset for each channel */ 72dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_SADDR_OFFSET 0x00 /* Source Address Register */ 73dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_DADDR_OFFSET 0x04 /* Destination Address Register */ 74dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_DSCR_OFFSET 0x08 /* Descriptor Address Register */ 75dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_CTRLA_OFFSET 0x0C /* Control A Register */ 76dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_CTRLB_OFFSET 0x10 /* Control B Register */ 77dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_CFG_OFFSET 0x14 /* Configuration Register */ 78dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_SPIP_OFFSET 0x18 /* Src PIP Configuration Register */ 79dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_DPIP_OFFSET 0x1C /* Dst PIP Configuration Register */ 80dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 81dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 82dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre/* Bitfield definitions */ 83dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 84dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre/* Bitfields in DSCR */ 85dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_DSCR_IF(i) (0x3 & (i)) /* Dsc feched via AHB-Lite Interface i */ 86dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 87dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre/* Bitfields in CTRLA */ 88dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_BTSIZE_MAX 0xFFFFUL /* Maximum Buffer Transfer Size */ 89dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_BTSIZE(x) (ATC_BTSIZE_MAX & (x)) /* Buffer Transfer Size */ 90808347f6a31792079e345ec865e9cfcb6e8ae6b2Nicolas Ferre/* Chunck Tranfer size definitions are in at_hdmac.h */ 91dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_SRC_WIDTH_MASK (0x3 << 24) /* Source Single Transfer Size */ 92808347f6a31792079e345ec865e9cfcb6e8ae6b2Nicolas Ferre#define ATC_SRC_WIDTH(x) ((x) << 24) 93dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_SRC_WIDTH_BYTE (0x0 << 24) 94dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_SRC_WIDTH_HALFWORD (0x1 << 24) 95dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_SRC_WIDTH_WORD (0x2 << 24) 96dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_DST_WIDTH_MASK (0x3 << 28) /* Destination Single Transfer Size */ 97808347f6a31792079e345ec865e9cfcb6e8ae6b2Nicolas Ferre#define ATC_DST_WIDTH(x) ((x) << 28) 98dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_DST_WIDTH_BYTE (0x0 << 28) 99dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_DST_WIDTH_HALFWORD (0x1 << 28) 100dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_DST_WIDTH_WORD (0x2 << 28) 101dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_DONE (0x1 << 31) /* Tx Done (only written back in descriptor) */ 102dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 103dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre/* Bitfields in CTRLB */ 104dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_SIF(i) (0x3 & (i)) /* Src tx done via AHB-Lite Interface i */ 105dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_DIF(i) ((0x3 & (i)) << 4) /* Dst tx done via AHB-Lite Interface i */ 106ae14d4b5e0a4ebc4e674831cbb97b73ba66dba08Nicolas Ferre /* Specify AHB interfaces */ 107ae14d4b5e0a4ebc4e674831cbb97b73ba66dba08Nicolas Ferre#define AT_DMA_MEM_IF 0 /* interface 0 as memory interface */ 108ae14d4b5e0a4ebc4e674831cbb97b73ba66dba08Nicolas Ferre#define AT_DMA_PER_IF 1 /* interface 1 as peripheral interface */ 109ae14d4b5e0a4ebc4e674831cbb97b73ba66dba08Nicolas Ferre 110dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_SRC_PIP (0x1 << 8) /* Source Picture-in-Picture enabled */ 111dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_DST_PIP (0x1 << 12) /* Destination Picture-in-Picture enabled */ 112dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_SRC_DSCR_DIS (0x1 << 16) /* Src Descriptor fetch disable */ 113dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_DST_DSCR_DIS (0x1 << 20) /* Dst Descriptor fetch disable */ 114dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_FC_MASK (0x7 << 21) /* Choose Flow Controller */ 115dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_FC_MEM2MEM (0x0 << 21) /* Mem-to-Mem (DMA) */ 116dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_FC_MEM2PER (0x1 << 21) /* Mem-to-Periph (DMA) */ 117dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_FC_PER2MEM (0x2 << 21) /* Periph-to-Mem (DMA) */ 118dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_FC_PER2PER (0x3 << 21) /* Periph-to-Periph (DMA) */ 119dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_FC_PER2MEM_PER (0x4 << 21) /* Periph-to-Mem (Peripheral) */ 120dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_FC_MEM2PER_PER (0x5 << 21) /* Mem-to-Periph (Peripheral) */ 121808347f6a31792079e345ec865e9cfcb6e8ae6b2Nicolas Ferre#define ATC_FC_PER2PER_SRCPER (0x6 << 21) /* Periph-to-Periph (Src Peripheral) */ 122808347f6a31792079e345ec865e9cfcb6e8ae6b2Nicolas Ferre#define ATC_FC_PER2PER_DSTPER (0x7 << 21) /* Periph-to-Periph (Dst Peripheral) */ 123dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_SRC_ADDR_MODE_MASK (0x3 << 24) 124dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_SRC_ADDR_MODE_INCR (0x0 << 24) /* Incrementing Mode */ 125dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_SRC_ADDR_MODE_DECR (0x1 << 24) /* Decrementing Mode */ 126dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_SRC_ADDR_MODE_FIXED (0x2 << 24) /* Fixed Mode */ 127dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_DST_ADDR_MODE_MASK (0x3 << 28) 128dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_DST_ADDR_MODE_INCR (0x0 << 28) /* Incrementing Mode */ 129dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_DST_ADDR_MODE_DECR (0x1 << 28) /* Decrementing Mode */ 130dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_DST_ADDR_MODE_FIXED (0x2 << 28) /* Fixed Mode */ 131dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_IEN (0x1 << 30) /* BTC interrupt enable (active low) */ 132dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_AUTO (0x1 << 31) /* Auto multiple buffer tx enable */ 133dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 134dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre/* Bitfields in CFG */ 135808347f6a31792079e345ec865e9cfcb6e8ae6b2Nicolas Ferre/* are in at_hdmac.h */ 136dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 137dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre/* Bitfields in SPIP */ 138dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_SPIP_HOLE(x) (0xFFFFU & (x)) 139dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_SPIP_BOUNDARY(x) ((0x3FF & (x)) << 16) 140dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 141dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre/* Bitfields in DPIP */ 142dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_DPIP_HOLE(x) (0xFFFFU & (x)) 143dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define ATC_DPIP_BOUNDARY(x) ((0x3FF & (x)) << 16) 144dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 145dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 146dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre/*-- descriptors -----------------------------------------------------*/ 147dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 148dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre/* LLI == Linked List Item; aka DMA buffer descriptor */ 149dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferrestruct at_lli { 150dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre /* values that are not changed by hardware */ 151dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre dma_addr_t saddr; 152dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre dma_addr_t daddr; 153dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre /* value that may get written back: */ 154dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre u32 ctrla; 155dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre /* more values that are not changed by hardware */ 156dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre u32 ctrlb; 157dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre dma_addr_t dscr; /* chain to next lli */ 158dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre}; 159dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 160dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre/** 161dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * struct at_desc - software descriptor 162dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * @at_lli: hardware lli structure 163dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * @txd: support for the async_tx api 164dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * @desc_node: node on the channed descriptors list 165dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * @len: total transaction bytecount 166dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre */ 167dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferrestruct at_desc { 168dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre /* FIRST values the hardware uses */ 169dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre struct at_lli lli; 170dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 171dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre /* THEN values for driver housekeeping */ 172285a3c71640ad7101b7237b8fbaa4ead22c6551cDan Williams struct list_head tx_list; 173dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre struct dma_async_tx_descriptor txd; 174dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre struct list_head desc_node; 175dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre size_t len; 176dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre}; 177dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 178dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferrestatic inline struct at_desc * 179dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferretxd_to_at_desc(struct dma_async_tx_descriptor *txd) 180dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre{ 181dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre return container_of(txd, struct at_desc, txd); 182dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre} 183dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 184dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 185dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre/*-- Channels --------------------------------------------------------*/ 186dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 187dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre/** 18853830cc75974a199b6b654c062ff8c54c58caa0bNicolas Ferre * atc_status - information bits stored in channel status flag 18953830cc75974a199b6b654c062ff8c54c58caa0bNicolas Ferre * 19053830cc75974a199b6b654c062ff8c54c58caa0bNicolas Ferre * Manipulated with atomic operations. 19153830cc75974a199b6b654c062ff8c54c58caa0bNicolas Ferre */ 19253830cc75974a199b6b654c062ff8c54c58caa0bNicolas Ferreenum atc_status { 19353830cc75974a199b6b654c062ff8c54c58caa0bNicolas Ferre ATC_IS_ERROR = 0, 19423b5e3ad68a3c26a6a36039ea907997664aedcabNicolas Ferre ATC_IS_PAUSED = 1, 19553830cc75974a199b6b654c062ff8c54c58caa0bNicolas Ferre ATC_IS_CYCLIC = 24, 19653830cc75974a199b6b654c062ff8c54c58caa0bNicolas Ferre}; 19753830cc75974a199b6b654c062ff8c54c58caa0bNicolas Ferre 19853830cc75974a199b6b654c062ff8c54c58caa0bNicolas Ferre/** 199dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * struct at_dma_chan - internal representation of an Atmel HDMAC channel 200dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * @chan_common: common dmaengine channel object members 201dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * @device: parent device 202dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * @ch_regs: memory mapped register base 203dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * @mask: channel index in a mask 20453830cc75974a199b6b654c062ff8c54c58caa0bNicolas Ferre * @status: transmit status information from irq/prep* functions 205dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * to tasklet (use atomic operations) 206dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * @tasklet: bottom half to finish transaction work 207c0ba5947370a0900b1823922fc4faf41515bc901Nicolas Ferre * @save_cfg: configuration register that is saved on suspend/resume cycle 208c0ba5947370a0900b1823922fc4faf41515bc901Nicolas Ferre * @save_dscr: for cyclic operations, preserve next descriptor address in 209c0ba5947370a0900b1823922fc4faf41515bc901Nicolas Ferre * the cyclic list on suspend/resume cycle 210beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre * @dma_sconfig: configuration for slave transfers, passed via DMA_SLAVE_CONFIG 211dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * @lock: serializes enqueue/dequeue operations to descriptors lists 212dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * @active_list: list of descriptors dmaengine is being running on 213dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * @queue: list of descriptors ready to be submitted to engine 214dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * @free_list: list of descriptors usable by the channel 215dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * @descs_allocated: records the actual size of the descriptor pool 216dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre */ 217dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferrestruct at_dma_chan { 218dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre struct dma_chan chan_common; 219dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre struct at_dma *device; 220dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre void __iomem *ch_regs; 221dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre u8 mask; 22253830cc75974a199b6b654c062ff8c54c58caa0bNicolas Ferre unsigned long status; 223dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre struct tasklet_struct tasklet; 224c0ba5947370a0900b1823922fc4faf41515bc901Nicolas Ferre u32 save_cfg; 225c0ba5947370a0900b1823922fc4faf41515bc901Nicolas Ferre u32 save_dscr; 226beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre struct dma_slave_config dma_sconfig; 227dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 228dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre spinlock_t lock; 229dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 230dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre /* these other elements are all protected by lock */ 231dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre struct list_head active_list; 232dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre struct list_head queue; 233dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre struct list_head free_list; 234dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre unsigned int descs_allocated; 235dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre}; 236dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 237dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define channel_readl(atchan, name) \ 238dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre __raw_readl((atchan)->ch_regs + ATC_##name##_OFFSET) 239dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 240dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define channel_writel(atchan, name, val) \ 241dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre __raw_writel((val), (atchan)->ch_regs + ATC_##name##_OFFSET) 242dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 243dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferrestatic inline struct at_dma_chan *to_at_dma_chan(struct dma_chan *dchan) 244dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre{ 245dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre return container_of(dchan, struct at_dma_chan, chan_common); 246dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre} 247dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 248beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre/* 249beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre * Fix sconfig's burst size according to at_hdmac. We need to convert them as: 250beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3, 32 -> 4, 64 -> 5, 128 -> 6, 256 -> 7. 251beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre * 252beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre * This can be done by finding most significant bit set. 253beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre */ 254beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferrestatic inline void convert_burst(u32 *maxburst) 255beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre{ 256beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre if (*maxburst > 1) 257beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre *maxburst = fls(*maxburst) - 2; 258beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre else 259beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre *maxburst = 0; 260beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre} 261beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre 262beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre/* 263beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre * Fix sconfig's bus width according to at_hdmac. 264beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre * 1 byte -> 0, 2 bytes -> 1, 4 bytes -> 2. 265beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre */ 266beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferrestatic inline u8 convert_buswidth(enum dma_slave_buswidth addr_width) 267beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre{ 268beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre switch (addr_width) { 269beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre case DMA_SLAVE_BUSWIDTH_2_BYTES: 270beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre return 1; 271beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre case DMA_SLAVE_BUSWIDTH_4_BYTES: 272beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre return 2; 273beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre default: 274beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre /* For 1 byte width or fallback */ 275beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre return 0; 276beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre } 277beeaa103eecc7a132682c40867f0ef70655383a5Nicolas Ferre} 278dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 279dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre/*-- Controller ------------------------------------------------------*/ 280dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 281dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre/** 282dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * struct at_dma - internal representation of an Atmel HDMA Controller 283dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * @chan_common: common dmaengine dma_device object members 28467348450b86cb1b42aa4dd55cf7cde19c2e53461Nicolas Ferre * @atdma_devtype: identifier of DMA controller compatibility 285dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * @ch_regs: memory mapped register base 286dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * @clk: dma controller clock 287c0ba5947370a0900b1823922fc4faf41515bc901Nicolas Ferre * @save_imr: interrupt mask register that is saved on suspend/resume cycle 288dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * @all_chan_mask: all channels availlable in a mask 289dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * @dma_desc_pool: base of DMA descriptor region (DMA address) 290dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * @chan: channels table to store at_dma_chan structures 291dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre */ 292dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferrestruct at_dma { 293dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre struct dma_device dma_common; 294dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre void __iomem *regs; 295dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre struct clk *clk; 296c0ba5947370a0900b1823922fc4faf41515bc901Nicolas Ferre u32 save_imr; 297dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 298dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre u8 all_chan_mask; 299dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 300dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre struct dma_pool *dma_desc_pool; 301dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre /* AT THE END channels table */ 302dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre struct at_dma_chan chan[0]; 303dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre}; 304dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 305dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define dma_readl(atdma, name) \ 306dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre __raw_readl((atdma)->regs + AT_DMA_##name) 307dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#define dma_writel(atdma, name, val) \ 308dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre __raw_writel((val), (atdma)->regs + AT_DMA_##name) 309dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 310dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferrestatic inline struct at_dma *to_at_dma(struct dma_device *ddev) 311dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre{ 312dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre return container_of(ddev, struct at_dma, dma_common); 313dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre} 314dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 315dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 316dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre/*-- Helper functions ------------------------------------------------*/ 317dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 318dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferrestatic struct device *chan2dev(struct dma_chan *chan) 319dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre{ 320dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre return &chan->dev->device; 321dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre} 322dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferrestatic struct device *chan2parent(struct dma_chan *chan) 323dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre{ 324dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre return chan->dev->device.parent; 325dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre} 326dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 327dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#if defined(VERBOSE_DEBUG) 328dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferrestatic void vdbg_dump_regs(struct at_dma_chan *atchan) 329dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre{ 330dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre struct at_dma *atdma = to_at_dma(atchan->chan_common.device); 331dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 332dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre dev_err(chan2dev(&atchan->chan_common), 333dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre " channel %d : imr = 0x%x, chsr = 0x%x\n", 334dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre atchan->chan_common.chan_id, 335dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre dma_readl(atdma, EBCIMR), 336dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre dma_readl(atdma, CHSR)); 337dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 338dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre dev_err(chan2dev(&atchan->chan_common), 339808347f6a31792079e345ec865e9cfcb6e8ae6b2Nicolas Ferre " channel: s0x%x d0x%x ctrl0x%x:0x%x cfg0x%x l0x%x\n", 340dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre channel_readl(atchan, SADDR), 341dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre channel_readl(atchan, DADDR), 342dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre channel_readl(atchan, CTRLA), 343dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre channel_readl(atchan, CTRLB), 344808347f6a31792079e345ec865e9cfcb6e8ae6b2Nicolas Ferre channel_readl(atchan, CFG), 345dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre channel_readl(atchan, DSCR)); 346dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre} 347dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#else 348dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferrestatic void vdbg_dump_regs(struct at_dma_chan *atchan) {} 349dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#endif 350dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 351dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferrestatic void atc_dump_lli(struct at_dma_chan *atchan, struct at_lli *lli) 352dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre{ 353dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre dev_printk(KERN_CRIT, chan2dev(&atchan->chan_common), 354dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre " desc: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n", 355dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre lli->saddr, lli->daddr, 356dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre lli->ctrla, lli->ctrlb, lli->dscr); 357dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre} 358dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 359dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 360bda3a47c886664e86ee14eb79e9072b9e341f575Nikolaus Vossstatic void atc_setup_irq(struct at_dma *atdma, int chan_id, int on) 361dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre{ 362bda3a47c886664e86ee14eb79e9072b9e341f575Nikolaus Voss u32 ebci; 363dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 3649b3aa589eaa1366200062ce1f9cc7ddca8d1d578Nicolas Ferre /* enable interrupts on buffer transfer completion & error */ 365bda3a47c886664e86ee14eb79e9072b9e341f575Nikolaus Voss ebci = AT_DMA_BTC(chan_id) 366bda3a47c886664e86ee14eb79e9072b9e341f575Nikolaus Voss | AT_DMA_ERR(chan_id); 367dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre if (on) 368dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre dma_writel(atdma, EBCIER, ebci); 369dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre else 370dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre dma_writel(atdma, EBCIDR, ebci); 371dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre} 372dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 373bda3a47c886664e86ee14eb79e9072b9e341f575Nikolaus Vossstatic void atc_enable_chan_irq(struct at_dma *atdma, int chan_id) 374dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre{ 375bda3a47c886664e86ee14eb79e9072b9e341f575Nikolaus Voss atc_setup_irq(atdma, chan_id, 1); 376dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre} 377dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 378bda3a47c886664e86ee14eb79e9072b9e341f575Nikolaus Vossstatic void atc_disable_chan_irq(struct at_dma *atdma, int chan_id) 379dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre{ 380bda3a47c886664e86ee14eb79e9072b9e341f575Nikolaus Voss atc_setup_irq(atdma, chan_id, 0); 381dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre} 382dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 383dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 384dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre/** 385dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * atc_chan_is_enabled - test if given channel is enabled 386dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * @atchan: channel we want to test status 387dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre */ 388dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferrestatic inline int atc_chan_is_enabled(struct at_dma_chan *atchan) 389dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre{ 390dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre struct at_dma *atdma = to_at_dma(atchan->chan_common.device); 391dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 392dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre return !!(dma_readl(atdma, CHSR) & atchan->mask); 393dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre} 394dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 3953c477482bb9f976e5451c50be7d3d60ea6f88646Nicolas Ferre/** 3963c477482bb9f976e5451c50be7d3d60ea6f88646Nicolas Ferre * atc_chan_is_paused - test channel pause/resume status 3973c477482bb9f976e5451c50be7d3d60ea6f88646Nicolas Ferre * @atchan: channel we want to test status 3983c477482bb9f976e5451c50be7d3d60ea6f88646Nicolas Ferre */ 3993c477482bb9f976e5451c50be7d3d60ea6f88646Nicolas Ferrestatic inline int atc_chan_is_paused(struct at_dma_chan *atchan) 4003c477482bb9f976e5451c50be7d3d60ea6f88646Nicolas Ferre{ 4013c477482bb9f976e5451c50be7d3d60ea6f88646Nicolas Ferre return test_bit(ATC_IS_PAUSED, &atchan->status); 4023c477482bb9f976e5451c50be7d3d60ea6f88646Nicolas Ferre} 4033c477482bb9f976e5451c50be7d3d60ea6f88646Nicolas Ferre 4043c477482bb9f976e5451c50be7d3d60ea6f88646Nicolas Ferre/** 4053c477482bb9f976e5451c50be7d3d60ea6f88646Nicolas Ferre * atc_chan_is_cyclic - test if given channel has cyclic property set 4063c477482bb9f976e5451c50be7d3d60ea6f88646Nicolas Ferre * @atchan: channel we want to test status 4073c477482bb9f976e5451c50be7d3d60ea6f88646Nicolas Ferre */ 4083c477482bb9f976e5451c50be7d3d60ea6f88646Nicolas Ferrestatic inline int atc_chan_is_cyclic(struct at_dma_chan *atchan) 4093c477482bb9f976e5451c50be7d3d60ea6f88646Nicolas Ferre{ 4103c477482bb9f976e5451c50be7d3d60ea6f88646Nicolas Ferre return test_bit(ATC_IS_CYCLIC, &atchan->status); 4113c477482bb9f976e5451c50be7d3d60ea6f88646Nicolas Ferre} 412dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 413dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre/** 414dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * set_desc_eol - set end-of-link to descriptor so it will end transfer 415dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre * @desc: descriptor, signle or at the end of a chain, to end chain on 416dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre */ 417dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferrestatic void set_desc_eol(struct at_desc *desc) 418dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre{ 4199b3aa589eaa1366200062ce1f9cc7ddca8d1d578Nicolas Ferre u32 ctrlb = desc->lli.ctrlb; 4209b3aa589eaa1366200062ce1f9cc7ddca8d1d578Nicolas Ferre 4219b3aa589eaa1366200062ce1f9cc7ddca8d1d578Nicolas Ferre ctrlb &= ~ATC_IEN; 4229b3aa589eaa1366200062ce1f9cc7ddca8d1d578Nicolas Ferre ctrlb |= ATC_SRC_DSCR_DIS | ATC_DST_DSCR_DIS; 4239b3aa589eaa1366200062ce1f9cc7ddca8d1d578Nicolas Ferre 4249b3aa589eaa1366200062ce1f9cc7ddca8d1d578Nicolas Ferre desc->lli.ctrlb = ctrlb; 425dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre desc->lli.dscr = 0; 426dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre} 427dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre 428dc78baa2b90b289590911b40b6800f77d0dc935aNicolas Ferre#endif /* AT_HDMAC_REGS_H */ 429