1/*
2 * Intel 3200/3210 Memory Controller kernel module
3 * Copyright (C) 2008-2009 Akamai Technologies, Inc.
4 * Portions by Hitoshi Mitake <h.mitake@gmail.com>.
5 *
6 * This file may be distributed under the terms of the
7 * GNU General Public License.
8 */
9
10#include <linux/module.h>
11#include <linux/init.h>
12#include <linux/pci.h>
13#include <linux/pci_ids.h>
14#include <linux/edac.h>
15#include <linux/io.h>
16#include "edac_core.h"
17
18#include <asm-generic/io-64-nonatomic-lo-hi.h>
19
20#define I3200_REVISION        "1.1"
21
22#define EDAC_MOD_STR        "i3200_edac"
23
24#define PCI_DEVICE_ID_INTEL_3200_HB    0x29f0
25
26#define I3200_RANKS		8
27#define I3200_RANKS_PER_CHANNEL	4
28#define I3200_CHANNELS		2
29
30/* Intel 3200 register addresses - device 0 function 0 - DRAM Controller */
31
32#define I3200_MCHBAR_LOW	0x48	/* MCH Memory Mapped Register BAR */
33#define I3200_MCHBAR_HIGH	0x4c
34#define I3200_MCHBAR_MASK	0xfffffc000ULL	/* bits 35:14 */
35#define I3200_MMR_WINDOW_SIZE	16384
36
37#define I3200_TOM		0xa0	/* Top of Memory (16b)
38		 *
39		 * 15:10 reserved
40		 *  9:0  total populated physical memory
41		 */
42#define I3200_TOM_MASK		0x3ff	/* bits 9:0 */
43#define I3200_TOM_SHIFT		26	/* 64MiB grain */
44
45#define I3200_ERRSTS		0xc8	/* Error Status Register (16b)
46		 *
47		 * 15    reserved
48		 * 14    Isochronous TBWRR Run Behind FIFO Full
49		 *       (ITCV)
50		 * 13    Isochronous TBWRR Run Behind FIFO Put
51		 *       (ITSTV)
52		 * 12    reserved
53		 * 11    MCH Thermal Sensor Event
54		 *       for SMI/SCI/SERR (GTSE)
55		 * 10    reserved
56		 *  9    LOCK to non-DRAM Memory Flag (LCKF)
57		 *  8    reserved
58		 *  7    DRAM Throttle Flag (DTF)
59		 *  6:2  reserved
60		 *  1    Multi-bit DRAM ECC Error Flag (DMERR)
61		 *  0    Single-bit DRAM ECC Error Flag (DSERR)
62		 */
63#define I3200_ERRSTS_UE		0x0002
64#define I3200_ERRSTS_CE		0x0001
65#define I3200_ERRSTS_BITS	(I3200_ERRSTS_UE | I3200_ERRSTS_CE)
66
67
68/* Intel  MMIO register space - device 0 function 0 - MMR space */
69
70#define I3200_C0DRB	0x200	/* Channel 0 DRAM Rank Boundary (16b x 4)
71		 *
72		 * 15:10 reserved
73		 *  9:0  Channel 0 DRAM Rank Boundary Address
74		 */
75#define I3200_C1DRB	0x600	/* Channel 1 DRAM Rank Boundary (16b x 4) */
76#define I3200_DRB_MASK	0x3ff	/* bits 9:0 */
77#define I3200_DRB_SHIFT	26	/* 64MiB grain */
78
79#define I3200_C0ECCERRLOG	0x280	/* Channel 0 ECC Error Log (64b)
80		 *
81		 * 63:48 Error Column Address (ERRCOL)
82		 * 47:32 Error Row Address (ERRROW)
83		 * 31:29 Error Bank Address (ERRBANK)
84		 * 28:27 Error Rank Address (ERRRANK)
85		 * 26:24 reserved
86		 * 23:16 Error Syndrome (ERRSYND)
87		 * 15: 2 reserved
88		 *    1  Multiple Bit Error Status (MERRSTS)
89		 *    0  Correctable Error Status (CERRSTS)
90		 */
91#define I3200_C1ECCERRLOG		0x680	/* Chan 1 ECC Error Log (64b) */
92#define I3200_ECCERRLOG_CE		0x1
93#define I3200_ECCERRLOG_UE		0x2
94#define I3200_ECCERRLOG_RANK_BITS	0x18000000
95#define I3200_ECCERRLOG_RANK_SHIFT	27
96#define I3200_ECCERRLOG_SYNDROME_BITS	0xff0000
97#define I3200_ECCERRLOG_SYNDROME_SHIFT	16
98#define I3200_CAPID0			0xe0	/* P.95 of spec for details */
99
100struct i3200_priv {
101	void __iomem *window;
102};
103
104static int nr_channels;
105
106static int how_many_channels(struct pci_dev *pdev)
107{
108	unsigned char capid0_8b; /* 8th byte of CAPID0 */
109
110	pci_read_config_byte(pdev, I3200_CAPID0 + 8, &capid0_8b);
111	if (capid0_8b & 0x20) { /* check DCD: Dual Channel Disable */
112		debugf0("In single channel mode.\n");
113		return 1;
114	} else {
115		debugf0("In dual channel mode.\n");
116		return 2;
117	}
118}
119
120static unsigned long eccerrlog_syndrome(u64 log)
121{
122	return (log & I3200_ECCERRLOG_SYNDROME_BITS) >>
123		I3200_ECCERRLOG_SYNDROME_SHIFT;
124}
125
126static int eccerrlog_row(int channel, u64 log)
127{
128	u64 rank = ((log & I3200_ECCERRLOG_RANK_BITS) >>
129		I3200_ECCERRLOG_RANK_SHIFT);
130	return rank | (channel * I3200_RANKS_PER_CHANNEL);
131}
132
133enum i3200_chips {
134	I3200 = 0,
135};
136
137struct i3200_dev_info {
138	const char *ctl_name;
139};
140
141struct i3200_error_info {
142	u16 errsts;
143	u16 errsts2;
144	u64 eccerrlog[I3200_CHANNELS];
145};
146
147static const struct i3200_dev_info i3200_devs[] = {
148	[I3200] = {
149		.ctl_name = "i3200"
150	},
151};
152
153static struct pci_dev *mci_pdev;
154static int i3200_registered = 1;
155
156
157static void i3200_clear_error_info(struct mem_ctl_info *mci)
158{
159	struct pci_dev *pdev;
160
161	pdev = to_pci_dev(mci->dev);
162
163	/*
164	 * Clear any error bits.
165	 * (Yes, we really clear bits by writing 1 to them.)
166	 */
167	pci_write_bits16(pdev, I3200_ERRSTS, I3200_ERRSTS_BITS,
168		I3200_ERRSTS_BITS);
169}
170
171static void i3200_get_and_clear_error_info(struct mem_ctl_info *mci,
172		struct i3200_error_info *info)
173{
174	struct pci_dev *pdev;
175	struct i3200_priv *priv = mci->pvt_info;
176	void __iomem *window = priv->window;
177
178	pdev = to_pci_dev(mci->dev);
179
180	/*
181	 * This is a mess because there is no atomic way to read all the
182	 * registers at once and the registers can transition from CE being
183	 * overwritten by UE.
184	 */
185	pci_read_config_word(pdev, I3200_ERRSTS, &info->errsts);
186	if (!(info->errsts & I3200_ERRSTS_BITS))
187		return;
188
189	info->eccerrlog[0] = readq(window + I3200_C0ECCERRLOG);
190	if (nr_channels == 2)
191		info->eccerrlog[1] = readq(window + I3200_C1ECCERRLOG);
192
193	pci_read_config_word(pdev, I3200_ERRSTS, &info->errsts2);
194
195	/*
196	 * If the error is the same for both reads then the first set
197	 * of reads is valid.  If there is a change then there is a CE
198	 * with no info and the second set of reads is valid and
199	 * should be UE info.
200	 */
201	if ((info->errsts ^ info->errsts2) & I3200_ERRSTS_BITS) {
202		info->eccerrlog[0] = readq(window + I3200_C0ECCERRLOG);
203		if (nr_channels == 2)
204			info->eccerrlog[1] = readq(window + I3200_C1ECCERRLOG);
205	}
206
207	i3200_clear_error_info(mci);
208}
209
210static void i3200_process_error_info(struct mem_ctl_info *mci,
211		struct i3200_error_info *info)
212{
213	int channel;
214	u64 log;
215
216	if (!(info->errsts & I3200_ERRSTS_BITS))
217		return;
218
219	if ((info->errsts ^ info->errsts2) & I3200_ERRSTS_BITS) {
220		edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
221		info->errsts = info->errsts2;
222	}
223
224	for (channel = 0; channel < nr_channels; channel++) {
225		log = info->eccerrlog[channel];
226		if (log & I3200_ECCERRLOG_UE) {
227			edac_mc_handle_ue(mci, 0, 0,
228				eccerrlog_row(channel, log),
229				"i3200 UE");
230		} else if (log & I3200_ECCERRLOG_CE) {
231			edac_mc_handle_ce(mci, 0, 0,
232				eccerrlog_syndrome(log),
233				eccerrlog_row(channel, log), 0,
234				"i3200 CE");
235		}
236	}
237}
238
239static void i3200_check(struct mem_ctl_info *mci)
240{
241	struct i3200_error_info info;
242
243	debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
244	i3200_get_and_clear_error_info(mci, &info);
245	i3200_process_error_info(mci, &info);
246}
247
248
249void __iomem *i3200_map_mchbar(struct pci_dev *pdev)
250{
251	union {
252		u64 mchbar;
253		struct {
254			u32 mchbar_low;
255			u32 mchbar_high;
256		};
257	} u;
258	void __iomem *window;
259
260	pci_read_config_dword(pdev, I3200_MCHBAR_LOW, &u.mchbar_low);
261	pci_read_config_dword(pdev, I3200_MCHBAR_HIGH, &u.mchbar_high);
262	u.mchbar &= I3200_MCHBAR_MASK;
263
264	if (u.mchbar != (resource_size_t)u.mchbar) {
265		printk(KERN_ERR
266			"i3200: mmio space beyond accessible range (0x%llx)\n",
267			(unsigned long long)u.mchbar);
268		return NULL;
269	}
270
271	window = ioremap_nocache(u.mchbar, I3200_MMR_WINDOW_SIZE);
272	if (!window)
273		printk(KERN_ERR "i3200: cannot map mmio space at 0x%llx\n",
274			(unsigned long long)u.mchbar);
275
276	return window;
277}
278
279
280static void i3200_get_drbs(void __iomem *window,
281	u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL])
282{
283	int i;
284
285	for (i = 0; i < I3200_RANKS_PER_CHANNEL; i++) {
286		drbs[0][i] = readw(window + I3200_C0DRB + 2*i) & I3200_DRB_MASK;
287		drbs[1][i] = readw(window + I3200_C1DRB + 2*i) & I3200_DRB_MASK;
288	}
289}
290
291static bool i3200_is_stacked(struct pci_dev *pdev,
292	u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL])
293{
294	u16 tom;
295
296	pci_read_config_word(pdev, I3200_TOM, &tom);
297	tom &= I3200_TOM_MASK;
298
299	return drbs[I3200_CHANNELS - 1][I3200_RANKS_PER_CHANNEL - 1] == tom;
300}
301
302static unsigned long drb_to_nr_pages(
303	u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL], bool stacked,
304	int channel, int rank)
305{
306	int n;
307
308	n = drbs[channel][rank];
309	if (rank > 0)
310		n -= drbs[channel][rank - 1];
311	if (stacked && (channel == 1) &&
312	drbs[channel][rank] == drbs[channel][I3200_RANKS_PER_CHANNEL - 1])
313		n -= drbs[0][I3200_RANKS_PER_CHANNEL - 1];
314
315	n <<= (I3200_DRB_SHIFT - PAGE_SHIFT);
316	return n;
317}
318
319static int i3200_probe1(struct pci_dev *pdev, int dev_idx)
320{
321	int rc;
322	int i;
323	struct mem_ctl_info *mci = NULL;
324	unsigned long last_page;
325	u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL];
326	bool stacked;
327	void __iomem *window;
328	struct i3200_priv *priv;
329
330	debugf0("MC: %s()\n", __func__);
331
332	window = i3200_map_mchbar(pdev);
333	if (!window)
334		return -ENODEV;
335
336	i3200_get_drbs(window, drbs);
337	nr_channels = how_many_channels(pdev);
338
339	mci = edac_mc_alloc(sizeof(struct i3200_priv), I3200_RANKS,
340		nr_channels, 0);
341	if (!mci)
342		return -ENOMEM;
343
344	debugf3("MC: %s(): init mci\n", __func__);
345
346	mci->dev = &pdev->dev;
347	mci->mtype_cap = MEM_FLAG_DDR2;
348
349	mci->edac_ctl_cap = EDAC_FLAG_SECDED;
350	mci->edac_cap = EDAC_FLAG_SECDED;
351
352	mci->mod_name = EDAC_MOD_STR;
353	mci->mod_ver = I3200_REVISION;
354	mci->ctl_name = i3200_devs[dev_idx].ctl_name;
355	mci->dev_name = pci_name(pdev);
356	mci->edac_check = i3200_check;
357	mci->ctl_page_to_phys = NULL;
358	priv = mci->pvt_info;
359	priv->window = window;
360
361	stacked = i3200_is_stacked(pdev, drbs);
362
363	/*
364	 * The dram rank boundary (DRB) reg values are boundary addresses
365	 * for each DRAM rank with a granularity of 64MB.  DRB regs are
366	 * cumulative; the last one will contain the total memory
367	 * contained in all ranks.
368	 */
369	last_page = -1UL;
370	for (i = 0; i < mci->nr_csrows; i++) {
371		unsigned long nr_pages;
372		struct csrow_info *csrow = &mci->csrows[i];
373
374		nr_pages = drb_to_nr_pages(drbs, stacked,
375			i / I3200_RANKS_PER_CHANNEL,
376			i % I3200_RANKS_PER_CHANNEL);
377
378		if (nr_pages == 0) {
379			csrow->mtype = MEM_EMPTY;
380			continue;
381		}
382
383		csrow->first_page = last_page + 1;
384		last_page += nr_pages;
385		csrow->last_page = last_page;
386		csrow->nr_pages = nr_pages;
387
388		csrow->grain = nr_pages << PAGE_SHIFT;
389		csrow->mtype = MEM_DDR2;
390		csrow->dtype = DEV_UNKNOWN;
391		csrow->edac_mode = EDAC_UNKNOWN;
392	}
393
394	i3200_clear_error_info(mci);
395
396	rc = -ENODEV;
397	if (edac_mc_add_mc(mci)) {
398		debugf3("MC: %s(): failed edac_mc_add_mc()\n", __func__);
399		goto fail;
400	}
401
402	/* get this far and it's successful */
403	debugf3("MC: %s(): success\n", __func__);
404	return 0;
405
406fail:
407	iounmap(window);
408	if (mci)
409		edac_mc_free(mci);
410
411	return rc;
412}
413
414static int __devinit i3200_init_one(struct pci_dev *pdev,
415		const struct pci_device_id *ent)
416{
417	int rc;
418
419	debugf0("MC: %s()\n", __func__);
420
421	if (pci_enable_device(pdev) < 0)
422		return -EIO;
423
424	rc = i3200_probe1(pdev, ent->driver_data);
425	if (!mci_pdev)
426		mci_pdev = pci_dev_get(pdev);
427
428	return rc;
429}
430
431static void __devexit i3200_remove_one(struct pci_dev *pdev)
432{
433	struct mem_ctl_info *mci;
434	struct i3200_priv *priv;
435
436	debugf0("%s()\n", __func__);
437
438	mci = edac_mc_del_mc(&pdev->dev);
439	if (!mci)
440		return;
441
442	priv = mci->pvt_info;
443	iounmap(priv->window);
444
445	edac_mc_free(mci);
446}
447
448static DEFINE_PCI_DEVICE_TABLE(i3200_pci_tbl) = {
449	{
450		PCI_VEND_DEV(INTEL, 3200_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
451		I3200},
452	{
453		0,
454	}            /* 0 terminated list. */
455};
456
457MODULE_DEVICE_TABLE(pci, i3200_pci_tbl);
458
459static struct pci_driver i3200_driver = {
460	.name = EDAC_MOD_STR,
461	.probe = i3200_init_one,
462	.remove = __devexit_p(i3200_remove_one),
463	.id_table = i3200_pci_tbl,
464};
465
466static int __init i3200_init(void)
467{
468	int pci_rc;
469
470	debugf3("MC: %s()\n", __func__);
471
472	/* Ensure that the OPSTATE is set correctly for POLL or NMI */
473	opstate_init();
474
475	pci_rc = pci_register_driver(&i3200_driver);
476	if (pci_rc < 0)
477		goto fail0;
478
479	if (!mci_pdev) {
480		i3200_registered = 0;
481		mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
482				PCI_DEVICE_ID_INTEL_3200_HB, NULL);
483		if (!mci_pdev) {
484			debugf0("i3200 pci_get_device fail\n");
485			pci_rc = -ENODEV;
486			goto fail1;
487		}
488
489		pci_rc = i3200_init_one(mci_pdev, i3200_pci_tbl);
490		if (pci_rc < 0) {
491			debugf0("i3200 init fail\n");
492			pci_rc = -ENODEV;
493			goto fail1;
494		}
495	}
496
497	return 0;
498
499fail1:
500	pci_unregister_driver(&i3200_driver);
501
502fail0:
503	if (mci_pdev)
504		pci_dev_put(mci_pdev);
505
506	return pci_rc;
507}
508
509static void __exit i3200_exit(void)
510{
511	debugf3("MC: %s()\n", __func__);
512
513	pci_unregister_driver(&i3200_driver);
514	if (!i3200_registered) {
515		i3200_remove_one(mci_pdev);
516		pci_dev_put(mci_pdev);
517	}
518}
519
520module_init(i3200_init);
521module_exit(i3200_exit);
522
523MODULE_LICENSE("GPL");
524MODULE_AUTHOR("Akamai Technologies, Inc.");
525MODULE_DESCRIPTION("MC support for Intel 3200 memory hub controllers");
526
527module_param(edac_op_state, int, 0444);
528MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
529