intel_i2c.c revision 2d1a8a48ac68a835c42d8a31a02b8158cd599615 
1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 *   Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 *	Eric Anholt <eric@anholt.net>
27 *	Chris Wilson <chris@chris-wilson.co.uk>
28 */
29#include <linux/i2c.h>
30#include <linux/i2c-algo-bit.h>
31#include <linux/export.h>
32#include "drmP.h"
33#include "drm.h"
34#include "intel_drv.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
37
38/* Intel GPIO access functions */
39
40#define I2C_RISEFALL_TIME 20
41
42static inline struct intel_gmbus *
43to_intel_gmbus(struct i2c_adapter *i2c)
44{
45	return container_of(i2c, struct intel_gmbus, adapter);
46}
47
48struct intel_gpio {
49	struct i2c_adapter adapter;
50	struct i2c_algo_bit_data algo;
51	struct drm_i915_private *dev_priv;
52	u32 reg;
53};
54
55void
56intel_i2c_reset(struct drm_device *dev)
57{
58	struct drm_i915_private *dev_priv = dev->dev_private;
59	if (HAS_PCH_SPLIT(dev))
60		I915_WRITE(PCH_GMBUS0, 0);
61	else
62		I915_WRITE(GMBUS0, 0);
63}
64
65static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
66{
67	u32 val;
68
69	/* When using bit bashing for I2C, this bit needs to be set to 1 */
70	if (!IS_PINEVIEW(dev_priv->dev))
71		return;
72
73	val = I915_READ(DSPCLK_GATE_D);
74	if (enable)
75		val |= DPCUNIT_CLOCK_GATE_DISABLE;
76	else
77		val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
78	I915_WRITE(DSPCLK_GATE_D, val);
79}
80
81static u32 get_reserved(struct intel_gpio *gpio)
82{
83	struct drm_i915_private *dev_priv = gpio->dev_priv;
84	struct drm_device *dev = dev_priv->dev;
85	u32 reserved = 0;
86
87	/* On most chips, these bits must be preserved in software. */
88	if (!IS_I830(dev) && !IS_845G(dev))
89		reserved = I915_READ_NOTRACE(gpio->reg) &
90					     (GPIO_DATA_PULLUP_DISABLE |
91					      GPIO_CLOCK_PULLUP_DISABLE);
92
93	return reserved;
94}
95
96static int get_clock(void *data)
97{
98	struct intel_gpio *gpio = data;
99	struct drm_i915_private *dev_priv = gpio->dev_priv;
100	u32 reserved = get_reserved(gpio);
101	I915_WRITE_NOTRACE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK);
102	I915_WRITE_NOTRACE(gpio->reg, reserved);
103	return (I915_READ_NOTRACE(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
104}
105
106static int get_data(void *data)
107{
108	struct intel_gpio *gpio = data;
109	struct drm_i915_private *dev_priv = gpio->dev_priv;
110	u32 reserved = get_reserved(gpio);
111	I915_WRITE_NOTRACE(gpio->reg, reserved | GPIO_DATA_DIR_MASK);
112	I915_WRITE_NOTRACE(gpio->reg, reserved);
113	return (I915_READ_NOTRACE(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
114}
115
116static void set_clock(void *data, int state_high)
117{
118	struct intel_gpio *gpio = data;
119	struct drm_i915_private *dev_priv = gpio->dev_priv;
120	u32 reserved = get_reserved(gpio);
121	u32 clock_bits;
122
123	if (state_high)
124		clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
125	else
126		clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
127			GPIO_CLOCK_VAL_MASK;
128
129	I915_WRITE_NOTRACE(gpio->reg, reserved | clock_bits);
130	POSTING_READ(gpio->reg);
131}
132
133static void set_data(void *data, int state_high)
134{
135	struct intel_gpio *gpio = data;
136	struct drm_i915_private *dev_priv = gpio->dev_priv;
137	u32 reserved = get_reserved(gpio);
138	u32 data_bits;
139
140	if (state_high)
141		data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
142	else
143		data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
144			GPIO_DATA_VAL_MASK;
145
146	I915_WRITE_NOTRACE(gpio->reg, reserved | data_bits);
147	POSTING_READ(gpio->reg);
148}
149
150static struct i2c_adapter *
151intel_gpio_create(struct drm_i915_private *dev_priv, u32 pin)
152{
153	static const int map_pin_to_reg[] = {
154		0,
155		GPIOB,
156		GPIOA,
157		GPIOC,
158		GPIOD,
159		GPIOE,
160		0,
161		GPIOF,
162	};
163	struct intel_gpio *gpio;
164
165	if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin])
166		return NULL;
167
168	gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL);
169	if (gpio == NULL)
170		return NULL;
171
172	gpio->reg = map_pin_to_reg[pin];
173	if (HAS_PCH_SPLIT(dev_priv->dev))
174		gpio->reg += PCH_GPIOA - GPIOA;
175	gpio->dev_priv = dev_priv;
176
177	snprintf(gpio->adapter.name, sizeof(gpio->adapter.name),
178		 "i915 GPIO%c", "?BACDE?F"[pin]);
179	gpio->adapter.owner = THIS_MODULE;
180	gpio->adapter.algo_data	= &gpio->algo;
181	gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev;
182	gpio->algo.setsda = set_data;
183	gpio->algo.setscl = set_clock;
184	gpio->algo.getsda = get_data;
185	gpio->algo.getscl = get_clock;
186	gpio->algo.udelay = I2C_RISEFALL_TIME;
187	gpio->algo.timeout = usecs_to_jiffies(2200);
188	gpio->algo.data = gpio;
189
190	if (i2c_bit_add_bus(&gpio->adapter))
191		goto out_free;
192
193	return &gpio->adapter;
194
195out_free:
196	kfree(gpio);
197	return NULL;
198}
199
200static int
201intel_i2c_quirk_xfer(struct drm_i915_private *dev_priv,
202		     struct i2c_adapter *adapter,
203		     struct i2c_msg *msgs,
204		     int num)
205{
206	struct intel_gpio *gpio = container_of(adapter,
207					       struct intel_gpio,
208					       adapter);
209	int ret;
210
211	intel_i2c_reset(dev_priv->dev);
212
213	intel_i2c_quirk_set(dev_priv, true);
214	set_data(gpio, 1);
215	set_clock(gpio, 1);
216	udelay(I2C_RISEFALL_TIME);
217
218	ret = adapter->algo->master_xfer(adapter, msgs, num);
219
220	set_data(gpio, 1);
221	set_clock(gpio, 1);
222	intel_i2c_quirk_set(dev_priv, false);
223
224	return ret;
225}
226
227static int
228gmbus_xfer(struct i2c_adapter *adapter,
229	   struct i2c_msg *msgs,
230	   int num)
231{
232	struct intel_gmbus *bus = container_of(adapter,
233					       struct intel_gmbus,
234					       adapter);
235	struct drm_i915_private *dev_priv = adapter->algo_data;
236	int i, reg_offset;
237
238	if (bus->force_bit)
239		return intel_i2c_quirk_xfer(dev_priv,
240					    bus->force_bit, msgs, num);
241
242	reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;
243
244	I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
245
246	for (i = 0; i < num; i++) {
247		u16 len = msgs[i].len;
248		u8 *buf = msgs[i].buf;
249
250		if (msgs[i].flags & I2C_M_RD) {
251			I915_WRITE(GMBUS1 + reg_offset,
252				   GMBUS_CYCLE_WAIT | (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
253				   (len << GMBUS_BYTE_COUNT_SHIFT) |
254				   (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
255				   GMBUS_SLAVE_READ | GMBUS_SW_RDY);
256			POSTING_READ(GMBUS2+reg_offset);
257			do {
258				u32 val, loop = 0;
259
260				if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
261					goto timeout;
262				if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
263					goto clear_err;
264
265				val = I915_READ(GMBUS3 + reg_offset);
266				do {
267					*buf++ = val & 0xff;
268					val >>= 8;
269				} while (--len && ++loop < 4);
270			} while (len);
271		} else {
272			u32 val, loop;
273
274			val = loop = 0;
275			do {
276				val |= *buf++ << (8 * loop);
277			} while (--len && ++loop < 4);
278
279			I915_WRITE(GMBUS3 + reg_offset, val);
280			I915_WRITE(GMBUS1 + reg_offset,
281				   (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) |
282				   (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
283				   (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
284				   GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
285			POSTING_READ(GMBUS2+reg_offset);
286
287			while (len) {
288				if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
289					goto timeout;
290				if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
291					goto clear_err;
292
293				val = loop = 0;
294				do {
295					val |= *buf++ << (8 * loop);
296				} while (--len && ++loop < 4);
297
298				I915_WRITE(GMBUS3 + reg_offset, val);
299				POSTING_READ(GMBUS2+reg_offset);
300			}
301		}
302
303		if (i + 1 < num && wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
304			goto timeout;
305		if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
306			goto clear_err;
307	}
308
309	goto done;
310
311clear_err:
312	/* Toggle the Software Clear Interrupt bit. This has the effect
313	 * of resetting the GMBUS controller and so clearing the
314	 * BUS_ERROR raised by the slave's NAK.
315	 */
316	I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
317	I915_WRITE(GMBUS1 + reg_offset, 0);
318
319done:
320	/* Mark the GMBUS interface as disabled. We will re-enable it at the
321	 * start of the next xfer, till then let it sleep.
322	 */
323	I915_WRITE(GMBUS0 + reg_offset, 0);
324	return i;
325
326timeout:
327	DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
328		 bus->reg0 & 0xff, bus->adapter.name);
329	I915_WRITE(GMBUS0 + reg_offset, 0);
330
331	/* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
332	bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
333	if (!bus->force_bit)
334		return -ENOMEM;
335
336	return intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num);
337}
338
339static u32 gmbus_func(struct i2c_adapter *adapter)
340{
341	struct intel_gmbus *bus = container_of(adapter,
342					       struct intel_gmbus,
343					       adapter);
344
345	if (bus->force_bit)
346		bus->force_bit->algo->functionality(bus->force_bit);
347
348	return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
349		/* I2C_FUNC_10BIT_ADDR | */
350		I2C_FUNC_SMBUS_READ_BLOCK_DATA |
351		I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
352}
353
354static const struct i2c_algorithm gmbus_algorithm = {
355	.master_xfer	= gmbus_xfer,
356	.functionality	= gmbus_func
357};
358
359/**
360 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
361 * @dev: DRM device
362 */
363int intel_setup_gmbus(struct drm_device *dev)
364{
365	static const char *names[GMBUS_NUM_PORTS] = {
366		"disabled",
367		"ssc",
368		"vga",
369		"panel",
370		"dpc",
371		"dpb",
372		"reserved",
373		"dpd",
374	};
375	struct drm_i915_private *dev_priv = dev->dev_private;
376	int ret, i;
377
378	dev_priv->gmbus = kcalloc(sizeof(struct intel_gmbus), GMBUS_NUM_PORTS,
379				  GFP_KERNEL);
380	if (dev_priv->gmbus == NULL)
381		return -ENOMEM;
382
383	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
384		struct intel_gmbus *bus = &dev_priv->gmbus[i];
385
386		bus->adapter.owner = THIS_MODULE;
387		bus->adapter.class = I2C_CLASS_DDC;
388		snprintf(bus->adapter.name,
389			 sizeof(bus->adapter.name),
390			 "i915 gmbus %s",
391			 names[i]);
392
393		bus->adapter.dev.parent = &dev->pdev->dev;
394		bus->adapter.algo_data	= dev_priv;
395
396		bus->adapter.algo = &gmbus_algorithm;
397		ret = i2c_add_adapter(&bus->adapter);
398		if (ret)
399			goto err;
400
401		/* By default use a conservative clock rate */
402		bus->reg0 = i | GMBUS_RATE_100KHZ;
403
404		/* XXX force bit banging until GMBUS is fully debugged */
405		bus->force_bit = intel_gpio_create(dev_priv, i);
406	}
407
408	intel_i2c_reset(dev_priv->dev);
409
410	return 0;
411
412err:
413	while (--i) {
414		struct intel_gmbus *bus = &dev_priv->gmbus[i];
415		i2c_del_adapter(&bus->adapter);
416	}
417	kfree(dev_priv->gmbus);
418	dev_priv->gmbus = NULL;
419	return ret;
420}
421
422void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
423{
424	struct intel_gmbus *bus = to_intel_gmbus(adapter);
425
426	bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
427}
428
429void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
430{
431	struct intel_gmbus *bus = to_intel_gmbus(adapter);
432
433	if (force_bit) {
434		if (bus->force_bit == NULL) {
435			struct drm_i915_private *dev_priv = adapter->algo_data;
436			bus->force_bit = intel_gpio_create(dev_priv,
437							   bus->reg0 & 0xff);
438		}
439	} else {
440		if (bus->force_bit) {
441			i2c_del_adapter(bus->force_bit);
442			kfree(bus->force_bit);
443			bus->force_bit = NULL;
444		}
445	}
446}
447
448void intel_teardown_gmbus(struct drm_device *dev)
449{
450	struct drm_i915_private *dev_priv = dev->dev_private;
451	int i;
452
453	if (dev_priv->gmbus == NULL)
454		return;
455
456	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
457		struct intel_gmbus *bus = &dev_priv->gmbus[i];
458		if (bus->force_bit) {
459			i2c_del_adapter(bus->force_bit);
460			kfree(bus->force_bit);
461		}
462		i2c_del_adapter(&bus->adapter);
463	}
464
465	kfree(dev_priv->gmbus);
466	dev_priv->gmbus = NULL;
467}
468