| 6a562e3daee217ce99fe0e31150acd89a5b22606 |
|
09-Apr-2012 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
Revert "drm/i915: reenable gmbus on gen3+ again"
This reverts commit c3dfefa0a6d235bd465309e12f4c56ea16e71111.
gmbus in 3.4 has simply too many known issues:
- gmbus is too noisy, we need to rework the logging:
https://bugs.freedesktop.org/show_bug.cgi?id=48248
- zero-length writes cause an OOPS, and they are
userspace-triggerable:
https://lkml.org/lkml/2012/3/30/176
- same for zero-length reads:
https://bugs.freedesktop.org/show_bug.cgi?id=48269
We can try again for 3.5.
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
|
| c3dfefa0a6d235bd465309e12f4c56ea16e71111 |
|
14-Feb-2012 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: reenable gmbus on gen3+ again
With the rework to merge the bit-banging fallback into the gmbus
i2c adapter we've gotten rid of the deadlock possibility that
originally lead to the disabling of this code.
This reverts the revert
commit 826c7e4147f902737b281e8a5a7d7aa33fd63316
Author: Jean Delvare <khali@linux-fr.org>
Date: Sat Jun 4 19:34:56 2011 +0000
Revert "drm/i915: Enable GMBUS for post-gen2 chipsets"
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=35572
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
|
| f6f808c8e1c4a3b7e3e0a6cb81541ec615aeb5fd |
|
14-Feb-2012 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: i2c: unconditionally set up gpio fallback
This way we can simplify the setup and teardown a bit.
Because we don't actually allocate anything anymore for the force_bit
case, we can now convert that into a boolean.
Also and the functionality supported by the bit-banging together with
what gmbus can do, so that this doesn't randomly change any more.
v2: Chris Wilson noticed that I've mixed up && and & ...
v3: Clarify an if block as suggested by Eugeni Dodonov.
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
|
| c167a6fc6ed78a300c29181a6caf9ae1b9993289 |
|
28-Feb-2012 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: merge gmbus and gpio i2c adpater into one
... and directly call the newly exported i2c bit-banging functions.
The code is still pretty convoluted because we only set up the gpio
i2c stuff when actually falling back, resulting in more complexity
than necessary. This will be fixed up in the next patch.
v2: Use exported i2c_bit_algo vtable instead of exported functions.
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
|
| 36c785f051b21728775c9c4f2621d37d586553d0 |
|
14-Feb-2012 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: merge struct intel_gpio into struct intel_gmbus
When we set up the gpio fallback, we always have a 1:1 relationship
with an intel_gmbus. Exploit that to store all gpio related data in
there, too. This is a preparation step to merge the tw i2c adapters
controlling the same bus into one.
Just mundane code-munging in this patch.
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
|
| c2b9152f098e213dc5f2e8a4dbbfe090302c58ed |
|
14-Feb-2012 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: add dev_priv to intel_gmbus
This way we can free up the bus->adaptor.algo_data pointer and make it
available for use with the bitbanging fallback algo.
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
|
| caae745a352377f48f6eb43b5040214d803a885f |
|
09-Feb-2012 |
Benson Leung <bleung@chromium.org> |
drm/i915: Fix single msg gmbus_xfers writes
gmbus_xfer with a single message (particularly a single message write) would
set Bus Cycle Select to 100b, the Gen Stop cycle, instead of 101b,
No Index, Stop cycle. This would not start single message i2c transactions.
Also, gmbus_xfer done: will disable the interface without checking if
it is idle. In the case of writes, there will be no wait on status or delay
to ensure the write starts and completes before the interface is turned off.
Fixed the former issue by using the same cycle selection as used in the
I2C_M_RD for the write case.
GMBUS_CYCLE_WAIT | (i + 1 == num ? GMBUS_CYCLE_STOP : 0)
Fixed the latter by waiting on GMBUS_ACTIVE to deassert before disable.
Note from the grumpy d-i-n maintainer: The first hunk that changes the
gmbus read path is just cosmetics to align the code with the write
path. I.e. the commit message above is slightly lying because the
first issue is _only_ with writes (and not simply "particularly").
Signed-off-by: Benson Leung <bleung@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
|
| 8a8ed1f5143b3df312e436ab15290e4a7ca6a559 |
|
13-Feb-2012 |
Yufeng Shen <miletus@chromium.org> |
drm/i915: Fix race condition in accessing GMBUS
GMBUS has several ports and each has it's own corresponding
I2C adpater. When multiple I2C adapters call gmbus_xfer() at
the same time there is a race condition in using the underlying
GMBUS controller. Fixing this by adding a mutex lock when calling
gmbus_xfer().
v2: Moved gmbus_mutex below intel_gmbus and added comments.
Rebased to drm-intel-next-queued.
Signed-off-by: Yufeng Shen <miletus@chromium.org>
[danvet: Shortened the gmbus_mutex comment a bit and add the patch
revision comment to the commit message.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
|
| 51a59ac8739b333eaa43a3102b6acaab5037bfa2 |
|
10-Feb-2012 |
Axel Lin <axel.lin@gmail.com> |
drm: Fix kcalloc parameters swapped
The first parameter should be "number of elements" and the second parameter
should be "element size".
Signed-off-by: Axel Lin <axel.lin@gmail.com>
Acked-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
|
| 1849ecb22fb3b5d57b65e7369a3957adf9f26f39 |
|
28-Jan-2012 |
Jean Delvare <jdelvare@suse.de> |
drm/kms: Make i2c buses faster
A udelay value of 20 leads to an I2C bus running at only 25 kbps. I2C
devices can typically operate faster than this, 50 kbps should be fine
for all devices (and compliant devices can always stretch the clock if
needed.)
FWIW, the vast majority of framebuffer drivers set udelay to 10
already. So set it to 10 in DRM drivers too, this will make EDID block
reads faster. We might even lower the udelay value later if no problem
is reported.
Signed-off-by: Jean Delvare <jdelvare@suse.de>
Acked-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Cc: Keith Packard <keithp@keithp.com>
Reviewed-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
|
| 2d1a8a48ac68a835c42d8a31a02b8158cd599615 |
|
31-Aug-2011 |
Paul Gortmaker <paul.gortmaker@windriver.com> |
gpu: Add export.h as required to drivers/gpu files.
They need this to get all the EXPORT_SYMBOL variants and THIS_MODULE
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
|
| d5090b96256b9bc479514d54cb55dcaba3144a8d |
|
16-Jun-2011 |
Adam Jackson <ajax@redhat.com> |
drm/i915: Remove redundant bit shifting from intel_gmbus_set_speed
Signed-off-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>
|
| 826c7e4147f902737b281e8a5a7d7aa33fd63316 |
|
04-Jun-2011 |
Jean Delvare <khali@linux-fr.org> |
Revert "drm/i915: Enable GMBUS for post-gen2 chipsets"
Revert commit 8f9a3f9b63b8cd3f03be9dc53533f90bd4120e5f. This fixes a
hang when loading the eeprom driver (see bug #35572.) GMBUS will be
re-enabled later, differently.
Signed-off-by: Jean Delvare <khali@linux-fr.org>
Reported-by: Marek Otahal <markotahal@gmail.com>
Tested-by: Yermandu Patapitafious <yermandu.dev@gmail.com>
Tested-by: Andrew Lutomirski <luto@mit.edu>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Dave Airlie <airlied@redhat.com>
|
| 7f58aabc369014fda3a4a33604ba0a1b63b941ac |
|
30-Mar-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Reset GMBUS controller after NAK
Once a NAK has been asserted by the slave, we need to reset the GMBUS
controller in order to continue. This is done by asserting the Software
Clear Interrupt bit and then clearing it again to restore operations.
If we don't clear the NAK, then all future GMBUS xfers will fail,
including DDC probes and EDID retrieval.
v2: Add some comments as suggested by Keith Packard.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35781
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Keith Packard <keithp@keithp.com>
Tested-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: "Mengmeng Meng" <mengmeng.meng@intel.com>
|
| 8f9a3f9b63b8cd3f03be9dc53533f90bd4120e5f |
|
01-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Enable GMBUS for post-gen2 chipsets
With the recent SDVO fix, this is working on all the machines I have to
hand - except for an 845G.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
|
| 69669455b049c0f1f04bb306625c5d4db6838b11 |
|
05-Nov-2010 |
Jean Delvare <khali@linux-fr.org> |
drm/i915: Fix I2C adapter registration
Fix many small bugs in I2C adapter registration:
* Properly reject unsupported GPIO pin.
* Fix improper use of I2C_NAME_SIZE (which is the size of
i2c_client.name, not i2c_adapter.name.)
* Prefix adapter names with "i915" so that the user knows what the
I2C channel is connected to.
* Fix swapped characters in the string used to name the GPIO-based
adapter.
* Add missing comma in gmbus name table.
Signed-off-by: Jean Delvare <khali@linux-fr.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
|
| 374c479bef7ecd2b41d6dd6e24aa21d73b3afae5 |
|
08-Nov-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: POSTING_READs are simply flushes and so irrelevant to tracing
As we use POSTING_READ to flush the write to the register before
proceeding, we do not care what the return value is and similar we do
not care for the read to be recorded whilst tracing register
read/writes.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
|
| db5e4172a023cff68b3597ace8a5390b02669d27 |
|
08-Nov-2010 |
Yuanhan Liu <yuanhan.liu@linux.intel.com> |
drm/i915: filter out the read/write of GPIO registers from debug tracing
These registers are written very frequently, are timing sensitive, and
not particularly relevant to any debugging, so remove the tracepoints
from these.
Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
|
| 7b5337ddbaf7e4b71ef6fd6307c6f9ef84f636e9 |
|
13-Oct-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
drm/i915: Fix GPIO pin to register mapping
In i2c GPIO fallback, index 6 is reserved for nothing.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
|
| cb8ea7527b813dd6e19fb07328f7867a5f0a8d0a |
|
28-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Use i2c bit banging instead of GMBUS
There are several reported instances of GMBUS failing to successfully
read the EDID, so revert back to bit banging until the issue is
resolved.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=30371
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
|
| e957d7720a2797b31231616014b68f4f6203145e |
|
24-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915/sdvo: Fix GMBUSification
Besides a couple of bugs when writing more than a single byte along the
GMBUS, SDVO was completely failing whilst trying to use GMBUS, so use
bit banging instead.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
|
| f899fc64cda8569d0529452aafc0da31c042df2e |
|
21-Jul-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: use GMBUS to manage i2c links
Use the GMBUS interface rather than direct bit banging to grab the EDID
over DDC (and for other forms of auxiliary communication with external
display controllers). The hope is that this method will be much faster
and more reliable than bit banging for fetching EDIDs from buggy monitors
or through switches, though we still preserve the bit banging as a
fallback in case GMBUS fails.
Based on an original patch by Jesse Barnes.
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
|
| 890f3359f7b84d7015104360d647ccac5f515542 |
|
14-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915/i2c: Track the parent encoder rather than just the dev
The SDVO proxy i2c adapter wants to be able to use information stored in
the encoder, so pass that through intel_i2c rather than iterate over all
known encoders every time.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
|
| b222f2673354c65e178cbcba610e7883a05f5bf3 |
|
11-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915/i2c: The bit-banging interface controls the delay, drop ours
Remove our redundant udelay() as the timings are already handled by the
i2c-algo-bit controller.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
|
| 5a0e3ad6af8660be21ca98a971cd00f331318c05 |
|
24-Mar-2010 |
Tejun Heo <tj@kernel.org> |
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
|
| c619eed4b2ee1b2bde3e02464eb81632a08bb976 |
|
29-Jan-2010 |
Eric Anholt <eric@anholt.net> |
drm/i915: More s/IS_IRONLAKE/HAS_PCH_SPLIT for Sandybridge.
I think this is pretty much correct. Not really tested.
Signed-off-by: Eric Anholt <eric@anholt.net>
|
| f2b115e69d46344ae7afcaad5823496d2a0d8650 |
|
03-Dec-2009 |
Adam Jackson <ajax@redhat.com> |
drm/i915: Fix product names and #defines
IGD* isn't a useful name. Replace with the codenames, as sourced from
pci.ids.
Signed-off-by: Adam Jackson <ajax@redhat.com>
[anholt: Fixed up for merge with pineview/ironlake changes]
Signed-off-by: Eric Anholt <eric@anholt.net>
|
| f0217c42c9ab3d772e543f635ce628b9478f70b6 |
|
01-Dec-2009 |
Eric Anholt <eric@anholt.net> |
drm/i915: Fix DDC on some systems by clearing BIOS GMBUS setup.
This is a sync of a fix I made in the old UMS code. If the BIOS uses
the GMBUS and doesn't clear that setup, then our bit-banging I2C can
fail, leading to monitors not being detected.
Signed-off-by: Eric Anholt <eric@anholt.net>
|
| 652c393a3368af84359da37c45afc35a91144960 |
|
17-Aug-2009 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: add dynamic clock frequency control
There are several sources of unnecessary power consumption on Intel
graphics systems. The first is the LVDS clock. TFTs don't suffer from
persistence issues like CRTs, and so we can reduce the LVDS refresh rate
when the screen is idle. It will be automatically upclocked when
userspace triggers graphical activity. Beyond that, we can enable memory
self refresh. This allows the memory to go into a lower power state when
the graphics are idle. Finally, we can drop some clocks on the gpu
itself. All of these things can be reenabled between frames when GPU
activity is triggered, and so there should be no user visible graphical
changes.
Signed-off-by: Jesse Barnes <jesse.barnes@intel.com>
Signed-off-by: Matthew Garrett <mjg@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
|
| f9c10a9b96a31b4a82a4fa807400c04f00284068 |
|
30-May-2009 |
Keith Packard <keithp@keithp.com> |
drm/i915: Change I2C api to pass around i2c_adapters
The existing API passed around intel_i2c_chan pointers, which are dependent
on the i2c bit-banging algo. This precluded the driver from using outputs
which use a different algo. Switching to the more general i2c_adpater allows
the driver to support non bit-banging DDC.
This also required moving the slave address into the output private
structures.
Signed-off-by: Keith Packard <keithp@keithp.com>
|
| 0ba0e9e1f173a59ba402a253d356612c821b7a14 |
|
07-Apr-2009 |
Shaohua Li <shaohua.li@intel.com> |
drm/i915: workaround IGD i2c bus issue in kernel side (v2)
In IGD, DPCUNIT_CLOCK_GATE_DISABLE bit should be set, otherwise i2c
access will be wrong.
v2: Disable CLOCK_GATE_DISABLE bit after bit bashing as suggested by Eric.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
|
| 1745522ccbabd990bfc7511861aa9fa98287cba0 |
|
26-Jan-2009 |
Jean Delvare <khali@linux-fr.org> |
i2c: Delete many unused adapter IDs
Signed-off-by: Jean Delvare <khali@linux-fr.org>
|
| 79e539453b34e35f39299a899d263b0a1f1670bd |
|
07-Nov-2008 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
|