intel_i2c.c revision 7f58aabc369014fda3a4a33604ba0a1b63b941ac 
1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 *   Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 *	Eric Anholt <eric@anholt.net>
27 *	Chris Wilson <chris@chris-wilson.co.uk>
28 */
29#include <linux/i2c.h>
30#include <linux/i2c-algo-bit.h>
31#include "drmP.h"
32#include "drm.h"
33#include "intel_drv.h"
34#include "i915_drm.h"
35#include "i915_drv.h"
36
37/* Intel GPIO access functions */
38
39#define I2C_RISEFALL_TIME 20
40
41static inline struct intel_gmbus *
42to_intel_gmbus(struct i2c_adapter *i2c)
43{
44	return container_of(i2c, struct intel_gmbus, adapter);
45}
46
47struct intel_gpio {
48	struct i2c_adapter adapter;
49	struct i2c_algo_bit_data algo;
50	struct drm_i915_private *dev_priv;
51	u32 reg;
52};
53
54void
55intel_i2c_reset(struct drm_device *dev)
56{
57	struct drm_i915_private *dev_priv = dev->dev_private;
58	if (HAS_PCH_SPLIT(dev))
59		I915_WRITE(PCH_GMBUS0, 0);
60	else
61		I915_WRITE(GMBUS0, 0);
62}
63
64static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
65{
66	u32 val;
67
68	/* When using bit bashing for I2C, this bit needs to be set to 1 */
69	if (!IS_PINEVIEW(dev_priv->dev))
70		return;
71
72	val = I915_READ(DSPCLK_GATE_D);
73	if (enable)
74		val |= DPCUNIT_CLOCK_GATE_DISABLE;
75	else
76		val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
77	I915_WRITE(DSPCLK_GATE_D, val);
78}
79
80static u32 get_reserved(struct intel_gpio *gpio)
81{
82	struct drm_i915_private *dev_priv = gpio->dev_priv;
83	struct drm_device *dev = dev_priv->dev;
84	u32 reserved = 0;
85
86	/* On most chips, these bits must be preserved in software. */
87	if (!IS_I830(dev) && !IS_845G(dev))
88		reserved = I915_READ_NOTRACE(gpio->reg) &
89					     (GPIO_DATA_PULLUP_DISABLE |
90					      GPIO_CLOCK_PULLUP_DISABLE);
91
92	return reserved;
93}
94
95static int get_clock(void *data)
96{
97	struct intel_gpio *gpio = data;
98	struct drm_i915_private *dev_priv = gpio->dev_priv;
99	u32 reserved = get_reserved(gpio);
100	I915_WRITE_NOTRACE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK);
101	I915_WRITE_NOTRACE(gpio->reg, reserved);
102	return (I915_READ_NOTRACE(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
103}
104
105static int get_data(void *data)
106{
107	struct intel_gpio *gpio = data;
108	struct drm_i915_private *dev_priv = gpio->dev_priv;
109	u32 reserved = get_reserved(gpio);
110	I915_WRITE_NOTRACE(gpio->reg, reserved | GPIO_DATA_DIR_MASK);
111	I915_WRITE_NOTRACE(gpio->reg, reserved);
112	return (I915_READ_NOTRACE(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
113}
114
115static void set_clock(void *data, int state_high)
116{
117	struct intel_gpio *gpio = data;
118	struct drm_i915_private *dev_priv = gpio->dev_priv;
119	u32 reserved = get_reserved(gpio);
120	u32 clock_bits;
121
122	if (state_high)
123		clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
124	else
125		clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
126			GPIO_CLOCK_VAL_MASK;
127
128	I915_WRITE_NOTRACE(gpio->reg, reserved | clock_bits);
129	POSTING_READ(gpio->reg);
130}
131
132static void set_data(void *data, int state_high)
133{
134	struct intel_gpio *gpio = data;
135	struct drm_i915_private *dev_priv = gpio->dev_priv;
136	u32 reserved = get_reserved(gpio);
137	u32 data_bits;
138
139	if (state_high)
140		data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
141	else
142		data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
143			GPIO_DATA_VAL_MASK;
144
145	I915_WRITE_NOTRACE(gpio->reg, reserved | data_bits);
146	POSTING_READ(gpio->reg);
147}
148
149static struct i2c_adapter *
150intel_gpio_create(struct drm_i915_private *dev_priv, u32 pin)
151{
152	static const int map_pin_to_reg[] = {
153		0,
154		GPIOB,
155		GPIOA,
156		GPIOC,
157		GPIOD,
158		GPIOE,
159		0,
160		GPIOF,
161	};
162	struct intel_gpio *gpio;
163
164	if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin])
165		return NULL;
166
167	gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL);
168	if (gpio == NULL)
169		return NULL;
170
171	gpio->reg = map_pin_to_reg[pin];
172	if (HAS_PCH_SPLIT(dev_priv->dev))
173		gpio->reg += PCH_GPIOA - GPIOA;
174	gpio->dev_priv = dev_priv;
175
176	snprintf(gpio->adapter.name, sizeof(gpio->adapter.name),
177		 "i915 GPIO%c", "?BACDE?F"[pin]);
178	gpio->adapter.owner = THIS_MODULE;
179	gpio->adapter.algo_data	= &gpio->algo;
180	gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev;
181	gpio->algo.setsda = set_data;
182	gpio->algo.setscl = set_clock;
183	gpio->algo.getsda = get_data;
184	gpio->algo.getscl = get_clock;
185	gpio->algo.udelay = I2C_RISEFALL_TIME;
186	gpio->algo.timeout = usecs_to_jiffies(2200);
187	gpio->algo.data = gpio;
188
189	if (i2c_bit_add_bus(&gpio->adapter))
190		goto out_free;
191
192	return &gpio->adapter;
193
194out_free:
195	kfree(gpio);
196	return NULL;
197}
198
199static int
200intel_i2c_quirk_xfer(struct drm_i915_private *dev_priv,
201		     struct i2c_adapter *adapter,
202		     struct i2c_msg *msgs,
203		     int num)
204{
205	struct intel_gpio *gpio = container_of(adapter,
206					       struct intel_gpio,
207					       adapter);
208	int ret;
209
210	intel_i2c_reset(dev_priv->dev);
211
212	intel_i2c_quirk_set(dev_priv, true);
213	set_data(gpio, 1);
214	set_clock(gpio, 1);
215	udelay(I2C_RISEFALL_TIME);
216
217	ret = adapter->algo->master_xfer(adapter, msgs, num);
218
219	set_data(gpio, 1);
220	set_clock(gpio, 1);
221	intel_i2c_quirk_set(dev_priv, false);
222
223	return ret;
224}
225
226static int
227gmbus_xfer(struct i2c_adapter *adapter,
228	   struct i2c_msg *msgs,
229	   int num)
230{
231	struct intel_gmbus *bus = container_of(adapter,
232					       struct intel_gmbus,
233					       adapter);
234	struct drm_i915_private *dev_priv = adapter->algo_data;
235	int i, reg_offset;
236
237	if (bus->force_bit)
238		return intel_i2c_quirk_xfer(dev_priv,
239					    bus->force_bit, msgs, num);
240
241	reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;
242
243	I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
244
245	for (i = 0; i < num; i++) {
246		u16 len = msgs[i].len;
247		u8 *buf = msgs[i].buf;
248
249		if (msgs[i].flags & I2C_M_RD) {
250			I915_WRITE(GMBUS1 + reg_offset,
251				   GMBUS_CYCLE_WAIT | (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
252				   (len << GMBUS_BYTE_COUNT_SHIFT) |
253				   (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
254				   GMBUS_SLAVE_READ | GMBUS_SW_RDY);
255			POSTING_READ(GMBUS2+reg_offset);
256			do {
257				u32 val, loop = 0;
258
259				if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
260					goto timeout;
261				if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
262					goto clear_err;
263
264				val = I915_READ(GMBUS3 + reg_offset);
265				do {
266					*buf++ = val & 0xff;
267					val >>= 8;
268				} while (--len && ++loop < 4);
269			} while (len);
270		} else {
271			u32 val, loop;
272
273			val = loop = 0;
274			do {
275				val |= *buf++ << (8 * loop);
276			} while (--len && ++loop < 4);
277
278			I915_WRITE(GMBUS3 + reg_offset, val);
279			I915_WRITE(GMBUS1 + reg_offset,
280				   (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) |
281				   (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
282				   (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
283				   GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
284			POSTING_READ(GMBUS2+reg_offset);
285
286			while (len) {
287				if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
288					goto timeout;
289				if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
290					goto clear_err;
291
292				val = loop = 0;
293				do {
294					val |= *buf++ << (8 * loop);
295				} while (--len && ++loop < 4);
296
297				I915_WRITE(GMBUS3 + reg_offset, val);
298				POSTING_READ(GMBUS2+reg_offset);
299			}
300		}
301
302		if (i + 1 < num && wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
303			goto timeout;
304		if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
305			goto clear_err;
306	}
307
308	goto done;
309
310clear_err:
311	/* Toggle the Software Clear Interrupt bit. This has the effect
312	 * of resetting the GMBUS controller and so clearing the
313	 * BUS_ERROR raised by the slave's NAK.
314	 */
315	I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
316	I915_WRITE(GMBUS1 + reg_offset, 0);
317
318done:
319	/* Mark the GMBUS interface as disabled. We will re-enable it at the
320	 * start of the next xfer, till then let it sleep.
321	 */
322	I915_WRITE(GMBUS0 + reg_offset, 0);
323	return i;
324
325timeout:
326	DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
327		 bus->reg0 & 0xff, bus->adapter.name);
328	I915_WRITE(GMBUS0 + reg_offset, 0);
329
330	/* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
331	bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
332	if (!bus->force_bit)
333		return -ENOMEM;
334
335	return intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num);
336}
337
338static u32 gmbus_func(struct i2c_adapter *adapter)
339{
340	struct intel_gmbus *bus = container_of(adapter,
341					       struct intel_gmbus,
342					       adapter);
343
344	if (bus->force_bit)
345		bus->force_bit->algo->functionality(bus->force_bit);
346
347	return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
348		/* I2C_FUNC_10BIT_ADDR | */
349		I2C_FUNC_SMBUS_READ_BLOCK_DATA |
350		I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
351}
352
353static const struct i2c_algorithm gmbus_algorithm = {
354	.master_xfer	= gmbus_xfer,
355	.functionality	= gmbus_func
356};
357
358/**
359 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
360 * @dev: DRM device
361 */
362int intel_setup_gmbus(struct drm_device *dev)
363{
364	static const char *names[GMBUS_NUM_PORTS] = {
365		"disabled",
366		"ssc",
367		"vga",
368		"panel",
369		"dpc",
370		"dpb",
371		"reserved",
372		"dpd",
373	};
374	struct drm_i915_private *dev_priv = dev->dev_private;
375	int ret, i;
376
377	dev_priv->gmbus = kcalloc(sizeof(struct intel_gmbus), GMBUS_NUM_PORTS,
378				  GFP_KERNEL);
379	if (dev_priv->gmbus == NULL)
380		return -ENOMEM;
381
382	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
383		struct intel_gmbus *bus = &dev_priv->gmbus[i];
384
385		bus->adapter.owner = THIS_MODULE;
386		bus->adapter.class = I2C_CLASS_DDC;
387		snprintf(bus->adapter.name,
388			 sizeof(bus->adapter.name),
389			 "i915 gmbus %s",
390			 names[i]);
391
392		bus->adapter.dev.parent = &dev->pdev->dev;
393		bus->adapter.algo_data	= dev_priv;
394
395		bus->adapter.algo = &gmbus_algorithm;
396		ret = i2c_add_adapter(&bus->adapter);
397		if (ret)
398			goto err;
399
400		/* By default use a conservative clock rate */
401		bus->reg0 = i | GMBUS_RATE_100KHZ;
402
403		/* XXX force bit banging until GMBUS is fully debugged */
404		if (IS_GEN2(dev))
405			bus->force_bit = intel_gpio_create(dev_priv, i);
406	}
407
408	intel_i2c_reset(dev_priv->dev);
409
410	return 0;
411
412err:
413	while (--i) {
414		struct intel_gmbus *bus = &dev_priv->gmbus[i];
415		i2c_del_adapter(&bus->adapter);
416	}
417	kfree(dev_priv->gmbus);
418	dev_priv->gmbus = NULL;
419	return ret;
420}
421
422void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
423{
424	struct intel_gmbus *bus = to_intel_gmbus(adapter);
425
426	/* speed:
427	 * 0x0 = 100 KHz
428	 * 0x1 = 50 KHz
429	 * 0x2 = 400 KHz
430	 * 0x3 = 1000 Khz
431	 */
432	bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | (speed << 8);
433}
434
435void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
436{
437	struct intel_gmbus *bus = to_intel_gmbus(adapter);
438
439	if (force_bit) {
440		if (bus->force_bit == NULL) {
441			struct drm_i915_private *dev_priv = adapter->algo_data;
442			bus->force_bit = intel_gpio_create(dev_priv,
443							   bus->reg0 & 0xff);
444		}
445	} else {
446		if (bus->force_bit) {
447			i2c_del_adapter(bus->force_bit);
448			kfree(bus->force_bit);
449			bus->force_bit = NULL;
450		}
451	}
452}
453
454void intel_teardown_gmbus(struct drm_device *dev)
455{
456	struct drm_i915_private *dev_priv = dev->dev_private;
457	int i;
458
459	if (dev_priv->gmbus == NULL)
460		return;
461
462	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
463		struct intel_gmbus *bus = &dev_priv->gmbus[i];
464		if (bus->force_bit) {
465			i2c_del_adapter(bus->force_bit);
466			kfree(bus->force_bit);
467		}
468		i2c_del_adapter(&bus->adapter);
469	}
470
471	kfree(dev_priv->gmbus);
472	dev_priv->gmbus = NULL;
473}
474