1/* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24#ifndef EVERGREEND_H 25#define EVERGREEND_H 26 27#define EVERGREEN_MAX_SH_GPRS 256 28#define EVERGREEN_MAX_TEMP_GPRS 16 29#define EVERGREEN_MAX_SH_THREADS 256 30#define EVERGREEN_MAX_SH_STACK_ENTRIES 4096 31#define EVERGREEN_MAX_FRC_EOV_CNT 16384 32#define EVERGREEN_MAX_BACKENDS 8 33#define EVERGREEN_MAX_BACKENDS_MASK 0xFF 34#define EVERGREEN_MAX_SIMDS 16 35#define EVERGREEN_MAX_SIMDS_MASK 0xFFFF 36#define EVERGREEN_MAX_PIPES 8 37#define EVERGREEN_MAX_PIPES_MASK 0xFF 38#define EVERGREEN_MAX_LDS_NUM 0xFFFF 39 40/* Registers */ 41 42#define RCU_IND_INDEX 0x100 43#define RCU_IND_DATA 0x104 44 45#define GRBM_GFX_INDEX 0x802C 46#define INSTANCE_INDEX(x) ((x) << 0) 47#define SE_INDEX(x) ((x) << 16) 48#define INSTANCE_BROADCAST_WRITES (1 << 30) 49#define SE_BROADCAST_WRITES (1 << 31) 50#define RLC_GFX_INDEX 0x3fC4 51#define CC_GC_SHADER_PIPE_CONFIG 0x8950 52#define WRITE_DIS (1 << 0) 53#define CC_RB_BACKEND_DISABLE 0x98F4 54#define BACKEND_DISABLE(x) ((x) << 16) 55#define GB_ADDR_CONFIG 0x98F8 56#define NUM_PIPES(x) ((x) << 0) 57#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 58#define BANK_INTERLEAVE_SIZE(x) ((x) << 8) 59#define NUM_SHADER_ENGINES(x) ((x) << 12) 60#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 61#define NUM_GPUS(x) ((x) << 20) 62#define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 63#define ROW_SIZE(x) ((x) << 28) 64#define GB_BACKEND_MAP 0x98FC 65#define DMIF_ADDR_CONFIG 0xBD4 66#define HDP_ADDR_CONFIG 0x2F48 67#define HDP_MISC_CNTL 0x2F4C 68#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 69 70#define CC_SYS_RB_BACKEND_DISABLE 0x3F88 71#define GC_USER_RB_BACKEND_DISABLE 0x9B7C 72 73#define CGTS_SYS_TCC_DISABLE 0x3F90 74#define CGTS_TCC_DISABLE 0x9148 75#define CGTS_USER_SYS_TCC_DISABLE 0x3F94 76#define CGTS_USER_TCC_DISABLE 0x914C 77 78#define CONFIG_MEMSIZE 0x5428 79 80#define CP_COHER_BASE 0x85F8 81#define CP_ME_CNTL 0x86D8 82#define CP_ME_HALT (1 << 28) 83#define CP_PFP_HALT (1 << 26) 84#define CP_ME_RAM_DATA 0xC160 85#define CP_ME_RAM_RADDR 0xC158 86#define CP_ME_RAM_WADDR 0xC15C 87#define CP_MEQ_THRESHOLDS 0x8764 88#define STQ_SPLIT(x) ((x) << 0) 89#define CP_PERFMON_CNTL 0x87FC 90#define CP_PFP_UCODE_ADDR 0xC150 91#define CP_PFP_UCODE_DATA 0xC154 92#define CP_QUEUE_THRESHOLDS 0x8760 93#define ROQ_IB1_START(x) ((x) << 0) 94#define ROQ_IB2_START(x) ((x) << 8) 95#define CP_RB_BASE 0xC100 96#define CP_RB_CNTL 0xC104 97#define RB_BUFSZ(x) ((x) << 0) 98#define RB_BLKSZ(x) ((x) << 8) 99#define RB_NO_UPDATE (1 << 27) 100#define RB_RPTR_WR_ENA (1 << 31) 101#define BUF_SWAP_32BIT (2 << 16) 102#define CP_RB_RPTR 0x8700 103#define CP_RB_RPTR_ADDR 0xC10C 104#define RB_RPTR_SWAP(x) ((x) << 0) 105#define CP_RB_RPTR_ADDR_HI 0xC110 106#define CP_RB_RPTR_WR 0xC108 107#define CP_RB_WPTR 0xC114 108#define CP_RB_WPTR_ADDR 0xC118 109#define CP_RB_WPTR_ADDR_HI 0xC11C 110#define CP_RB_WPTR_DELAY 0x8704 111#define CP_SEM_WAIT_TIMER 0x85BC 112#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 113#define CP_DEBUG 0xC1FC 114 115 116#define GC_USER_SHADER_PIPE_CONFIG 0x8954 117#define INACTIVE_QD_PIPES(x) ((x) << 8) 118#define INACTIVE_QD_PIPES_MASK 0x0000FF00 119#define INACTIVE_SIMDS(x) ((x) << 16) 120#define INACTIVE_SIMDS_MASK 0x00FF0000 121 122#define GRBM_CNTL 0x8000 123#define GRBM_READ_TIMEOUT(x) ((x) << 0) 124#define GRBM_SOFT_RESET 0x8020 125#define SOFT_RESET_CP (1 << 0) 126#define SOFT_RESET_CB (1 << 1) 127#define SOFT_RESET_DB (1 << 3) 128#define SOFT_RESET_PA (1 << 5) 129#define SOFT_RESET_SC (1 << 6) 130#define SOFT_RESET_SPI (1 << 8) 131#define SOFT_RESET_SH (1 << 9) 132#define SOFT_RESET_SX (1 << 10) 133#define SOFT_RESET_TC (1 << 11) 134#define SOFT_RESET_TA (1 << 12) 135#define SOFT_RESET_VC (1 << 13) 136#define SOFT_RESET_VGT (1 << 14) 137 138#define GRBM_STATUS 0x8010 139#define CMDFIFO_AVAIL_MASK 0x0000000F 140#define SRBM_RQ_PENDING (1 << 5) 141#define CF_RQ_PENDING (1 << 7) 142#define PF_RQ_PENDING (1 << 8) 143#define GRBM_EE_BUSY (1 << 10) 144#define SX_CLEAN (1 << 11) 145#define DB_CLEAN (1 << 12) 146#define CB_CLEAN (1 << 13) 147#define TA_BUSY (1 << 14) 148#define VGT_BUSY_NO_DMA (1 << 16) 149#define VGT_BUSY (1 << 17) 150#define SX_BUSY (1 << 20) 151#define SH_BUSY (1 << 21) 152#define SPI_BUSY (1 << 22) 153#define SC_BUSY (1 << 24) 154#define PA_BUSY (1 << 25) 155#define DB_BUSY (1 << 26) 156#define CP_COHERENCY_BUSY (1 << 28) 157#define CP_BUSY (1 << 29) 158#define CB_BUSY (1 << 30) 159#define GUI_ACTIVE (1 << 31) 160#define GRBM_STATUS_SE0 0x8014 161#define GRBM_STATUS_SE1 0x8018 162#define SE_SX_CLEAN (1 << 0) 163#define SE_DB_CLEAN (1 << 1) 164#define SE_CB_CLEAN (1 << 2) 165#define SE_TA_BUSY (1 << 25) 166#define SE_SX_BUSY (1 << 26) 167#define SE_SPI_BUSY (1 << 27) 168#define SE_SH_BUSY (1 << 28) 169#define SE_SC_BUSY (1 << 29) 170#define SE_DB_BUSY (1 << 30) 171#define SE_CB_BUSY (1 << 31) 172/* evergreen */ 173#define CG_THERMAL_CTRL 0x72c 174#define TOFFSET_MASK 0x00003FE0 175#define TOFFSET_SHIFT 5 176#define CG_MULT_THERMAL_STATUS 0x740 177#define ASIC_T(x) ((x) << 16) 178#define ASIC_T_MASK 0x07FF0000 179#define ASIC_T_SHIFT 16 180#define CG_TS0_STATUS 0x760 181#define TS0_ADC_DOUT_MASK 0x000003FF 182#define TS0_ADC_DOUT_SHIFT 0 183/* APU */ 184#define CG_THERMAL_STATUS 0x678 185 186#define HDP_HOST_PATH_CNTL 0x2C00 187#define HDP_NONSURFACE_BASE 0x2C04 188#define HDP_NONSURFACE_INFO 0x2C08 189#define HDP_NONSURFACE_SIZE 0x2C0C 190#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 191#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 192#define HDP_TILING_CONFIG 0x2F3C 193 194#define MC_SHARED_CHMAP 0x2004 195#define NOOFCHAN_SHIFT 12 196#define NOOFCHAN_MASK 0x00003000 197#define MC_SHARED_CHREMAP 0x2008 198 199#define MC_ARB_RAMCFG 0x2760 200#define NOOFBANK_SHIFT 0 201#define NOOFBANK_MASK 0x00000003 202#define NOOFRANK_SHIFT 2 203#define NOOFRANK_MASK 0x00000004 204#define NOOFROWS_SHIFT 3 205#define NOOFROWS_MASK 0x00000038 206#define NOOFCOLS_SHIFT 6 207#define NOOFCOLS_MASK 0x000000C0 208#define CHANSIZE_SHIFT 8 209#define CHANSIZE_MASK 0x00000100 210#define BURSTLENGTH_SHIFT 9 211#define BURSTLENGTH_MASK 0x00000200 212#define CHANSIZE_OVERRIDE (1 << 11) 213#define FUS_MC_ARB_RAMCFG 0x2768 214#define MC_VM_AGP_TOP 0x2028 215#define MC_VM_AGP_BOT 0x202C 216#define MC_VM_AGP_BASE 0x2030 217#define MC_VM_FB_LOCATION 0x2024 218#define MC_FUS_VM_FB_OFFSET 0x2898 219#define MC_VM_MB_L1_TLB0_CNTL 0x2234 220#define MC_VM_MB_L1_TLB1_CNTL 0x2238 221#define MC_VM_MB_L1_TLB2_CNTL 0x223C 222#define MC_VM_MB_L1_TLB3_CNTL 0x2240 223#define ENABLE_L1_TLB (1 << 0) 224#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 225#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 226#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 227#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 228#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 229#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 230#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) 231#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) 232#define MC_VM_MD_L1_TLB0_CNTL 0x2654 233#define MC_VM_MD_L1_TLB1_CNTL 0x2658 234#define MC_VM_MD_L1_TLB2_CNTL 0x265C 235#define MC_VM_MD_L1_TLB3_CNTL 0x2698 236 237#define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C 238#define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660 239#define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664 240 241#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 242#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 243#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 244 245#define PA_CL_ENHANCE 0x8A14 246#define CLIP_VTX_REORDER_ENA (1 << 0) 247#define NUM_CLIP_SEQ(x) ((x) << 1) 248#define PA_SC_ENHANCE 0x8BF0 249#define PA_SC_AA_CONFIG 0x28C04 250#define MSAA_NUM_SAMPLES_SHIFT 0 251#define MSAA_NUM_SAMPLES_MASK 0x3 252#define PA_SC_CLIPRECT_RULE 0x2820C 253#define PA_SC_EDGERULE 0x28230 254#define PA_SC_FIFO_SIZE 0x8BCC 255#define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 256#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 257#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 258#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 259#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 260#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 261#define PA_SC_LINE_STIPPLE 0x28A0C 262#define PA_SU_LINE_STIPPLE_VALUE 0x8A60 263#define PA_SC_LINE_STIPPLE_STATE 0x8B10 264 265#define SCRATCH_REG0 0x8500 266#define SCRATCH_REG1 0x8504 267#define SCRATCH_REG2 0x8508 268#define SCRATCH_REG3 0x850C 269#define SCRATCH_REG4 0x8510 270#define SCRATCH_REG5 0x8514 271#define SCRATCH_REG6 0x8518 272#define SCRATCH_REG7 0x851C 273#define SCRATCH_UMSK 0x8540 274#define SCRATCH_ADDR 0x8544 275 276#define SMX_SAR_CTL0 0xA008 277#define SMX_DC_CTL0 0xA020 278#define USE_HASH_FUNCTION (1 << 0) 279#define NUMBER_OF_SETS(x) ((x) << 1) 280#define FLUSH_ALL_ON_EVENT (1 << 10) 281#define STALL_ON_EVENT (1 << 11) 282#define SMX_EVENT_CTL 0xA02C 283#define ES_FLUSH_CTL(x) ((x) << 0) 284#define GS_FLUSH_CTL(x) ((x) << 3) 285#define ACK_FLUSH_CTL(x) ((x) << 6) 286#define SYNC_FLUSH_CTL (1 << 8) 287 288#define SPI_CONFIG_CNTL 0x9100 289#define GPR_WRITE_PRIORITY(x) ((x) << 0) 290#define SPI_CONFIG_CNTL_1 0x913C 291#define VTX_DONE_DELAY(x) ((x) << 0) 292#define INTERP_ONE_PRIM_PER_ROW (1 << 4) 293#define SPI_INPUT_Z 0x286D8 294#define SPI_PS_IN_CONTROL_0 0x286CC 295#define NUM_INTERP(x) ((x)<<0) 296#define POSITION_ENA (1<<8) 297#define POSITION_CENTROID (1<<9) 298#define POSITION_ADDR(x) ((x)<<10) 299#define PARAM_GEN(x) ((x)<<15) 300#define PARAM_GEN_ADDR(x) ((x)<<19) 301#define BARYC_SAMPLE_CNTL(x) ((x)<<26) 302#define PERSP_GRADIENT_ENA (1<<28) 303#define LINEAR_GRADIENT_ENA (1<<29) 304#define POSITION_SAMPLE (1<<30) 305#define BARYC_AT_SAMPLE_ENA (1<<31) 306 307#define SQ_CONFIG 0x8C00 308#define VC_ENABLE (1 << 0) 309#define EXPORT_SRC_C (1 << 1) 310#define CS_PRIO(x) ((x) << 18) 311#define LS_PRIO(x) ((x) << 20) 312#define HS_PRIO(x) ((x) << 22) 313#define PS_PRIO(x) ((x) << 24) 314#define VS_PRIO(x) ((x) << 26) 315#define GS_PRIO(x) ((x) << 28) 316#define ES_PRIO(x) ((x) << 30) 317#define SQ_GPR_RESOURCE_MGMT_1 0x8C04 318#define NUM_PS_GPRS(x) ((x) << 0) 319#define NUM_VS_GPRS(x) ((x) << 16) 320#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 321#define SQ_GPR_RESOURCE_MGMT_2 0x8C08 322#define NUM_GS_GPRS(x) ((x) << 0) 323#define NUM_ES_GPRS(x) ((x) << 16) 324#define SQ_GPR_RESOURCE_MGMT_3 0x8C0C 325#define NUM_HS_GPRS(x) ((x) << 0) 326#define NUM_LS_GPRS(x) ((x) << 16) 327#define SQ_GLOBAL_GPR_RESOURCE_MGMT_1 0x8C10 328#define SQ_GLOBAL_GPR_RESOURCE_MGMT_2 0x8C14 329#define SQ_THREAD_RESOURCE_MGMT 0x8C18 330#define NUM_PS_THREADS(x) ((x) << 0) 331#define NUM_VS_THREADS(x) ((x) << 8) 332#define NUM_GS_THREADS(x) ((x) << 16) 333#define NUM_ES_THREADS(x) ((x) << 24) 334#define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C 335#define NUM_HS_THREADS(x) ((x) << 0) 336#define NUM_LS_THREADS(x) ((x) << 8) 337#define SQ_STACK_RESOURCE_MGMT_1 0x8C20 338#define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 339#define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 340#define SQ_STACK_RESOURCE_MGMT_2 0x8C24 341#define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 342#define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 343#define SQ_STACK_RESOURCE_MGMT_3 0x8C28 344#define NUM_HS_STACK_ENTRIES(x) ((x) << 0) 345#define NUM_LS_STACK_ENTRIES(x) ((x) << 16) 346#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C 347#define SQ_DYN_GPR_SIMD_LOCK_EN 0x8D94 348#define SQ_STATIC_THREAD_MGMT_1 0x8E20 349#define SQ_STATIC_THREAD_MGMT_2 0x8E24 350#define SQ_STATIC_THREAD_MGMT_3 0x8E28 351#define SQ_LDS_RESOURCE_MGMT 0x8E2C 352 353#define SQ_MS_FIFO_SIZES 0x8CF0 354#define CACHE_FIFO_SIZE(x) ((x) << 0) 355#define FETCH_FIFO_HIWATER(x) ((x) << 8) 356#define DONE_FIFO_HIWATER(x) ((x) << 16) 357#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 358 359#define SX_DEBUG_1 0x9058 360#define ENABLE_NEW_SMX_ADDRESS (1 << 16) 361#define SX_EXPORT_BUFFER_SIZES 0x900C 362#define COLOR_BUFFER_SIZE(x) ((x) << 0) 363#define POSITION_BUFFER_SIZE(x) ((x) << 8) 364#define SMX_BUFFER_SIZE(x) ((x) << 16) 365#define SX_MEMORY_EXPORT_BASE 0x9010 366#define SX_MISC 0x28350 367 368#define CB_PERF_CTR0_SEL_0 0x9A20 369#define CB_PERF_CTR0_SEL_1 0x9A24 370#define CB_PERF_CTR1_SEL_0 0x9A28 371#define CB_PERF_CTR1_SEL_1 0x9A2C 372#define CB_PERF_CTR2_SEL_0 0x9A30 373#define CB_PERF_CTR2_SEL_1 0x9A34 374#define CB_PERF_CTR3_SEL_0 0x9A38 375#define CB_PERF_CTR3_SEL_1 0x9A3C 376 377#define TA_CNTL_AUX 0x9508 378#define DISABLE_CUBE_WRAP (1 << 0) 379#define DISABLE_CUBE_ANISO (1 << 1) 380#define SYNC_GRADIENT (1 << 24) 381#define SYNC_WALKER (1 << 25) 382#define SYNC_ALIGNER (1 << 26) 383 384#define TCP_CHAN_STEER_LO 0x960c 385#define TCP_CHAN_STEER_HI 0x9610 386 387#define VGT_CACHE_INVALIDATION 0x88C4 388#define CACHE_INVALIDATION(x) ((x) << 0) 389#define VC_ONLY 0 390#define TC_ONLY 1 391#define VC_AND_TC 2 392#define AUTO_INVLD_EN(x) ((x) << 6) 393#define NO_AUTO 0 394#define ES_AUTO 1 395#define GS_AUTO 2 396#define ES_AND_GS_AUTO 3 397#define VGT_GS_VERTEX_REUSE 0x88D4 398#define VGT_NUM_INSTANCES 0x8974 399#define VGT_OUT_DEALLOC_CNTL 0x28C5C 400#define DEALLOC_DIST_MASK 0x0000007F 401#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 402#define VTX_REUSE_DEPTH_MASK 0x000000FF 403 404#define VM_CONTEXT0_CNTL 0x1410 405#define ENABLE_CONTEXT (1 << 0) 406#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 407#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 408#define VM_CONTEXT1_CNTL 0x1414 409#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 410#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 411#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 412#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 413#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 414#define REQUEST_TYPE(x) (((x) & 0xf) << 0) 415#define RESPONSE_TYPE_MASK 0x000000F0 416#define RESPONSE_TYPE_SHIFT 4 417#define VM_L2_CNTL 0x1400 418#define ENABLE_L2_CACHE (1 << 0) 419#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 420#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 421#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 422#define VM_L2_CNTL2 0x1404 423#define INVALIDATE_ALL_L1_TLBS (1 << 0) 424#define INVALIDATE_L2_CACHE (1 << 1) 425#define VM_L2_CNTL3 0x1408 426#define BANK_SELECT(x) ((x) << 0) 427#define CACHE_UPDATE_MODE(x) ((x) << 6) 428#define VM_L2_STATUS 0x140C 429#define L2_BUSY (1 << 0) 430 431#define WAIT_UNTIL 0x8040 432 433#define SRBM_STATUS 0x0E50 434#define SRBM_SOFT_RESET 0x0E60 435#define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6 436#define SOFT_RESET_BIF (1 << 1) 437#define SOFT_RESET_CG (1 << 2) 438#define SOFT_RESET_DC (1 << 5) 439#define SOFT_RESET_GRBM (1 << 8) 440#define SOFT_RESET_HDP (1 << 9) 441#define SOFT_RESET_IH (1 << 10) 442#define SOFT_RESET_MC (1 << 11) 443#define SOFT_RESET_RLC (1 << 13) 444#define SOFT_RESET_ROM (1 << 14) 445#define SOFT_RESET_SEM (1 << 15) 446#define SOFT_RESET_VMC (1 << 17) 447#define SOFT_RESET_TST (1 << 21) 448#define SOFT_RESET_REGBB (1 << 22) 449#define SOFT_RESET_ORB (1 << 23) 450 451/* display watermarks */ 452#define DC_LB_MEMORY_SPLIT 0x6b0c 453#define PRIORITY_A_CNT 0x6b18 454#define PRIORITY_MARK_MASK 0x7fff 455#define PRIORITY_OFF (1 << 16) 456#define PRIORITY_ALWAYS_ON (1 << 20) 457#define PRIORITY_B_CNT 0x6b1c 458#define PIPE0_ARBITRATION_CONTROL3 0x0bf0 459# define LATENCY_WATERMARK_MASK(x) ((x) << 16) 460#define PIPE0_LATENCY_CONTROL 0x0bf4 461# define LATENCY_LOW_WATERMARK(x) ((x) << 0) 462# define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 463 464#define IH_RB_CNTL 0x3e00 465# define IH_RB_ENABLE (1 << 0) 466# define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 467# define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 468# define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 469# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 470# define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 471# define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 472#define IH_RB_BASE 0x3e04 473#define IH_RB_RPTR 0x3e08 474#define IH_RB_WPTR 0x3e0c 475# define RB_OVERFLOW (1 << 0) 476# define WPTR_OFFSET_MASK 0x3fffc 477#define IH_RB_WPTR_ADDR_HI 0x3e10 478#define IH_RB_WPTR_ADDR_LO 0x3e14 479#define IH_CNTL 0x3e18 480# define ENABLE_INTR (1 << 0) 481# define IH_MC_SWAP(x) ((x) << 1) 482# define IH_MC_SWAP_NONE 0 483# define IH_MC_SWAP_16BIT 1 484# define IH_MC_SWAP_32BIT 2 485# define IH_MC_SWAP_64BIT 3 486# define RPTR_REARM (1 << 4) 487# define MC_WRREQ_CREDIT(x) ((x) << 15) 488# define MC_WR_CLEAN_CNT(x) ((x) << 20) 489 490#define CP_INT_CNTL 0xc124 491# define CNTX_BUSY_INT_ENABLE (1 << 19) 492# define CNTX_EMPTY_INT_ENABLE (1 << 20) 493# define SCRATCH_INT_ENABLE (1 << 25) 494# define TIME_STAMP_INT_ENABLE (1 << 26) 495# define IB2_INT_ENABLE (1 << 29) 496# define IB1_INT_ENABLE (1 << 30) 497# define RB_INT_ENABLE (1 << 31) 498#define CP_INT_STATUS 0xc128 499# define SCRATCH_INT_STAT (1 << 25) 500# define TIME_STAMP_INT_STAT (1 << 26) 501# define IB2_INT_STAT (1 << 29) 502# define IB1_INT_STAT (1 << 30) 503# define RB_INT_STAT (1 << 31) 504 505#define GRBM_INT_CNTL 0x8060 506# define RDERR_INT_ENABLE (1 << 0) 507# define GUI_IDLE_INT_ENABLE (1 << 19) 508 509/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ 510#define CRTC_STATUS_FRAME_COUNT 0x6e98 511 512/* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ 513#define VLINE_STATUS 0x6bb8 514# define VLINE_OCCURRED (1 << 0) 515# define VLINE_ACK (1 << 4) 516# define VLINE_STAT (1 << 12) 517# define VLINE_INTERRUPT (1 << 16) 518# define VLINE_INTERRUPT_TYPE (1 << 17) 519/* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ 520#define VBLANK_STATUS 0x6bbc 521# define VBLANK_OCCURRED (1 << 0) 522# define VBLANK_ACK (1 << 4) 523# define VBLANK_STAT (1 << 12) 524# define VBLANK_INTERRUPT (1 << 16) 525# define VBLANK_INTERRUPT_TYPE (1 << 17) 526 527/* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ 528#define INT_MASK 0x6b40 529# define VBLANK_INT_MASK (1 << 0) 530# define VLINE_INT_MASK (1 << 4) 531 532#define DISP_INTERRUPT_STATUS 0x60f4 533# define LB_D1_VLINE_INTERRUPT (1 << 2) 534# define LB_D1_VBLANK_INTERRUPT (1 << 3) 535# define DC_HPD1_INTERRUPT (1 << 17) 536# define DC_HPD1_RX_INTERRUPT (1 << 18) 537# define DACA_AUTODETECT_INTERRUPT (1 << 22) 538# define DACB_AUTODETECT_INTERRUPT (1 << 23) 539# define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 540# define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 541#define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 542# define LB_D2_VLINE_INTERRUPT (1 << 2) 543# define LB_D2_VBLANK_INTERRUPT (1 << 3) 544# define DC_HPD2_INTERRUPT (1 << 17) 545# define DC_HPD2_RX_INTERRUPT (1 << 18) 546# define DISP_TIMER_INTERRUPT (1 << 24) 547#define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 548# define LB_D3_VLINE_INTERRUPT (1 << 2) 549# define LB_D3_VBLANK_INTERRUPT (1 << 3) 550# define DC_HPD3_INTERRUPT (1 << 17) 551# define DC_HPD3_RX_INTERRUPT (1 << 18) 552#define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 553# define LB_D4_VLINE_INTERRUPT (1 << 2) 554# define LB_D4_VBLANK_INTERRUPT (1 << 3) 555# define DC_HPD4_INTERRUPT (1 << 17) 556# define DC_HPD4_RX_INTERRUPT (1 << 18) 557#define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 558# define LB_D5_VLINE_INTERRUPT (1 << 2) 559# define LB_D5_VBLANK_INTERRUPT (1 << 3) 560# define DC_HPD5_INTERRUPT (1 << 17) 561# define DC_HPD5_RX_INTERRUPT (1 << 18) 562#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 563# define LB_D6_VLINE_INTERRUPT (1 << 2) 564# define LB_D6_VBLANK_INTERRUPT (1 << 3) 565# define DC_HPD6_INTERRUPT (1 << 17) 566# define DC_HPD6_RX_INTERRUPT (1 << 18) 567 568/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 569#define GRPH_INT_STATUS 0x6858 570# define GRPH_PFLIP_INT_OCCURRED (1 << 0) 571# define GRPH_PFLIP_INT_CLEAR (1 << 8) 572/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 573#define GRPH_INT_CONTROL 0x685c 574# define GRPH_PFLIP_INT_MASK (1 << 0) 575# define GRPH_PFLIP_INT_TYPE (1 << 8) 576 577#define DACA_AUTODETECT_INT_CONTROL 0x66c8 578#define DACB_AUTODETECT_INT_CONTROL 0x67c8 579 580#define DC_HPD1_INT_STATUS 0x601c 581#define DC_HPD2_INT_STATUS 0x6028 582#define DC_HPD3_INT_STATUS 0x6034 583#define DC_HPD4_INT_STATUS 0x6040 584#define DC_HPD5_INT_STATUS 0x604c 585#define DC_HPD6_INT_STATUS 0x6058 586# define DC_HPDx_INT_STATUS (1 << 0) 587# define DC_HPDx_SENSE (1 << 1) 588# define DC_HPDx_RX_INT_STATUS (1 << 8) 589 590#define DC_HPD1_INT_CONTROL 0x6020 591#define DC_HPD2_INT_CONTROL 0x602c 592#define DC_HPD3_INT_CONTROL 0x6038 593#define DC_HPD4_INT_CONTROL 0x6044 594#define DC_HPD5_INT_CONTROL 0x6050 595#define DC_HPD6_INT_CONTROL 0x605c 596# define DC_HPDx_INT_ACK (1 << 0) 597# define DC_HPDx_INT_POLARITY (1 << 8) 598# define DC_HPDx_INT_EN (1 << 16) 599# define DC_HPDx_RX_INT_ACK (1 << 20) 600# define DC_HPDx_RX_INT_EN (1 << 24) 601 602#define DC_HPD1_CONTROL 0x6024 603#define DC_HPD2_CONTROL 0x6030 604#define DC_HPD3_CONTROL 0x603c 605#define DC_HPD4_CONTROL 0x6048 606#define DC_HPD5_CONTROL 0x6054 607#define DC_HPD6_CONTROL 0x6060 608# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 609# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 610# define DC_HPDx_EN (1 << 28) 611 612/* PCIE link stuff */ 613#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 614#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 615# define LC_LINK_WIDTH_SHIFT 0 616# define LC_LINK_WIDTH_MASK 0x7 617# define LC_LINK_WIDTH_X0 0 618# define LC_LINK_WIDTH_X1 1 619# define LC_LINK_WIDTH_X2 2 620# define LC_LINK_WIDTH_X4 3 621# define LC_LINK_WIDTH_X8 4 622# define LC_LINK_WIDTH_X16 6 623# define LC_LINK_WIDTH_RD_SHIFT 4 624# define LC_LINK_WIDTH_RD_MASK 0x70 625# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 626# define LC_RECONFIG_NOW (1 << 8) 627# define LC_RENEGOTIATION_SUPPORT (1 << 9) 628# define LC_RENEGOTIATE_EN (1 << 10) 629# define LC_SHORT_RECONFIG_EN (1 << 11) 630# define LC_UPCONFIGURE_SUPPORT (1 << 12) 631# define LC_UPCONFIGURE_DIS (1 << 13) 632#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 633# define LC_GEN2_EN_STRAP (1 << 0) 634# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 635# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 636# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 637# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 638# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 639# define LC_CURRENT_DATA_RATE (1 << 11) 640# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 641# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 642# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 643# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 644#define MM_CFGREGS_CNTL 0x544c 645# define MM_WR_TO_CFG_EN (1 << 3) 646#define LINK_CNTL2 0x88 /* F0 */ 647# define TARGET_LINK_SPEED_MASK (0xf << 0) 648# define SELECTABLE_DEEMPHASIS (1 << 6) 649 650/* 651 * PM4 652 */ 653#define PACKET_TYPE0 0 654#define PACKET_TYPE1 1 655#define PACKET_TYPE2 2 656#define PACKET_TYPE3 3 657 658#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 659#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 660#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 661#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 662#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 663 (((reg) >> 2) & 0xFFFF) | \ 664 ((n) & 0x3FFF) << 16) 665#define CP_PACKET2 0x80000000 666#define PACKET2_PAD_SHIFT 0 667#define PACKET2_PAD_MASK (0x3fffffff << 0) 668 669#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 670 671#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 672 (((op) & 0xFF) << 8) | \ 673 ((n) & 0x3FFF) << 16) 674 675/* Packet 3 types */ 676#define PACKET3_NOP 0x10 677#define PACKET3_SET_BASE 0x11 678#define PACKET3_CLEAR_STATE 0x12 679#define PACKET3_INDEX_BUFFER_SIZE 0x13 680#define PACKET3_DISPATCH_DIRECT 0x15 681#define PACKET3_DISPATCH_INDIRECT 0x16 682#define PACKET3_INDIRECT_BUFFER_END 0x17 683#define PACKET3_MODE_CONTROL 0x18 684#define PACKET3_SET_PREDICATION 0x20 685#define PACKET3_REG_RMW 0x21 686#define PACKET3_COND_EXEC 0x22 687#define PACKET3_PRED_EXEC 0x23 688#define PACKET3_DRAW_INDIRECT 0x24 689#define PACKET3_DRAW_INDEX_INDIRECT 0x25 690#define PACKET3_INDEX_BASE 0x26 691#define PACKET3_DRAW_INDEX_2 0x27 692#define PACKET3_CONTEXT_CONTROL 0x28 693#define PACKET3_DRAW_INDEX_OFFSET 0x29 694#define PACKET3_INDEX_TYPE 0x2A 695#define PACKET3_DRAW_INDEX 0x2B 696#define PACKET3_DRAW_INDEX_AUTO 0x2D 697#define PACKET3_DRAW_INDEX_IMMD 0x2E 698#define PACKET3_NUM_INSTANCES 0x2F 699#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 700#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 701#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 702#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 703#define PACKET3_MEM_SEMAPHORE 0x39 704#define PACKET3_MPEG_INDEX 0x3A 705#define PACKET3_COPY_DW 0x3B 706#define PACKET3_WAIT_REG_MEM 0x3C 707#define PACKET3_MEM_WRITE 0x3D 708#define PACKET3_INDIRECT_BUFFER 0x32 709#define PACKET3_SURFACE_SYNC 0x43 710# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 711# define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 712# define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 713# define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 714# define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 715# define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 716# define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 717# define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 718# define PACKET3_DB_DEST_BASE_ENA (1 << 14) 719# define PACKET3_CB8_DEST_BASE_ENA (1 << 15) 720# define PACKET3_CB9_DEST_BASE_ENA (1 << 16) 721# define PACKET3_CB10_DEST_BASE_ENA (1 << 17) 722# define PACKET3_CB11_DEST_BASE_ENA (1 << 18) 723# define PACKET3_FULL_CACHE_ENA (1 << 20) 724# define PACKET3_TC_ACTION_ENA (1 << 23) 725# define PACKET3_VC_ACTION_ENA (1 << 24) 726# define PACKET3_CB_ACTION_ENA (1 << 25) 727# define PACKET3_DB_ACTION_ENA (1 << 26) 728# define PACKET3_SH_ACTION_ENA (1 << 27) 729# define PACKET3_SX_ACTION_ENA (1 << 28) 730#define PACKET3_ME_INITIALIZE 0x44 731#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 732#define PACKET3_COND_WRITE 0x45 733#define PACKET3_EVENT_WRITE 0x46 734#define PACKET3_EVENT_WRITE_EOP 0x47 735#define PACKET3_EVENT_WRITE_EOS 0x48 736#define PACKET3_PREAMBLE_CNTL 0x4A 737# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 738# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 739#define PACKET3_RB_OFFSET 0x4B 740#define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C 741#define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D 742#define PACKET3_ALU_PS_CONST_UPDATE 0x4E 743#define PACKET3_ALU_VS_CONST_UPDATE 0x4F 744#define PACKET3_ONE_REG_WRITE 0x57 745#define PACKET3_SET_CONFIG_REG 0x68 746#define PACKET3_SET_CONFIG_REG_START 0x00008000 747#define PACKET3_SET_CONFIG_REG_END 0x0000ac00 748#define PACKET3_SET_CONTEXT_REG 0x69 749#define PACKET3_SET_CONTEXT_REG_START 0x00028000 750#define PACKET3_SET_CONTEXT_REG_END 0x00029000 751#define PACKET3_SET_ALU_CONST 0x6A 752/* alu const buffers only; no reg file */ 753#define PACKET3_SET_BOOL_CONST 0x6B 754#define PACKET3_SET_BOOL_CONST_START 0x0003a500 755#define PACKET3_SET_BOOL_CONST_END 0x0003a518 756#define PACKET3_SET_LOOP_CONST 0x6C 757#define PACKET3_SET_LOOP_CONST_START 0x0003a200 758#define PACKET3_SET_LOOP_CONST_END 0x0003a500 759#define PACKET3_SET_RESOURCE 0x6D 760#define PACKET3_SET_RESOURCE_START 0x00030000 761#define PACKET3_SET_RESOURCE_END 0x00038000 762#define PACKET3_SET_SAMPLER 0x6E 763#define PACKET3_SET_SAMPLER_START 0x0003c000 764#define PACKET3_SET_SAMPLER_END 0x0003c600 765#define PACKET3_SET_CTL_CONST 0x6F 766#define PACKET3_SET_CTL_CONST_START 0x0003cff0 767#define PACKET3_SET_CTL_CONST_END 0x0003ff0c 768#define PACKET3_SET_RESOURCE_OFFSET 0x70 769#define PACKET3_SET_ALU_CONST_VS 0x71 770#define PACKET3_SET_ALU_CONST_DI 0x72 771#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 772#define PACKET3_SET_RESOURCE_INDIRECT 0x74 773#define PACKET3_SET_APPEND_CNT 0x75 774 775#define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c 776#define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30) 777#define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3) 778#define SQ_TEX_VTX_INVALID_TEXTURE 0x0 779#define SQ_TEX_VTX_INVALID_BUFFER 0x1 780#define SQ_TEX_VTX_VALID_TEXTURE 0x2 781#define SQ_TEX_VTX_VALID_BUFFER 0x3 782 783#define VGT_VTX_VECT_EJECT_REG 0x88b0 784 785#define SQ_CONST_MEM_BASE 0x8df8 786 787#define SQ_ESGS_RING_BASE 0x8c40 788#define SQ_ESGS_RING_SIZE 0x8c44 789#define SQ_GSVS_RING_BASE 0x8c48 790#define SQ_GSVS_RING_SIZE 0x8c4c 791#define SQ_ESTMP_RING_BASE 0x8c50 792#define SQ_ESTMP_RING_SIZE 0x8c54 793#define SQ_GSTMP_RING_BASE 0x8c58 794#define SQ_GSTMP_RING_SIZE 0x8c5c 795#define SQ_VSTMP_RING_BASE 0x8c60 796#define SQ_VSTMP_RING_SIZE 0x8c64 797#define SQ_PSTMP_RING_BASE 0x8c68 798#define SQ_PSTMP_RING_SIZE 0x8c6c 799#define SQ_LSTMP_RING_BASE 0x8e10 800#define SQ_LSTMP_RING_SIZE 0x8e14 801#define SQ_HSTMP_RING_BASE 0x8e18 802#define SQ_HSTMP_RING_SIZE 0x8e1c 803#define VGT_TF_RING_SIZE 0x8988 804 805#define SQ_ESGS_RING_ITEMSIZE 0x28900 806#define SQ_GSVS_RING_ITEMSIZE 0x28904 807#define SQ_ESTMP_RING_ITEMSIZE 0x28908 808#define SQ_GSTMP_RING_ITEMSIZE 0x2890c 809#define SQ_VSTMP_RING_ITEMSIZE 0x28910 810#define SQ_PSTMP_RING_ITEMSIZE 0x28914 811#define SQ_LSTMP_RING_ITEMSIZE 0x28830 812#define SQ_HSTMP_RING_ITEMSIZE 0x28834 813 814#define SQ_GS_VERT_ITEMSIZE 0x2891c 815#define SQ_GS_VERT_ITEMSIZE_1 0x28920 816#define SQ_GS_VERT_ITEMSIZE_2 0x28924 817#define SQ_GS_VERT_ITEMSIZE_3 0x28928 818#define SQ_GSVS_RING_OFFSET_1 0x2892c 819#define SQ_GSVS_RING_OFFSET_2 0x28930 820#define SQ_GSVS_RING_OFFSET_3 0x28934 821 822#define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140 823#define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80 824 825#define SQ_ALU_CONST_CACHE_PS_0 0x28940 826#define SQ_ALU_CONST_CACHE_PS_1 0x28944 827#define SQ_ALU_CONST_CACHE_PS_2 0x28948 828#define SQ_ALU_CONST_CACHE_PS_3 0x2894c 829#define SQ_ALU_CONST_CACHE_PS_4 0x28950 830#define SQ_ALU_CONST_CACHE_PS_5 0x28954 831#define SQ_ALU_CONST_CACHE_PS_6 0x28958 832#define SQ_ALU_CONST_CACHE_PS_7 0x2895c 833#define SQ_ALU_CONST_CACHE_PS_8 0x28960 834#define SQ_ALU_CONST_CACHE_PS_9 0x28964 835#define SQ_ALU_CONST_CACHE_PS_10 0x28968 836#define SQ_ALU_CONST_CACHE_PS_11 0x2896c 837#define SQ_ALU_CONST_CACHE_PS_12 0x28970 838#define SQ_ALU_CONST_CACHE_PS_13 0x28974 839#define SQ_ALU_CONST_CACHE_PS_14 0x28978 840#define SQ_ALU_CONST_CACHE_PS_15 0x2897c 841#define SQ_ALU_CONST_CACHE_VS_0 0x28980 842#define SQ_ALU_CONST_CACHE_VS_1 0x28984 843#define SQ_ALU_CONST_CACHE_VS_2 0x28988 844#define SQ_ALU_CONST_CACHE_VS_3 0x2898c 845#define SQ_ALU_CONST_CACHE_VS_4 0x28990 846#define SQ_ALU_CONST_CACHE_VS_5 0x28994 847#define SQ_ALU_CONST_CACHE_VS_6 0x28998 848#define SQ_ALU_CONST_CACHE_VS_7 0x2899c 849#define SQ_ALU_CONST_CACHE_VS_8 0x289a0 850#define SQ_ALU_CONST_CACHE_VS_9 0x289a4 851#define SQ_ALU_CONST_CACHE_VS_10 0x289a8 852#define SQ_ALU_CONST_CACHE_VS_11 0x289ac 853#define SQ_ALU_CONST_CACHE_VS_12 0x289b0 854#define SQ_ALU_CONST_CACHE_VS_13 0x289b4 855#define SQ_ALU_CONST_CACHE_VS_14 0x289b8 856#define SQ_ALU_CONST_CACHE_VS_15 0x289bc 857#define SQ_ALU_CONST_CACHE_GS_0 0x289c0 858#define SQ_ALU_CONST_CACHE_GS_1 0x289c4 859#define SQ_ALU_CONST_CACHE_GS_2 0x289c8 860#define SQ_ALU_CONST_CACHE_GS_3 0x289cc 861#define SQ_ALU_CONST_CACHE_GS_4 0x289d0 862#define SQ_ALU_CONST_CACHE_GS_5 0x289d4 863#define SQ_ALU_CONST_CACHE_GS_6 0x289d8 864#define SQ_ALU_CONST_CACHE_GS_7 0x289dc 865#define SQ_ALU_CONST_CACHE_GS_8 0x289e0 866#define SQ_ALU_CONST_CACHE_GS_9 0x289e4 867#define SQ_ALU_CONST_CACHE_GS_10 0x289e8 868#define SQ_ALU_CONST_CACHE_GS_11 0x289ec 869#define SQ_ALU_CONST_CACHE_GS_12 0x289f0 870#define SQ_ALU_CONST_CACHE_GS_13 0x289f4 871#define SQ_ALU_CONST_CACHE_GS_14 0x289f8 872#define SQ_ALU_CONST_CACHE_GS_15 0x289fc 873#define SQ_ALU_CONST_CACHE_HS_0 0x28f00 874#define SQ_ALU_CONST_CACHE_HS_1 0x28f04 875#define SQ_ALU_CONST_CACHE_HS_2 0x28f08 876#define SQ_ALU_CONST_CACHE_HS_3 0x28f0c 877#define SQ_ALU_CONST_CACHE_HS_4 0x28f10 878#define SQ_ALU_CONST_CACHE_HS_5 0x28f14 879#define SQ_ALU_CONST_CACHE_HS_6 0x28f18 880#define SQ_ALU_CONST_CACHE_HS_7 0x28f1c 881#define SQ_ALU_CONST_CACHE_HS_8 0x28f20 882#define SQ_ALU_CONST_CACHE_HS_9 0x28f24 883#define SQ_ALU_CONST_CACHE_HS_10 0x28f28 884#define SQ_ALU_CONST_CACHE_HS_11 0x28f2c 885#define SQ_ALU_CONST_CACHE_HS_12 0x28f30 886#define SQ_ALU_CONST_CACHE_HS_13 0x28f34 887#define SQ_ALU_CONST_CACHE_HS_14 0x28f38 888#define SQ_ALU_CONST_CACHE_HS_15 0x28f3c 889#define SQ_ALU_CONST_CACHE_LS_0 0x28f40 890#define SQ_ALU_CONST_CACHE_LS_1 0x28f44 891#define SQ_ALU_CONST_CACHE_LS_2 0x28f48 892#define SQ_ALU_CONST_CACHE_LS_3 0x28f4c 893#define SQ_ALU_CONST_CACHE_LS_4 0x28f50 894#define SQ_ALU_CONST_CACHE_LS_5 0x28f54 895#define SQ_ALU_CONST_CACHE_LS_6 0x28f58 896#define SQ_ALU_CONST_CACHE_LS_7 0x28f5c 897#define SQ_ALU_CONST_CACHE_LS_8 0x28f60 898#define SQ_ALU_CONST_CACHE_LS_9 0x28f64 899#define SQ_ALU_CONST_CACHE_LS_10 0x28f68 900#define SQ_ALU_CONST_CACHE_LS_11 0x28f6c 901#define SQ_ALU_CONST_CACHE_LS_12 0x28f70 902#define SQ_ALU_CONST_CACHE_LS_13 0x28f74 903#define SQ_ALU_CONST_CACHE_LS_14 0x28f78 904#define SQ_ALU_CONST_CACHE_LS_15 0x28f7c 905 906#define PA_SC_SCREEN_SCISSOR_TL 0x28030 907#define PA_SC_GENERIC_SCISSOR_TL 0x28240 908#define PA_SC_WINDOW_SCISSOR_TL 0x28204 909 910#define VGT_PRIMITIVE_TYPE 0x8958 911#define VGT_INDEX_TYPE 0x895C 912 913#define VGT_NUM_INDICES 0x8970 914 915#define VGT_COMPUTE_DIM_X 0x8990 916#define VGT_COMPUTE_DIM_Y 0x8994 917#define VGT_COMPUTE_DIM_Z 0x8998 918#define VGT_COMPUTE_START_X 0x899C 919#define VGT_COMPUTE_START_Y 0x89A0 920#define VGT_COMPUTE_START_Z 0x89A4 921#define VGT_COMPUTE_INDEX 0x89A8 922#define VGT_COMPUTE_THREAD_GROUP_SIZE 0x89AC 923#define VGT_HS_OFFCHIP_PARAM 0x89B0 924 925#define DB_DEBUG 0x9830 926#define DB_DEBUG2 0x9834 927#define DB_DEBUG3 0x9838 928#define DB_DEBUG4 0x983C 929#define DB_WATERMARKS 0x9854 930#define DB_DEPTH_CONTROL 0x28800 931#define R_028800_DB_DEPTH_CONTROL 0x028800 932#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) 933#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) 934#define C_028800_STENCIL_ENABLE 0xFFFFFFFE 935#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) 936#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) 937#define C_028800_Z_ENABLE 0xFFFFFFFD 938#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) 939#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) 940#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB 941#define S_028800_ZFUNC(x) (((x) & 0x7) << 4) 942#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) 943#define C_028800_ZFUNC 0xFFFFFF8F 944#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) 945#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) 946#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F 947#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) 948#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) 949#define C_028800_STENCILFUNC 0xFFFFF8FF 950#define V_028800_STENCILFUNC_NEVER 0x00000000 951#define V_028800_STENCILFUNC_LESS 0x00000001 952#define V_028800_STENCILFUNC_EQUAL 0x00000002 953#define V_028800_STENCILFUNC_LEQUAL 0x00000003 954#define V_028800_STENCILFUNC_GREATER 0x00000004 955#define V_028800_STENCILFUNC_NOTEQUAL 0x00000005 956#define V_028800_STENCILFUNC_GEQUAL 0x00000006 957#define V_028800_STENCILFUNC_ALWAYS 0x00000007 958#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) 959#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) 960#define C_028800_STENCILFAIL 0xFFFFC7FF 961#define V_028800_STENCIL_KEEP 0x00000000 962#define V_028800_STENCIL_ZERO 0x00000001 963#define V_028800_STENCIL_REPLACE 0x00000002 964#define V_028800_STENCIL_INCR 0x00000003 965#define V_028800_STENCIL_DECR 0x00000004 966#define V_028800_STENCIL_INVERT 0x00000005 967#define V_028800_STENCIL_INCR_WRAP 0x00000006 968#define V_028800_STENCIL_DECR_WRAP 0x00000007 969#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) 970#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) 971#define C_028800_STENCILZPASS 0xFFFE3FFF 972#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) 973#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) 974#define C_028800_STENCILZFAIL 0xFFF1FFFF 975#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) 976#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) 977#define C_028800_STENCILFUNC_BF 0xFF8FFFFF 978#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) 979#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) 980#define C_028800_STENCILFAIL_BF 0xFC7FFFFF 981#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) 982#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) 983#define C_028800_STENCILZPASS_BF 0xE3FFFFFF 984#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) 985#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) 986#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF 987#define DB_DEPTH_VIEW 0x28008 988#define R_028008_DB_DEPTH_VIEW 0x00028008 989#define S_028008_SLICE_START(x) (((x) & 0x7FF) << 0) 990#define G_028008_SLICE_START(x) (((x) >> 0) & 0x7FF) 991#define C_028008_SLICE_START 0xFFFFF800 992#define S_028008_SLICE_MAX(x) (((x) & 0x7FF) << 13) 993#define G_028008_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 994#define C_028008_SLICE_MAX 0xFF001FFF 995#define DB_HTILE_DATA_BASE 0x28014 996#define DB_HTILE_SURFACE 0x28abc 997#define S_028ABC_HTILE_WIDTH(x) (((x) & 0x1) << 0) 998#define G_028ABC_HTILE_WIDTH(x) (((x) >> 0) & 0x1) 999#define C_028ABC_HTILE_WIDTH 0xFFFFFFFE 1000#define S_028ABC_HTILE_HEIGHT(x) (((x) & 0x1) << 1) 1001#define G_028ABC_HTILE_HEIGHT(x) (((x) >> 1) & 0x1) 1002#define C_028ABC_HTILE_HEIGHT 0xFFFFFFFD 1003#define G_028ABC_LINEAR(x) (((x) >> 2) & 0x1) 1004#define DB_Z_INFO 0x28040 1005# define Z_ARRAY_MODE(x) ((x) << 4) 1006# define DB_TILE_SPLIT(x) (((x) & 0x7) << 8) 1007# define DB_NUM_BANKS(x) (((x) & 0x3) << 12) 1008# define DB_BANK_WIDTH(x) (((x) & 0x3) << 16) 1009# define DB_BANK_HEIGHT(x) (((x) & 0x3) << 20) 1010# define DB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24) 1011#define R_028040_DB_Z_INFO 0x028040 1012#define S_028040_FORMAT(x) (((x) & 0x3) << 0) 1013#define G_028040_FORMAT(x) (((x) >> 0) & 0x3) 1014#define C_028040_FORMAT 0xFFFFFFFC 1015#define V_028040_Z_INVALID 0x00000000 1016#define V_028040_Z_16 0x00000001 1017#define V_028040_Z_24 0x00000002 1018#define V_028040_Z_32_FLOAT 0x00000003 1019#define S_028040_ARRAY_MODE(x) (((x) & 0xF) << 4) 1020#define G_028040_ARRAY_MODE(x) (((x) >> 4) & 0xF) 1021#define C_028040_ARRAY_MODE 0xFFFFFF0F 1022#define S_028040_READ_SIZE(x) (((x) & 0x1) << 28) 1023#define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1) 1024#define C_028040_READ_SIZE 0xEFFFFFFF 1025#define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29) 1026#define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1) 1027#define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF 1028#define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) 1029#define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) 1030#define C_028040_ZRANGE_PRECISION 0x7FFFFFFF 1031#define S_028040_TILE_SPLIT(x) (((x) & 0x7) << 8) 1032#define G_028040_TILE_SPLIT(x) (((x) >> 8) & 0x7) 1033#define S_028040_NUM_BANKS(x) (((x) & 0x3) << 12) 1034#define G_028040_NUM_BANKS(x) (((x) >> 12) & 0x3) 1035#define S_028040_BANK_WIDTH(x) (((x) & 0x3) << 16) 1036#define G_028040_BANK_WIDTH(x) (((x) >> 16) & 0x3) 1037#define S_028040_BANK_HEIGHT(x) (((x) & 0x3) << 20) 1038#define G_028040_BANK_HEIGHT(x) (((x) >> 20) & 0x3) 1039#define S_028040_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24) 1040#define G_028040_MACRO_TILE_ASPECT(x) (((x) >> 24) & 0x3) 1041#define DB_STENCIL_INFO 0x28044 1042#define R_028044_DB_STENCIL_INFO 0x028044 1043#define S_028044_FORMAT(x) (((x) & 0x1) << 0) 1044#define G_028044_FORMAT(x) (((x) >> 0) & 0x1) 1045#define C_028044_FORMAT 0xFFFFFFFE 1046#define G_028044_TILE_SPLIT(x) (((x) >> 8) & 0x7) 1047#define DB_Z_READ_BASE 0x28048 1048#define DB_STENCIL_READ_BASE 0x2804c 1049#define DB_Z_WRITE_BASE 0x28050 1050#define DB_STENCIL_WRITE_BASE 0x28054 1051#define DB_DEPTH_SIZE 0x28058 1052#define R_028058_DB_DEPTH_SIZE 0x028058 1053#define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0) 1054#define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF) 1055#define C_028058_PITCH_TILE_MAX 0xFFFFF800 1056#define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11) 1057#define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF) 1058#define C_028058_HEIGHT_TILE_MAX 0xFFC007FF 1059#define R_02805C_DB_DEPTH_SLICE 0x02805C 1060#define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0) 1061#define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF) 1062#define C_02805C_SLICE_TILE_MAX 0xFFC00000 1063 1064#define SQ_PGM_START_PS 0x28840 1065#define SQ_PGM_START_VS 0x2885c 1066#define SQ_PGM_START_GS 0x28874 1067#define SQ_PGM_START_ES 0x2888c 1068#define SQ_PGM_START_FS 0x288a4 1069#define SQ_PGM_START_HS 0x288b8 1070#define SQ_PGM_START_LS 0x288d0 1071 1072#define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 1073#define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 1074#define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 1075#define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 1076#define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0 1077#define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0 1078#define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0 1079#define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00 1080#define VGT_STRMOUT_CONFIG 0x28b94 1081#define VGT_STRMOUT_BUFFER_CONFIG 0x28b98 1082 1083#define CB_TARGET_MASK 0x28238 1084#define CB_SHADER_MASK 0x2823c 1085 1086#define GDS_ADDR_BASE 0x28720 1087 1088#define CB_IMMED0_BASE 0x28b9c 1089#define CB_IMMED1_BASE 0x28ba0 1090#define CB_IMMED2_BASE 0x28ba4 1091#define CB_IMMED3_BASE 0x28ba8 1092#define CB_IMMED4_BASE 0x28bac 1093#define CB_IMMED5_BASE 0x28bb0 1094#define CB_IMMED6_BASE 0x28bb4 1095#define CB_IMMED7_BASE 0x28bb8 1096#define CB_IMMED8_BASE 0x28bbc 1097#define CB_IMMED9_BASE 0x28bc0 1098#define CB_IMMED10_BASE 0x28bc4 1099#define CB_IMMED11_BASE 0x28bc8 1100 1101/* all 12 CB blocks have these regs */ 1102#define CB_COLOR0_BASE 0x28c60 1103#define CB_COLOR0_PITCH 0x28c64 1104#define CB_COLOR0_SLICE 0x28c68 1105#define CB_COLOR0_VIEW 0x28c6c 1106#define R_028C6C_CB_COLOR0_VIEW 0x00028C6C 1107#define S_028C6C_SLICE_START(x) (((x) & 0x7FF) << 0) 1108#define G_028C6C_SLICE_START(x) (((x) >> 0) & 0x7FF) 1109#define C_028C6C_SLICE_START 0xFFFFF800 1110#define S_028C6C_SLICE_MAX(x) (((x) & 0x7FF) << 13) 1111#define G_028C6C_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 1112#define C_028C6C_SLICE_MAX 0xFF001FFF 1113#define R_028C70_CB_COLOR0_INFO 0x028C70 1114#define S_028C70_ENDIAN(x) (((x) & 0x3) << 0) 1115#define G_028C70_ENDIAN(x) (((x) >> 0) & 0x3) 1116#define C_028C70_ENDIAN 0xFFFFFFFC 1117#define S_028C70_FORMAT(x) (((x) & 0x3F) << 2) 1118#define G_028C70_FORMAT(x) (((x) >> 2) & 0x3F) 1119#define C_028C70_FORMAT 0xFFFFFF03 1120#define V_028C70_COLOR_INVALID 0x00000000 1121#define V_028C70_COLOR_8 0x00000001 1122#define V_028C70_COLOR_4_4 0x00000002 1123#define V_028C70_COLOR_3_3_2 0x00000003 1124#define V_028C70_COLOR_16 0x00000005 1125#define V_028C70_COLOR_16_FLOAT 0x00000006 1126#define V_028C70_COLOR_8_8 0x00000007 1127#define V_028C70_COLOR_5_6_5 0x00000008 1128#define V_028C70_COLOR_6_5_5 0x00000009 1129#define V_028C70_COLOR_1_5_5_5 0x0000000A 1130#define V_028C70_COLOR_4_4_4_4 0x0000000B 1131#define V_028C70_COLOR_5_5_5_1 0x0000000C 1132#define V_028C70_COLOR_32 0x0000000D 1133#define V_028C70_COLOR_32_FLOAT 0x0000000E 1134#define V_028C70_COLOR_16_16 0x0000000F 1135#define V_028C70_COLOR_16_16_FLOAT 0x00000010 1136#define V_028C70_COLOR_8_24 0x00000011 1137#define V_028C70_COLOR_8_24_FLOAT 0x00000012 1138#define V_028C70_COLOR_24_8 0x00000013 1139#define V_028C70_COLOR_24_8_FLOAT 0x00000014 1140#define V_028C70_COLOR_10_11_11 0x00000015 1141#define V_028C70_COLOR_10_11_11_FLOAT 0x00000016 1142#define V_028C70_COLOR_11_11_10 0x00000017 1143#define V_028C70_COLOR_11_11_10_FLOAT 0x00000018 1144#define V_028C70_COLOR_2_10_10_10 0x00000019 1145#define V_028C70_COLOR_8_8_8_8 0x0000001A 1146#define V_028C70_COLOR_10_10_10_2 0x0000001B 1147#define V_028C70_COLOR_X24_8_32_FLOAT 0x0000001C 1148#define V_028C70_COLOR_32_32 0x0000001D 1149#define V_028C70_COLOR_32_32_FLOAT 0x0000001E 1150#define V_028C70_COLOR_16_16_16_16 0x0000001F 1151#define V_028C70_COLOR_16_16_16_16_FLOAT 0x00000020 1152#define V_028C70_COLOR_32_32_32_32 0x00000022 1153#define V_028C70_COLOR_32_32_32_32_FLOAT 0x00000023 1154#define V_028C70_COLOR_32_32_32_FLOAT 0x00000030 1155#define S_028C70_ARRAY_MODE(x) (((x) & 0xF) << 8) 1156#define G_028C70_ARRAY_MODE(x) (((x) >> 8) & 0xF) 1157#define C_028C70_ARRAY_MODE 0xFFFFF0FF 1158#define V_028C70_ARRAY_LINEAR_GENERAL 0x00000000 1159#define V_028C70_ARRAY_LINEAR_ALIGNED 0x00000001 1160#define V_028C70_ARRAY_1D_TILED_THIN1 0x00000002 1161#define V_028C70_ARRAY_2D_TILED_THIN1 0x00000004 1162#define S_028C70_NUMBER_TYPE(x) (((x) & 0x7) << 12) 1163#define G_028C70_NUMBER_TYPE(x) (((x) >> 12) & 0x7) 1164#define C_028C70_NUMBER_TYPE 0xFFFF8FFF 1165#define V_028C70_NUMBER_UNORM 0x00000000 1166#define V_028C70_NUMBER_SNORM 0x00000001 1167#define V_028C70_NUMBER_USCALED 0x00000002 1168#define V_028C70_NUMBER_SSCALED 0x00000003 1169#define V_028C70_NUMBER_UINT 0x00000004 1170#define V_028C70_NUMBER_SINT 0x00000005 1171#define V_028C70_NUMBER_SRGB 0x00000006 1172#define V_028C70_NUMBER_FLOAT 0x00000007 1173#define S_028C70_COMP_SWAP(x) (((x) & 0x3) << 15) 1174#define G_028C70_COMP_SWAP(x) (((x) >> 15) & 0x3) 1175#define C_028C70_COMP_SWAP 0xFFFE7FFF 1176#define V_028C70_SWAP_STD 0x00000000 1177#define V_028C70_SWAP_ALT 0x00000001 1178#define V_028C70_SWAP_STD_REV 0x00000002 1179#define V_028C70_SWAP_ALT_REV 0x00000003 1180#define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 17) 1181#define G_028C70_FAST_CLEAR(x) (((x) >> 17) & 0x1) 1182#define C_028C70_FAST_CLEAR 0xFFFDFFFF 1183#define S_028C70_COMPRESSION(x) (((x) & 0x3) << 18) 1184#define G_028C70_COMPRESSION(x) (((x) >> 18) & 0x3) 1185#define C_028C70_COMPRESSION 0xFFF3FFFF 1186#define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 19) 1187#define G_028C70_BLEND_CLAMP(x) (((x) >> 19) & 0x1) 1188#define C_028C70_BLEND_CLAMP 0xFFF7FFFF 1189#define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 20) 1190#define G_028C70_BLEND_BYPASS(x) (((x) >> 20) & 0x1) 1191#define C_028C70_BLEND_BYPASS 0xFFEFFFFF 1192#define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 21) 1193#define G_028C70_SIMPLE_FLOAT(x) (((x) >> 21) & 0x1) 1194#define C_028C70_SIMPLE_FLOAT 0xFFDFFFFF 1195#define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 22) 1196#define G_028C70_ROUND_MODE(x) (((x) >> 22) & 0x1) 1197#define C_028C70_ROUND_MODE 0xFFBFFFFF 1198#define S_028C70_TILE_COMPACT(x) (((x) & 0x1) << 23) 1199#define G_028C70_TILE_COMPACT(x) (((x) >> 23) & 0x1) 1200#define C_028C70_TILE_COMPACT 0xFF7FFFFF 1201#define S_028C70_SOURCE_FORMAT(x) (((x) & 0x3) << 24) 1202#define G_028C70_SOURCE_FORMAT(x) (((x) >> 24) & 0x3) 1203#define C_028C70_SOURCE_FORMAT 0xFCFFFFFF 1204#define V_028C70_EXPORT_4C_32BPC 0x0 1205#define V_028C70_EXPORT_4C_16BPC 0x1 1206#define V_028C70_EXPORT_2C_32BPC 0x2 /* Do not use */ 1207#define S_028C70_RAT(x) (((x) & 0x1) << 26) 1208#define G_028C70_RAT(x) (((x) >> 26) & 0x1) 1209#define C_028C70_RAT 0xFBFFFFFF 1210#define S_028C70_RESOURCE_TYPE(x) (((x) & 0x7) << 27) 1211#define G_028C70_RESOURCE_TYPE(x) (((x) >> 27) & 0x7) 1212#define C_028C70_RESOURCE_TYPE 0xC7FFFFFF 1213 1214#define CB_COLOR0_INFO 0x28c70 1215# define CB_FORMAT(x) ((x) << 2) 1216# define CB_ARRAY_MODE(x) ((x) << 8) 1217# define ARRAY_LINEAR_GENERAL 0 1218# define ARRAY_LINEAR_ALIGNED 1 1219# define ARRAY_1D_TILED_THIN1 2 1220# define ARRAY_2D_TILED_THIN1 4 1221# define CB_SOURCE_FORMAT(x) ((x) << 24) 1222# define CB_SF_EXPORT_FULL 0 1223# define CB_SF_EXPORT_NORM 1 1224#define R_028C74_CB_COLOR0_ATTRIB 0x028C74 1225#define S_028C74_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 4) 1226#define G_028C74_NON_DISP_TILING_ORDER(x) (((x) >> 4) & 0x1) 1227#define C_028C74_NON_DISP_TILING_ORDER 0xFFFFFFEF 1228#define S_028C74_TILE_SPLIT(x) (((x) & 0xf) << 5) 1229#define G_028C74_TILE_SPLIT(x) (((x) >> 5) & 0xf) 1230#define S_028C74_NUM_BANKS(x) (((x) & 0x3) << 10) 1231#define G_028C74_NUM_BANKS(x) (((x) >> 10) & 0x3) 1232#define S_028C74_BANK_WIDTH(x) (((x) & 0x3) << 13) 1233#define G_028C74_BANK_WIDTH(x) (((x) >> 13) & 0x3) 1234#define S_028C74_BANK_HEIGHT(x) (((x) & 0x3) << 16) 1235#define G_028C74_BANK_HEIGHT(x) (((x) >> 16) & 0x3) 1236#define S_028C74_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19) 1237#define G_028C74_MACRO_TILE_ASPECT(x) (((x) >> 19) & 0x3) 1238#define CB_COLOR0_ATTRIB 0x28c74 1239# define CB_TILE_SPLIT(x) (((x) & 0x7) << 5) 1240# define ADDR_SURF_TILE_SPLIT_64B 0 1241# define ADDR_SURF_TILE_SPLIT_128B 1 1242# define ADDR_SURF_TILE_SPLIT_256B 2 1243# define ADDR_SURF_TILE_SPLIT_512B 3 1244# define ADDR_SURF_TILE_SPLIT_1KB 4 1245# define ADDR_SURF_TILE_SPLIT_2KB 5 1246# define ADDR_SURF_TILE_SPLIT_4KB 6 1247# define CB_NUM_BANKS(x) (((x) & 0x3) << 10) 1248# define ADDR_SURF_2_BANK 0 1249# define ADDR_SURF_4_BANK 1 1250# define ADDR_SURF_8_BANK 2 1251# define ADDR_SURF_16_BANK 3 1252# define CB_BANK_WIDTH(x) (((x) & 0x3) << 13) 1253# define ADDR_SURF_BANK_WIDTH_1 0 1254# define ADDR_SURF_BANK_WIDTH_2 1 1255# define ADDR_SURF_BANK_WIDTH_4 2 1256# define ADDR_SURF_BANK_WIDTH_8 3 1257# define CB_BANK_HEIGHT(x) (((x) & 0x3) << 16) 1258# define ADDR_SURF_BANK_HEIGHT_1 0 1259# define ADDR_SURF_BANK_HEIGHT_2 1 1260# define ADDR_SURF_BANK_HEIGHT_4 2 1261# define ADDR_SURF_BANK_HEIGHT_8 3 1262# define CB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19) 1263#define CB_COLOR0_DIM 0x28c78 1264/* only CB0-7 blocks have these regs */ 1265#define CB_COLOR0_CMASK 0x28c7c 1266#define CB_COLOR0_CMASK_SLICE 0x28c80 1267#define CB_COLOR0_FMASK 0x28c84 1268#define CB_COLOR0_FMASK_SLICE 0x28c88 1269#define CB_COLOR0_CLEAR_WORD0 0x28c8c 1270#define CB_COLOR0_CLEAR_WORD1 0x28c90 1271#define CB_COLOR0_CLEAR_WORD2 0x28c94 1272#define CB_COLOR0_CLEAR_WORD3 0x28c98 1273 1274#define CB_COLOR1_BASE 0x28c9c 1275#define CB_COLOR2_BASE 0x28cd8 1276#define CB_COLOR3_BASE 0x28d14 1277#define CB_COLOR4_BASE 0x28d50 1278#define CB_COLOR5_BASE 0x28d8c 1279#define CB_COLOR6_BASE 0x28dc8 1280#define CB_COLOR7_BASE 0x28e04 1281#define CB_COLOR8_BASE 0x28e40 1282#define CB_COLOR9_BASE 0x28e5c 1283#define CB_COLOR10_BASE 0x28e78 1284#define CB_COLOR11_BASE 0x28e94 1285 1286#define CB_COLOR1_PITCH 0x28ca0 1287#define CB_COLOR2_PITCH 0x28cdc 1288#define CB_COLOR3_PITCH 0x28d18 1289#define CB_COLOR4_PITCH 0x28d54 1290#define CB_COLOR5_PITCH 0x28d90 1291#define CB_COLOR6_PITCH 0x28dcc 1292#define CB_COLOR7_PITCH 0x28e08 1293#define CB_COLOR8_PITCH 0x28e44 1294#define CB_COLOR9_PITCH 0x28e60 1295#define CB_COLOR10_PITCH 0x28e7c 1296#define CB_COLOR11_PITCH 0x28e98 1297 1298#define CB_COLOR1_SLICE 0x28ca4 1299#define CB_COLOR2_SLICE 0x28ce0 1300#define CB_COLOR3_SLICE 0x28d1c 1301#define CB_COLOR4_SLICE 0x28d58 1302#define CB_COLOR5_SLICE 0x28d94 1303#define CB_COLOR6_SLICE 0x28dd0 1304#define CB_COLOR7_SLICE 0x28e0c 1305#define CB_COLOR8_SLICE 0x28e48 1306#define CB_COLOR9_SLICE 0x28e64 1307#define CB_COLOR10_SLICE 0x28e80 1308#define CB_COLOR11_SLICE 0x28e9c 1309 1310#define CB_COLOR1_VIEW 0x28ca8 1311#define CB_COLOR2_VIEW 0x28ce4 1312#define CB_COLOR3_VIEW 0x28d20 1313#define CB_COLOR4_VIEW 0x28d5c 1314#define CB_COLOR5_VIEW 0x28d98 1315#define CB_COLOR6_VIEW 0x28dd4 1316#define CB_COLOR7_VIEW 0x28e10 1317#define CB_COLOR8_VIEW 0x28e4c 1318#define CB_COLOR9_VIEW 0x28e68 1319#define CB_COLOR10_VIEW 0x28e84 1320#define CB_COLOR11_VIEW 0x28ea0 1321 1322#define CB_COLOR1_INFO 0x28cac 1323#define CB_COLOR2_INFO 0x28ce8 1324#define CB_COLOR3_INFO 0x28d24 1325#define CB_COLOR4_INFO 0x28d60 1326#define CB_COLOR5_INFO 0x28d9c 1327#define CB_COLOR6_INFO 0x28dd8 1328#define CB_COLOR7_INFO 0x28e14 1329#define CB_COLOR8_INFO 0x28e50 1330#define CB_COLOR9_INFO 0x28e6c 1331#define CB_COLOR10_INFO 0x28e88 1332#define CB_COLOR11_INFO 0x28ea4 1333 1334#define CB_COLOR1_ATTRIB 0x28cb0 1335#define CB_COLOR2_ATTRIB 0x28cec 1336#define CB_COLOR3_ATTRIB 0x28d28 1337#define CB_COLOR4_ATTRIB 0x28d64 1338#define CB_COLOR5_ATTRIB 0x28da0 1339#define CB_COLOR6_ATTRIB 0x28ddc 1340#define CB_COLOR7_ATTRIB 0x28e18 1341#define CB_COLOR8_ATTRIB 0x28e54 1342#define CB_COLOR9_ATTRIB 0x28e70 1343#define CB_COLOR10_ATTRIB 0x28e8c 1344#define CB_COLOR11_ATTRIB 0x28ea8 1345 1346#define CB_COLOR1_DIM 0x28cb4 1347#define CB_COLOR2_DIM 0x28cf0 1348#define CB_COLOR3_DIM 0x28d2c 1349#define CB_COLOR4_DIM 0x28d68 1350#define CB_COLOR5_DIM 0x28da4 1351#define CB_COLOR6_DIM 0x28de0 1352#define CB_COLOR7_DIM 0x28e1c 1353#define CB_COLOR8_DIM 0x28e58 1354#define CB_COLOR9_DIM 0x28e74 1355#define CB_COLOR10_DIM 0x28e90 1356#define CB_COLOR11_DIM 0x28eac 1357 1358#define CB_COLOR1_CMASK 0x28cb8 1359#define CB_COLOR2_CMASK 0x28cf4 1360#define CB_COLOR3_CMASK 0x28d30 1361#define CB_COLOR4_CMASK 0x28d6c 1362#define CB_COLOR5_CMASK 0x28da8 1363#define CB_COLOR6_CMASK 0x28de4 1364#define CB_COLOR7_CMASK 0x28e20 1365 1366#define CB_COLOR1_CMASK_SLICE 0x28cbc 1367#define CB_COLOR2_CMASK_SLICE 0x28cf8 1368#define CB_COLOR3_CMASK_SLICE 0x28d34 1369#define CB_COLOR4_CMASK_SLICE 0x28d70 1370#define CB_COLOR5_CMASK_SLICE 0x28dac 1371#define CB_COLOR6_CMASK_SLICE 0x28de8 1372#define CB_COLOR7_CMASK_SLICE 0x28e24 1373 1374#define CB_COLOR1_FMASK 0x28cc0 1375#define CB_COLOR2_FMASK 0x28cfc 1376#define CB_COLOR3_FMASK 0x28d38 1377#define CB_COLOR4_FMASK 0x28d74 1378#define CB_COLOR5_FMASK 0x28db0 1379#define CB_COLOR6_FMASK 0x28dec 1380#define CB_COLOR7_FMASK 0x28e28 1381 1382#define CB_COLOR1_FMASK_SLICE 0x28cc4 1383#define CB_COLOR2_FMASK_SLICE 0x28d00 1384#define CB_COLOR3_FMASK_SLICE 0x28d3c 1385#define CB_COLOR4_FMASK_SLICE 0x28d78 1386#define CB_COLOR5_FMASK_SLICE 0x28db4 1387#define CB_COLOR6_FMASK_SLICE 0x28df0 1388#define CB_COLOR7_FMASK_SLICE 0x28e2c 1389 1390#define CB_COLOR1_CLEAR_WORD0 0x28cc8 1391#define CB_COLOR2_CLEAR_WORD0 0x28d04 1392#define CB_COLOR3_CLEAR_WORD0 0x28d40 1393#define CB_COLOR4_CLEAR_WORD0 0x28d7c 1394#define CB_COLOR5_CLEAR_WORD0 0x28db8 1395#define CB_COLOR6_CLEAR_WORD0 0x28df4 1396#define CB_COLOR7_CLEAR_WORD0 0x28e30 1397 1398#define CB_COLOR1_CLEAR_WORD1 0x28ccc 1399#define CB_COLOR2_CLEAR_WORD1 0x28d08 1400#define CB_COLOR3_CLEAR_WORD1 0x28d44 1401#define CB_COLOR4_CLEAR_WORD1 0x28d80 1402#define CB_COLOR5_CLEAR_WORD1 0x28dbc 1403#define CB_COLOR6_CLEAR_WORD1 0x28df8 1404#define CB_COLOR7_CLEAR_WORD1 0x28e34 1405 1406#define CB_COLOR1_CLEAR_WORD2 0x28cd0 1407#define CB_COLOR2_CLEAR_WORD2 0x28d0c 1408#define CB_COLOR3_CLEAR_WORD2 0x28d48 1409#define CB_COLOR4_CLEAR_WORD2 0x28d84 1410#define CB_COLOR5_CLEAR_WORD2 0x28dc0 1411#define CB_COLOR6_CLEAR_WORD2 0x28dfc 1412#define CB_COLOR7_CLEAR_WORD2 0x28e38 1413 1414#define CB_COLOR1_CLEAR_WORD3 0x28cd4 1415#define CB_COLOR2_CLEAR_WORD3 0x28d10 1416#define CB_COLOR3_CLEAR_WORD3 0x28d4c 1417#define CB_COLOR4_CLEAR_WORD3 0x28d88 1418#define CB_COLOR5_CLEAR_WORD3 0x28dc4 1419#define CB_COLOR6_CLEAR_WORD3 0x28e00 1420#define CB_COLOR7_CLEAR_WORD3 0x28e3c 1421 1422#define SQ_TEX_RESOURCE_WORD0_0 0x30000 1423# define TEX_DIM(x) ((x) << 0) 1424# define SQ_TEX_DIM_1D 0 1425# define SQ_TEX_DIM_2D 1 1426# define SQ_TEX_DIM_3D 2 1427# define SQ_TEX_DIM_CUBEMAP 3 1428# define SQ_TEX_DIM_1D_ARRAY 4 1429# define SQ_TEX_DIM_2D_ARRAY 5 1430# define SQ_TEX_DIM_2D_MSAA 6 1431# define SQ_TEX_DIM_2D_ARRAY_MSAA 7 1432#define SQ_TEX_RESOURCE_WORD1_0 0x30004 1433# define TEX_ARRAY_MODE(x) ((x) << 28) 1434#define SQ_TEX_RESOURCE_WORD2_0 0x30008 1435#define SQ_TEX_RESOURCE_WORD3_0 0x3000C 1436#define SQ_TEX_RESOURCE_WORD4_0 0x30010 1437# define TEX_DST_SEL_X(x) ((x) << 16) 1438# define TEX_DST_SEL_Y(x) ((x) << 19) 1439# define TEX_DST_SEL_Z(x) ((x) << 22) 1440# define TEX_DST_SEL_W(x) ((x) << 25) 1441# define SQ_SEL_X 0 1442# define SQ_SEL_Y 1 1443# define SQ_SEL_Z 2 1444# define SQ_SEL_W 3 1445# define SQ_SEL_0 4 1446# define SQ_SEL_1 5 1447#define SQ_TEX_RESOURCE_WORD5_0 0x30014 1448#define SQ_TEX_RESOURCE_WORD6_0 0x30018 1449# define TEX_TILE_SPLIT(x) (((x) & 0x7) << 29) 1450#define SQ_TEX_RESOURCE_WORD7_0 0x3001c 1451# define MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6) 1452# define TEX_BANK_WIDTH(x) (((x) & 0x3) << 8) 1453# define TEX_BANK_HEIGHT(x) (((x) & 0x3) << 10) 1454# define TEX_NUM_BANKS(x) (((x) & 0x3) << 16) 1455#define R_030000_SQ_TEX_RESOURCE_WORD0_0 0x030000 1456#define S_030000_DIM(x) (((x) & 0x7) << 0) 1457#define G_030000_DIM(x) (((x) >> 0) & 0x7) 1458#define C_030000_DIM 0xFFFFFFF8 1459#define V_030000_SQ_TEX_DIM_1D 0x00000000 1460#define V_030000_SQ_TEX_DIM_2D 0x00000001 1461#define V_030000_SQ_TEX_DIM_3D 0x00000002 1462#define V_030000_SQ_TEX_DIM_CUBEMAP 0x00000003 1463#define V_030000_SQ_TEX_DIM_1D_ARRAY 0x00000004 1464#define V_030000_SQ_TEX_DIM_2D_ARRAY 0x00000005 1465#define V_030000_SQ_TEX_DIM_2D_MSAA 0x00000006 1466#define V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 1467#define S_030000_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 5) 1468#define G_030000_NON_DISP_TILING_ORDER(x) (((x) >> 5) & 0x1) 1469#define C_030000_NON_DISP_TILING_ORDER 0xFFFFFFDF 1470#define S_030000_PITCH(x) (((x) & 0xFFF) << 6) 1471#define G_030000_PITCH(x) (((x) >> 6) & 0xFFF) 1472#define C_030000_PITCH 0xFFFC003F 1473#define S_030000_TEX_WIDTH(x) (((x) & 0x3FFF) << 18) 1474#define G_030000_TEX_WIDTH(x) (((x) >> 18) & 0x3FFF) 1475#define C_030000_TEX_WIDTH 0x0003FFFF 1476#define R_030004_SQ_TEX_RESOURCE_WORD1_0 0x030004 1477#define S_030004_TEX_HEIGHT(x) (((x) & 0x3FFF) << 0) 1478#define G_030004_TEX_HEIGHT(x) (((x) >> 0) & 0x3FFF) 1479#define C_030004_TEX_HEIGHT 0xFFFFC000 1480#define S_030004_TEX_DEPTH(x) (((x) & 0x1FFF) << 14) 1481#define G_030004_TEX_DEPTH(x) (((x) >> 14) & 0x1FFF) 1482#define C_030004_TEX_DEPTH 0xF8003FFF 1483#define S_030004_ARRAY_MODE(x) (((x) & 0xF) << 28) 1484#define G_030004_ARRAY_MODE(x) (((x) >> 28) & 0xF) 1485#define C_030004_ARRAY_MODE 0x0FFFFFFF 1486#define R_030008_SQ_TEX_RESOURCE_WORD2_0 0x030008 1487#define S_030008_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 1488#define G_030008_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 1489#define C_030008_BASE_ADDRESS 0x00000000 1490#define R_03000C_SQ_TEX_RESOURCE_WORD3_0 0x03000C 1491#define S_03000C_MIP_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 1492#define G_03000C_MIP_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 1493#define C_03000C_MIP_ADDRESS 0x00000000 1494#define R_030010_SQ_TEX_RESOURCE_WORD4_0 0x030010 1495#define S_030010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) 1496#define G_030010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) 1497#define C_030010_FORMAT_COMP_X 0xFFFFFFFC 1498#define V_030010_SQ_FORMAT_COMP_UNSIGNED 0x00000000 1499#define V_030010_SQ_FORMAT_COMP_SIGNED 0x00000001 1500#define V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED 0x00000002 1501#define S_030010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) 1502#define G_030010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) 1503#define C_030010_FORMAT_COMP_Y 0xFFFFFFF3 1504#define S_030010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) 1505#define G_030010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) 1506#define C_030010_FORMAT_COMP_Z 0xFFFFFFCF 1507#define S_030010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) 1508#define G_030010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) 1509#define C_030010_FORMAT_COMP_W 0xFFFFFF3F 1510#define S_030010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) 1511#define G_030010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) 1512#define C_030010_NUM_FORMAT_ALL 0xFFFFFCFF 1513#define V_030010_SQ_NUM_FORMAT_NORM 0x00000000 1514#define V_030010_SQ_NUM_FORMAT_INT 0x00000001 1515#define V_030010_SQ_NUM_FORMAT_SCALED 0x00000002 1516#define S_030010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) 1517#define G_030010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) 1518#define C_030010_SRF_MODE_ALL 0xFFFFFBFF 1519#define V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE 0x00000000 1520#define V_030010_SRF_MODE_NO_ZERO 0x00000001 1521#define S_030010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) 1522#define G_030010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) 1523#define C_030010_FORCE_DEGAMMA 0xFFFFF7FF 1524#define S_030010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) 1525#define G_030010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) 1526#define C_030010_ENDIAN_SWAP 0xFFFFCFFF 1527#define S_030010_DST_SEL_X(x) (((x) & 0x7) << 16) 1528#define G_030010_DST_SEL_X(x) (((x) >> 16) & 0x7) 1529#define C_030010_DST_SEL_X 0xFFF8FFFF 1530#define V_030010_SQ_SEL_X 0x00000000 1531#define V_030010_SQ_SEL_Y 0x00000001 1532#define V_030010_SQ_SEL_Z 0x00000002 1533#define V_030010_SQ_SEL_W 0x00000003 1534#define V_030010_SQ_SEL_0 0x00000004 1535#define V_030010_SQ_SEL_1 0x00000005 1536#define S_030010_DST_SEL_Y(x) (((x) & 0x7) << 19) 1537#define G_030010_DST_SEL_Y(x) (((x) >> 19) & 0x7) 1538#define C_030010_DST_SEL_Y 0xFFC7FFFF 1539#define S_030010_DST_SEL_Z(x) (((x) & 0x7) << 22) 1540#define G_030010_DST_SEL_Z(x) (((x) >> 22) & 0x7) 1541#define C_030010_DST_SEL_Z 0xFE3FFFFF 1542#define S_030010_DST_SEL_W(x) (((x) & 0x7) << 25) 1543#define G_030010_DST_SEL_W(x) (((x) >> 25) & 0x7) 1544#define C_030010_DST_SEL_W 0xF1FFFFFF 1545#define S_030010_BASE_LEVEL(x) (((x) & 0xF) << 28) 1546#define G_030010_BASE_LEVEL(x) (((x) >> 28) & 0xF) 1547#define C_030010_BASE_LEVEL 0x0FFFFFFF 1548#define R_030014_SQ_TEX_RESOURCE_WORD5_0 0x030014 1549#define S_030014_LAST_LEVEL(x) (((x) & 0xF) << 0) 1550#define G_030014_LAST_LEVEL(x) (((x) >> 0) & 0xF) 1551#define C_030014_LAST_LEVEL 0xFFFFFFF0 1552#define S_030014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) 1553#define G_030014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) 1554#define C_030014_BASE_ARRAY 0xFFFE000F 1555#define S_030014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) 1556#define G_030014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) 1557#define C_030014_LAST_ARRAY 0xC001FFFF 1558#define R_030018_SQ_TEX_RESOURCE_WORD6_0 0x030018 1559#define S_030018_MAX_ANISO(x) (((x) & 0x7) << 0) 1560#define G_030018_MAX_ANISO(x) (((x) >> 0) & 0x7) 1561#define C_030018_MAX_ANISO 0xFFFFFFF8 1562#define S_030018_PERF_MODULATION(x) (((x) & 0x7) << 3) 1563#define G_030018_PERF_MODULATION(x) (((x) >> 3) & 0x7) 1564#define C_030018_PERF_MODULATION 0xFFFFFFC7 1565#define S_030018_INTERLACED(x) (((x) & 0x1) << 6) 1566#define G_030018_INTERLACED(x) (((x) >> 6) & 0x1) 1567#define C_030018_INTERLACED 0xFFFFFFBF 1568#define S_030018_TILE_SPLIT(x) (((x) & 0x7) << 29) 1569#define G_030018_TILE_SPLIT(x) (((x) >> 29) & 0x7) 1570#define R_03001C_SQ_TEX_RESOURCE_WORD7_0 0x03001C 1571#define S_03001C_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6) 1572#define G_03001C_MACRO_TILE_ASPECT(x) (((x) >> 6) & 0x3) 1573#define S_03001C_BANK_WIDTH(x) (((x) & 0x3) << 8) 1574#define G_03001C_BANK_WIDTH(x) (((x) >> 8) & 0x3) 1575#define S_03001C_BANK_HEIGHT(x) (((x) & 0x3) << 10) 1576#define G_03001C_BANK_HEIGHT(x) (((x) >> 10) & 0x3) 1577#define S_03001C_NUM_BANKS(x) (((x) & 0x3) << 16) 1578#define G_03001C_NUM_BANKS(x) (((x) >> 16) & 0x3) 1579#define S_03001C_TYPE(x) (((x) & 0x3) << 30) 1580#define G_03001C_TYPE(x) (((x) >> 30) & 0x3) 1581#define C_03001C_TYPE 0x3FFFFFFF 1582#define V_03001C_SQ_TEX_VTX_INVALID_TEXTURE 0x00000000 1583#define V_03001C_SQ_TEX_VTX_INVALID_BUFFER 0x00000001 1584#define V_03001C_SQ_TEX_VTX_VALID_TEXTURE 0x00000002 1585#define V_03001C_SQ_TEX_VTX_VALID_BUFFER 0x00000003 1586#define S_03001C_DATA_FORMAT(x) (((x) & 0x3F) << 0) 1587#define G_03001C_DATA_FORMAT(x) (((x) >> 0) & 0x3F) 1588#define C_03001C_DATA_FORMAT 0xFFFFFFC0 1589 1590#define SQ_VTX_CONSTANT_WORD0_0 0x30000 1591#define SQ_VTX_CONSTANT_WORD1_0 0x30004 1592#define SQ_VTX_CONSTANT_WORD2_0 0x30008 1593# define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0) 1594# define SQ_VTXC_STRIDE(x) ((x) << 8) 1595# define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30) 1596# define SQ_ENDIAN_NONE 0 1597# define SQ_ENDIAN_8IN16 1 1598# define SQ_ENDIAN_8IN32 2 1599#define SQ_VTX_CONSTANT_WORD3_0 0x3000C 1600# define SQ_VTCX_SEL_X(x) ((x) << 3) 1601# define SQ_VTCX_SEL_Y(x) ((x) << 6) 1602# define SQ_VTCX_SEL_Z(x) ((x) << 9) 1603# define SQ_VTCX_SEL_W(x) ((x) << 12) 1604#define SQ_VTX_CONSTANT_WORD4_0 0x30010 1605#define SQ_VTX_CONSTANT_WORD5_0 0x30014 1606#define SQ_VTX_CONSTANT_WORD6_0 0x30018 1607#define SQ_VTX_CONSTANT_WORD7_0 0x3001c 1608 1609#define TD_PS_BORDER_COLOR_INDEX 0xA400 1610#define TD_PS_BORDER_COLOR_RED 0xA404 1611#define TD_PS_BORDER_COLOR_GREEN 0xA408 1612#define TD_PS_BORDER_COLOR_BLUE 0xA40C 1613#define TD_PS_BORDER_COLOR_ALPHA 0xA410 1614#define TD_VS_BORDER_COLOR_INDEX 0xA414 1615#define TD_VS_BORDER_COLOR_RED 0xA418 1616#define TD_VS_BORDER_COLOR_GREEN 0xA41C 1617#define TD_VS_BORDER_COLOR_BLUE 0xA420 1618#define TD_VS_BORDER_COLOR_ALPHA 0xA424 1619#define TD_GS_BORDER_COLOR_INDEX 0xA428 1620#define TD_GS_BORDER_COLOR_RED 0xA42C 1621#define TD_GS_BORDER_COLOR_GREEN 0xA430 1622#define TD_GS_BORDER_COLOR_BLUE 0xA434 1623#define TD_GS_BORDER_COLOR_ALPHA 0xA438 1624#define TD_HS_BORDER_COLOR_INDEX 0xA43C 1625#define TD_HS_BORDER_COLOR_RED 0xA440 1626#define TD_HS_BORDER_COLOR_GREEN 0xA444 1627#define TD_HS_BORDER_COLOR_BLUE 0xA448 1628#define TD_HS_BORDER_COLOR_ALPHA 0xA44C 1629#define TD_LS_BORDER_COLOR_INDEX 0xA450 1630#define TD_LS_BORDER_COLOR_RED 0xA454 1631#define TD_LS_BORDER_COLOR_GREEN 0xA458 1632#define TD_LS_BORDER_COLOR_BLUE 0xA45C 1633#define TD_LS_BORDER_COLOR_ALPHA 0xA460 1634#define TD_CS_BORDER_COLOR_INDEX 0xA464 1635#define TD_CS_BORDER_COLOR_RED 0xA468 1636#define TD_CS_BORDER_COLOR_GREEN 0xA46C 1637#define TD_CS_BORDER_COLOR_BLUE 0xA470 1638#define TD_CS_BORDER_COLOR_ALPHA 0xA474 1639 1640/* cayman 3D regs */ 1641#define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B4 1642#define CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS 0x8E48 1643#define CAYMAN_DB_EQAA 0x28804 1644#define CAYMAN_DB_DEPTH_INFO 0x2803C 1645#define CAYMAN_PA_SC_AA_CONFIG 0x28BE0 1646#define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0 1647#define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7 1648#define CAYMAN_SX_SCATTER_EXPORT_BASE 0x28358 1649/* cayman packet3 addition */ 1650#define CAYMAN_PACKET3_DEALLOC_STATE 0x14 1651 1652#endif 1653