1/* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26#include "drmP.h" 27#include "radeon_drm.h" 28#include "radeon.h" 29 30#include "atom.h" 31#include <asm/div64.h> 32 33#include "drm_crtc_helper.h" 34#include "drm_edid.h" 35 36static void avivo_crtc_load_lut(struct drm_crtc *crtc) 37{ 38 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 39 struct drm_device *dev = crtc->dev; 40 struct radeon_device *rdev = dev->dev_private; 41 int i; 42 43 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 44 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 45 46 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 47 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 49 50 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 51 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 53 54 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); 55 WREG32(AVIVO_DC_LUT_RW_MODE, 0); 56 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); 57 58 WREG8(AVIVO_DC_LUT_RW_INDEX, 0); 59 for (i = 0; i < 256; i++) { 60 WREG32(AVIVO_DC_LUT_30_COLOR, 61 (radeon_crtc->lut_r[i] << 20) | 62 (radeon_crtc->lut_g[i] << 10) | 63 (radeon_crtc->lut_b[i] << 0)); 64 } 65 66 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); 67} 68 69static void dce4_crtc_load_lut(struct drm_crtc *crtc) 70{ 71 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 72 struct drm_device *dev = crtc->dev; 73 struct radeon_device *rdev = dev->dev_private; 74 int i; 75 76 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 77 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 78 79 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 80 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 82 83 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 84 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 86 87 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 88 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 89 90 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 91 for (i = 0; i < 256; i++) { 92 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 93 (radeon_crtc->lut_r[i] << 20) | 94 (radeon_crtc->lut_g[i] << 10) | 95 (radeon_crtc->lut_b[i] << 0)); 96 } 97} 98 99static void dce5_crtc_load_lut(struct drm_crtc *crtc) 100{ 101 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 102 struct drm_device *dev = crtc->dev; 103 struct radeon_device *rdev = dev->dev_private; 104 int i; 105 106 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 107 108 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 109 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | 110 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); 111 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, 112 NI_GRPH_PRESCALE_BYPASS); 113 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, 114 NI_OVL_PRESCALE_BYPASS); 115 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, 116 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | 117 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); 118 119 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 120 121 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 122 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 123 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 124 125 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 126 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 127 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 128 129 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 130 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 131 132 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 133 for (i = 0; i < 256; i++) { 134 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 135 (radeon_crtc->lut_r[i] << 20) | 136 (radeon_crtc->lut_g[i] << 10) | 137 (radeon_crtc->lut_b[i] << 0)); 138 } 139 140 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, 141 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 142 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 143 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 144 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); 145 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, 146 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | 147 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); 148 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, 149 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | 150 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); 151 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 152 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) | 153 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); 154 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 155 WREG32(0x6940 + radeon_crtc->crtc_offset, 0); 156 157} 158 159static void legacy_crtc_load_lut(struct drm_crtc *crtc) 160{ 161 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 162 struct drm_device *dev = crtc->dev; 163 struct radeon_device *rdev = dev->dev_private; 164 int i; 165 uint32_t dac2_cntl; 166 167 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 168 if (radeon_crtc->crtc_id == 0) 169 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; 170 else 171 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; 172 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 173 174 WREG8(RADEON_PALETTE_INDEX, 0); 175 for (i = 0; i < 256; i++) { 176 WREG32(RADEON_PALETTE_30_DATA, 177 (radeon_crtc->lut_r[i] << 20) | 178 (radeon_crtc->lut_g[i] << 10) | 179 (radeon_crtc->lut_b[i] << 0)); 180 } 181} 182 183void radeon_crtc_load_lut(struct drm_crtc *crtc) 184{ 185 struct drm_device *dev = crtc->dev; 186 struct radeon_device *rdev = dev->dev_private; 187 188 if (!crtc->enabled) 189 return; 190 191 if (ASIC_IS_DCE5(rdev)) 192 dce5_crtc_load_lut(crtc); 193 else if (ASIC_IS_DCE4(rdev)) 194 dce4_crtc_load_lut(crtc); 195 else if (ASIC_IS_AVIVO(rdev)) 196 avivo_crtc_load_lut(crtc); 197 else 198 legacy_crtc_load_lut(crtc); 199} 200 201/** Sets the color ramps on behalf of fbcon */ 202void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 203 u16 blue, int regno) 204{ 205 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 206 207 radeon_crtc->lut_r[regno] = red >> 6; 208 radeon_crtc->lut_g[regno] = green >> 6; 209 radeon_crtc->lut_b[regno] = blue >> 6; 210} 211 212/** Gets the color ramps on behalf of fbcon */ 213void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 214 u16 *blue, int regno) 215{ 216 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 217 218 *red = radeon_crtc->lut_r[regno] << 6; 219 *green = radeon_crtc->lut_g[regno] << 6; 220 *blue = radeon_crtc->lut_b[regno] << 6; 221} 222 223static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 224 u16 *blue, uint32_t start, uint32_t size) 225{ 226 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 227 int end = (start + size > 256) ? 256 : start + size, i; 228 229 /* userspace palettes are always correct as is */ 230 for (i = start; i < end; i++) { 231 radeon_crtc->lut_r[i] = red[i] >> 6; 232 radeon_crtc->lut_g[i] = green[i] >> 6; 233 radeon_crtc->lut_b[i] = blue[i] >> 6; 234 } 235 radeon_crtc_load_lut(crtc); 236} 237 238static void radeon_crtc_destroy(struct drm_crtc *crtc) 239{ 240 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 241 242 drm_crtc_cleanup(crtc); 243 kfree(radeon_crtc); 244} 245 246/* 247 * Handle unpin events outside the interrupt handler proper. 248 */ 249static void radeon_unpin_work_func(struct work_struct *__work) 250{ 251 struct radeon_unpin_work *work = 252 container_of(__work, struct radeon_unpin_work, work); 253 int r; 254 255 /* unpin of the old buffer */ 256 r = radeon_bo_reserve(work->old_rbo, false); 257 if (likely(r == 0)) { 258 r = radeon_bo_unpin(work->old_rbo); 259 if (unlikely(r != 0)) { 260 DRM_ERROR("failed to unpin buffer after flip\n"); 261 } 262 radeon_bo_unreserve(work->old_rbo); 263 } else 264 DRM_ERROR("failed to reserve buffer after flip\n"); 265 266 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 267 kfree(work); 268} 269 270void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) 271{ 272 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 273 struct radeon_unpin_work *work; 274 struct drm_pending_vblank_event *e; 275 struct timeval now; 276 unsigned long flags; 277 u32 update_pending; 278 int vpos, hpos; 279 280 spin_lock_irqsave(&rdev->ddev->event_lock, flags); 281 work = radeon_crtc->unpin_work; 282 if (work == NULL || 283 (work->fence && !radeon_fence_signaled(work->fence))) { 284 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 285 return; 286 } 287 /* New pageflip, or just completion of a previous one? */ 288 if (!radeon_crtc->deferred_flip_completion) { 289 /* do the flip (mmio) */ 290 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base); 291 } else { 292 /* This is just a completion of a flip queued in crtc 293 * at last invocation. Make sure we go directly to 294 * completion routine. 295 */ 296 update_pending = 0; 297 radeon_crtc->deferred_flip_completion = 0; 298 } 299 300 /* Has the pageflip already completed in crtc, or is it certain 301 * to complete in this vblank? 302 */ 303 if (update_pending && 304 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 305 &vpos, &hpos)) && 306 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) || 307 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) { 308 /* crtc didn't flip in this target vblank interval, 309 * but flip is pending in crtc. Based on the current 310 * scanout position we know that the current frame is 311 * (nearly) complete and the flip will (likely) 312 * complete before the start of the next frame. 313 */ 314 update_pending = 0; 315 } 316 if (update_pending) { 317 /* crtc didn't flip in this target vblank interval, 318 * but flip is pending in crtc. It will complete it 319 * in next vblank interval, so complete the flip at 320 * next vblank irq. 321 */ 322 radeon_crtc->deferred_flip_completion = 1; 323 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 324 return; 325 } 326 327 /* Pageflip (will be) certainly completed in this vblank. Clean up. */ 328 radeon_crtc->unpin_work = NULL; 329 330 /* wakeup userspace */ 331 if (work->event) { 332 e = work->event; 333 e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now); 334 e->event.tv_sec = now.tv_sec; 335 e->event.tv_usec = now.tv_usec; 336 list_add_tail(&e->base.link, &e->base.file_priv->event_list); 337 wake_up_interruptible(&e->base.file_priv->event_wait); 338 } 339 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 340 341 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id); 342 radeon_fence_unref(&work->fence); 343 radeon_post_page_flip(work->rdev, work->crtc_id); 344 schedule_work(&work->work); 345} 346 347static int radeon_crtc_page_flip(struct drm_crtc *crtc, 348 struct drm_framebuffer *fb, 349 struct drm_pending_vblank_event *event) 350{ 351 struct drm_device *dev = crtc->dev; 352 struct radeon_device *rdev = dev->dev_private; 353 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 354 struct radeon_framebuffer *old_radeon_fb; 355 struct radeon_framebuffer *new_radeon_fb; 356 struct drm_gem_object *obj; 357 struct radeon_bo *rbo; 358 struct radeon_unpin_work *work; 359 unsigned long flags; 360 u32 tiling_flags, pitch_pixels; 361 u64 base; 362 int r; 363 364 work = kzalloc(sizeof *work, GFP_KERNEL); 365 if (work == NULL) 366 return -ENOMEM; 367 368 work->event = event; 369 work->rdev = rdev; 370 work->crtc_id = radeon_crtc->crtc_id; 371 old_radeon_fb = to_radeon_framebuffer(crtc->fb); 372 new_radeon_fb = to_radeon_framebuffer(fb); 373 /* schedule unpin of the old buffer */ 374 obj = old_radeon_fb->obj; 375 /* take a reference to the old object */ 376 drm_gem_object_reference(obj); 377 rbo = gem_to_radeon_bo(obj); 378 work->old_rbo = rbo; 379 obj = new_radeon_fb->obj; 380 rbo = gem_to_radeon_bo(obj); 381 if (rbo->tbo.sync_obj) 382 work->fence = radeon_fence_ref(rbo->tbo.sync_obj); 383 INIT_WORK(&work->work, radeon_unpin_work_func); 384 385 /* We borrow the event spin lock for protecting unpin_work */ 386 spin_lock_irqsave(&dev->event_lock, flags); 387 if (radeon_crtc->unpin_work) { 388 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 389 r = -EBUSY; 390 goto unlock_free; 391 } 392 radeon_crtc->unpin_work = work; 393 radeon_crtc->deferred_flip_completion = 0; 394 spin_unlock_irqrestore(&dev->event_lock, flags); 395 396 /* pin the new buffer */ 397 DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n", 398 work->old_rbo, rbo); 399 400 r = radeon_bo_reserve(rbo, false); 401 if (unlikely(r != 0)) { 402 DRM_ERROR("failed to reserve new rbo buffer before flip\n"); 403 goto pflip_cleanup; 404 } 405 /* Only 27 bit offset for legacy CRTC */ 406 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 407 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base); 408 if (unlikely(r != 0)) { 409 radeon_bo_unreserve(rbo); 410 r = -EINVAL; 411 DRM_ERROR("failed to pin new rbo buffer before flip\n"); 412 goto pflip_cleanup; 413 } 414 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 415 radeon_bo_unreserve(rbo); 416 417 if (!ASIC_IS_AVIVO(rdev)) { 418 /* crtc offset is from display base addr not FB location */ 419 base -= radeon_crtc->legacy_display_base_addr; 420 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8); 421 422 if (tiling_flags & RADEON_TILING_MACRO) { 423 if (ASIC_IS_R300(rdev)) { 424 base &= ~0x7ff; 425 } else { 426 int byteshift = fb->bits_per_pixel >> 4; 427 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11; 428 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); 429 } 430 } else { 431 int offset = crtc->y * pitch_pixels + crtc->x; 432 switch (fb->bits_per_pixel) { 433 case 8: 434 default: 435 offset *= 1; 436 break; 437 case 15: 438 case 16: 439 offset *= 2; 440 break; 441 case 24: 442 offset *= 3; 443 break; 444 case 32: 445 offset *= 4; 446 break; 447 } 448 base += offset; 449 } 450 base &= ~7; 451 } 452 453 spin_lock_irqsave(&dev->event_lock, flags); 454 work->new_crtc_base = base; 455 spin_unlock_irqrestore(&dev->event_lock, flags); 456 457 /* update crtc fb */ 458 crtc->fb = fb; 459 460 r = drm_vblank_get(dev, radeon_crtc->crtc_id); 461 if (r) { 462 DRM_ERROR("failed to get vblank before flip\n"); 463 goto pflip_cleanup1; 464 } 465 466 /* set the proper interrupt */ 467 radeon_pre_page_flip(rdev, radeon_crtc->crtc_id); 468 469 return 0; 470 471pflip_cleanup1: 472 if (unlikely(radeon_bo_reserve(rbo, false) != 0)) { 473 DRM_ERROR("failed to reserve new rbo in error path\n"); 474 goto pflip_cleanup; 475 } 476 if (unlikely(radeon_bo_unpin(rbo) != 0)) { 477 DRM_ERROR("failed to unpin new rbo in error path\n"); 478 } 479 radeon_bo_unreserve(rbo); 480 481pflip_cleanup: 482 spin_lock_irqsave(&dev->event_lock, flags); 483 radeon_crtc->unpin_work = NULL; 484unlock_free: 485 spin_unlock_irqrestore(&dev->event_lock, flags); 486 drm_gem_object_unreference_unlocked(old_radeon_fb->obj); 487 radeon_fence_unref(&work->fence); 488 kfree(work); 489 490 return r; 491} 492 493static const struct drm_crtc_funcs radeon_crtc_funcs = { 494 .cursor_set = radeon_crtc_cursor_set, 495 .cursor_move = radeon_crtc_cursor_move, 496 .gamma_set = radeon_crtc_gamma_set, 497 .set_config = drm_crtc_helper_set_config, 498 .destroy = radeon_crtc_destroy, 499 .page_flip = radeon_crtc_page_flip, 500}; 501 502static void radeon_crtc_init(struct drm_device *dev, int index) 503{ 504 struct radeon_device *rdev = dev->dev_private; 505 struct radeon_crtc *radeon_crtc; 506 int i; 507 508 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 509 if (radeon_crtc == NULL) 510 return; 511 512 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); 513 514 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); 515 radeon_crtc->crtc_id = index; 516 rdev->mode_info.crtcs[index] = radeon_crtc; 517 518#if 0 519 radeon_crtc->mode_set.crtc = &radeon_crtc->base; 520 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); 521 radeon_crtc->mode_set.num_connectors = 0; 522#endif 523 524 for (i = 0; i < 256; i++) { 525 radeon_crtc->lut_r[i] = i << 2; 526 radeon_crtc->lut_g[i] = i << 2; 527 radeon_crtc->lut_b[i] = i << 2; 528 } 529 530 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) 531 radeon_atombios_init_crtc(dev, radeon_crtc); 532 else 533 radeon_legacy_init_crtc(dev, radeon_crtc); 534} 535 536static const char *encoder_names[37] = { 537 "NONE", 538 "INTERNAL_LVDS", 539 "INTERNAL_TMDS1", 540 "INTERNAL_TMDS2", 541 "INTERNAL_DAC1", 542 "INTERNAL_DAC2", 543 "INTERNAL_SDVOA", 544 "INTERNAL_SDVOB", 545 "SI170B", 546 "CH7303", 547 "CH7301", 548 "INTERNAL_DVO1", 549 "EXTERNAL_SDVOA", 550 "EXTERNAL_SDVOB", 551 "TITFP513", 552 "INTERNAL_LVTM1", 553 "VT1623", 554 "HDMI_SI1930", 555 "HDMI_INTERNAL", 556 "INTERNAL_KLDSCP_TMDS1", 557 "INTERNAL_KLDSCP_DVO1", 558 "INTERNAL_KLDSCP_DAC1", 559 "INTERNAL_KLDSCP_DAC2", 560 "SI178", 561 "MVPU_FPGA", 562 "INTERNAL_DDI", 563 "VT1625", 564 "HDMI_SI1932", 565 "DP_AN9801", 566 "DP_DP501", 567 "INTERNAL_UNIPHY", 568 "INTERNAL_KLDSCP_LVTMA", 569 "INTERNAL_UNIPHY1", 570 "INTERNAL_UNIPHY2", 571 "NUTMEG", 572 "TRAVIS", 573 "INTERNAL_VCE" 574}; 575 576static const char *connector_names[15] = { 577 "Unknown", 578 "VGA", 579 "DVI-I", 580 "DVI-D", 581 "DVI-A", 582 "Composite", 583 "S-video", 584 "LVDS", 585 "Component", 586 "DIN", 587 "DisplayPort", 588 "HDMI-A", 589 "HDMI-B", 590 "TV", 591 "eDP", 592}; 593 594static const char *hpd_names[6] = { 595 "HPD1", 596 "HPD2", 597 "HPD3", 598 "HPD4", 599 "HPD5", 600 "HPD6", 601}; 602 603static void radeon_print_display_setup(struct drm_device *dev) 604{ 605 struct drm_connector *connector; 606 struct radeon_connector *radeon_connector; 607 struct drm_encoder *encoder; 608 struct radeon_encoder *radeon_encoder; 609 uint32_t devices; 610 int i = 0; 611 612 DRM_INFO("Radeon Display Connectors\n"); 613 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 614 radeon_connector = to_radeon_connector(connector); 615 DRM_INFO("Connector %d:\n", i); 616 DRM_INFO(" %s\n", connector_names[connector->connector_type]); 617 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 618 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); 619 if (radeon_connector->ddc_bus) { 620 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 621 radeon_connector->ddc_bus->rec.mask_clk_reg, 622 radeon_connector->ddc_bus->rec.mask_data_reg, 623 radeon_connector->ddc_bus->rec.a_clk_reg, 624 radeon_connector->ddc_bus->rec.a_data_reg, 625 radeon_connector->ddc_bus->rec.en_clk_reg, 626 radeon_connector->ddc_bus->rec.en_data_reg, 627 radeon_connector->ddc_bus->rec.y_clk_reg, 628 radeon_connector->ddc_bus->rec.y_data_reg); 629 if (radeon_connector->router.ddc_valid) 630 DRM_INFO(" DDC Router 0x%x/0x%x\n", 631 radeon_connector->router.ddc_mux_control_pin, 632 radeon_connector->router.ddc_mux_state); 633 if (radeon_connector->router.cd_valid) 634 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 635 radeon_connector->router.cd_mux_control_pin, 636 radeon_connector->router.cd_mux_state); 637 } else { 638 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 639 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 640 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 641 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 642 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 643 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 644 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 645 } 646 DRM_INFO(" Encoders:\n"); 647 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 648 radeon_encoder = to_radeon_encoder(encoder); 649 devices = radeon_encoder->devices & radeon_connector->devices; 650 if (devices) { 651 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 652 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); 653 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 654 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); 655 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 656 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); 657 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 658 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); 659 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 660 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); 661 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 662 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); 663 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 664 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); 665 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 666 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); 667 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 668 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); 669 if (devices & ATOM_DEVICE_TV1_SUPPORT) 670 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); 671 if (devices & ATOM_DEVICE_CV_SUPPORT) 672 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); 673 } 674 } 675 i++; 676 } 677} 678 679static bool radeon_setup_enc_conn(struct drm_device *dev) 680{ 681 struct radeon_device *rdev = dev->dev_private; 682 bool ret = false; 683 684 if (rdev->bios) { 685 if (rdev->is_atom_bios) { 686 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); 687 if (ret == false) 688 ret = radeon_get_atom_connector_info_from_object_table(dev); 689 } else { 690 ret = radeon_get_legacy_connector_info_from_bios(dev); 691 if (ret == false) 692 ret = radeon_get_legacy_connector_info_from_table(dev); 693 } 694 } else { 695 if (!ASIC_IS_AVIVO(rdev)) 696 ret = radeon_get_legacy_connector_info_from_table(dev); 697 } 698 if (ret) { 699 radeon_setup_encoder_clones(dev); 700 radeon_print_display_setup(dev); 701 } 702 703 return ret; 704} 705 706int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) 707{ 708 struct drm_device *dev = radeon_connector->base.dev; 709 struct radeon_device *rdev = dev->dev_private; 710 int ret = 0; 711 712 /* on hw with routers, select right port */ 713 if (radeon_connector->router.ddc_valid) 714 radeon_router_select_ddc_port(radeon_connector); 715 716 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 717 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) || 718 (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) != 719 ENCODER_OBJECT_ID_NONE)) { 720 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 721 722 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 723 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus) 724 radeon_connector->edid = drm_get_edid(&radeon_connector->base, 725 &dig->dp_i2c_bus->adapter); 726 else if (radeon_connector->ddc_bus && !radeon_connector->edid) 727 radeon_connector->edid = drm_get_edid(&radeon_connector->base, 728 &radeon_connector->ddc_bus->adapter); 729 } else { 730 if (radeon_connector->ddc_bus && !radeon_connector->edid) 731 radeon_connector->edid = drm_get_edid(&radeon_connector->base, 732 &radeon_connector->ddc_bus->adapter); 733 } 734 735 if (!radeon_connector->edid) { 736 if (rdev->is_atom_bios) { 737 /* some laptops provide a hardcoded edid in rom for LCDs */ 738 if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) || 739 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP))) 740 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); 741 } else 742 /* some servers provide a hardcoded edid in rom for KVMs */ 743 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); 744 } 745 if (radeon_connector->edid) { 746 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); 747 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); 748 return ret; 749 } 750 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); 751 return 0; 752} 753 754/* avivo */ 755static void avivo_get_fb_div(struct radeon_pll *pll, 756 u32 target_clock, 757 u32 post_div, 758 u32 ref_div, 759 u32 *fb_div, 760 u32 *frac_fb_div) 761{ 762 u32 tmp = post_div * ref_div; 763 764 tmp *= target_clock; 765 *fb_div = tmp / pll->reference_freq; 766 *frac_fb_div = tmp % pll->reference_freq; 767 768 if (*fb_div > pll->max_feedback_div) 769 *fb_div = pll->max_feedback_div; 770 else if (*fb_div < pll->min_feedback_div) 771 *fb_div = pll->min_feedback_div; 772} 773 774static u32 avivo_get_post_div(struct radeon_pll *pll, 775 u32 target_clock) 776{ 777 u32 vco, post_div, tmp; 778 779 if (pll->flags & RADEON_PLL_USE_POST_DIV) 780 return pll->post_div; 781 782 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) { 783 if (pll->flags & RADEON_PLL_IS_LCD) 784 vco = pll->lcd_pll_out_min; 785 else 786 vco = pll->pll_out_min; 787 } else { 788 if (pll->flags & RADEON_PLL_IS_LCD) 789 vco = pll->lcd_pll_out_max; 790 else 791 vco = pll->pll_out_max; 792 } 793 794 post_div = vco / target_clock; 795 tmp = vco % target_clock; 796 797 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) { 798 if (tmp) 799 post_div++; 800 } else { 801 if (!tmp) 802 post_div--; 803 } 804 805 if (post_div > pll->max_post_div) 806 post_div = pll->max_post_div; 807 else if (post_div < pll->min_post_div) 808 post_div = pll->min_post_div; 809 810 return post_div; 811} 812 813#define MAX_TOLERANCE 10 814 815void radeon_compute_pll_avivo(struct radeon_pll *pll, 816 u32 freq, 817 u32 *dot_clock_p, 818 u32 *fb_div_p, 819 u32 *frac_fb_div_p, 820 u32 *ref_div_p, 821 u32 *post_div_p) 822{ 823 u32 target_clock = freq / 10; 824 u32 post_div = avivo_get_post_div(pll, target_clock); 825 u32 ref_div = pll->min_ref_div; 826 u32 fb_div = 0, frac_fb_div = 0, tmp; 827 828 if (pll->flags & RADEON_PLL_USE_REF_DIV) 829 ref_div = pll->reference_div; 830 831 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 832 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div); 833 frac_fb_div = (100 * frac_fb_div) / pll->reference_freq; 834 if (frac_fb_div >= 5) { 835 frac_fb_div -= 5; 836 frac_fb_div = frac_fb_div / 10; 837 frac_fb_div++; 838 } 839 if (frac_fb_div >= 10) { 840 fb_div++; 841 frac_fb_div = 0; 842 } 843 } else { 844 while (ref_div <= pll->max_ref_div) { 845 avivo_get_fb_div(pll, target_clock, post_div, ref_div, 846 &fb_div, &frac_fb_div); 847 if (frac_fb_div >= (pll->reference_freq / 2)) 848 fb_div++; 849 frac_fb_div = 0; 850 tmp = (pll->reference_freq * fb_div) / (post_div * ref_div); 851 tmp = (tmp * 10000) / target_clock; 852 853 if (tmp > (10000 + MAX_TOLERANCE)) 854 ref_div++; 855 else if (tmp >= (10000 - MAX_TOLERANCE)) 856 break; 857 else 858 ref_div++; 859 } 860 } 861 862 *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) / 863 (ref_div * post_div * 10); 864 *fb_div_p = fb_div; 865 *frac_fb_div_p = frac_fb_div; 866 *ref_div_p = ref_div; 867 *post_div_p = post_div; 868 DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n", 869 *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div); 870} 871 872/* pre-avivo */ 873static inline uint32_t radeon_div(uint64_t n, uint32_t d) 874{ 875 uint64_t mod; 876 877 n += d / 2; 878 879 mod = do_div(n, d); 880 return n; 881} 882 883void radeon_compute_pll_legacy(struct radeon_pll *pll, 884 uint64_t freq, 885 uint32_t *dot_clock_p, 886 uint32_t *fb_div_p, 887 uint32_t *frac_fb_div_p, 888 uint32_t *ref_div_p, 889 uint32_t *post_div_p) 890{ 891 uint32_t min_ref_div = pll->min_ref_div; 892 uint32_t max_ref_div = pll->max_ref_div; 893 uint32_t min_post_div = pll->min_post_div; 894 uint32_t max_post_div = pll->max_post_div; 895 uint32_t min_fractional_feed_div = 0; 896 uint32_t max_fractional_feed_div = 0; 897 uint32_t best_vco = pll->best_vco; 898 uint32_t best_post_div = 1; 899 uint32_t best_ref_div = 1; 900 uint32_t best_feedback_div = 1; 901 uint32_t best_frac_feedback_div = 0; 902 uint32_t best_freq = -1; 903 uint32_t best_error = 0xffffffff; 904 uint32_t best_vco_diff = 1; 905 uint32_t post_div; 906 u32 pll_out_min, pll_out_max; 907 908 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); 909 freq = freq * 1000; 910 911 if (pll->flags & RADEON_PLL_IS_LCD) { 912 pll_out_min = pll->lcd_pll_out_min; 913 pll_out_max = pll->lcd_pll_out_max; 914 } else { 915 pll_out_min = pll->pll_out_min; 916 pll_out_max = pll->pll_out_max; 917 } 918 919 if (pll_out_min > 64800) 920 pll_out_min = 64800; 921 922 if (pll->flags & RADEON_PLL_USE_REF_DIV) 923 min_ref_div = max_ref_div = pll->reference_div; 924 else { 925 while (min_ref_div < max_ref_div-1) { 926 uint32_t mid = (min_ref_div + max_ref_div) / 2; 927 uint32_t pll_in = pll->reference_freq / mid; 928 if (pll_in < pll->pll_in_min) 929 max_ref_div = mid; 930 else if (pll_in > pll->pll_in_max) 931 min_ref_div = mid; 932 else 933 break; 934 } 935 } 936 937 if (pll->flags & RADEON_PLL_USE_POST_DIV) 938 min_post_div = max_post_div = pll->post_div; 939 940 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 941 min_fractional_feed_div = pll->min_frac_feedback_div; 942 max_fractional_feed_div = pll->max_frac_feedback_div; 943 } 944 945 for (post_div = max_post_div; post_div >= min_post_div; --post_div) { 946 uint32_t ref_div; 947 948 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 949 continue; 950 951 /* legacy radeons only have a few post_divs */ 952 if (pll->flags & RADEON_PLL_LEGACY) { 953 if ((post_div == 5) || 954 (post_div == 7) || 955 (post_div == 9) || 956 (post_div == 10) || 957 (post_div == 11) || 958 (post_div == 13) || 959 (post_div == 14) || 960 (post_div == 15)) 961 continue; 962 } 963 964 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { 965 uint32_t feedback_div, current_freq = 0, error, vco_diff; 966 uint32_t pll_in = pll->reference_freq / ref_div; 967 uint32_t min_feed_div = pll->min_feedback_div; 968 uint32_t max_feed_div = pll->max_feedback_div + 1; 969 970 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) 971 continue; 972 973 while (min_feed_div < max_feed_div) { 974 uint32_t vco; 975 uint32_t min_frac_feed_div = min_fractional_feed_div; 976 uint32_t max_frac_feed_div = max_fractional_feed_div + 1; 977 uint32_t frac_feedback_div; 978 uint64_t tmp; 979 980 feedback_div = (min_feed_div + max_feed_div) / 2; 981 982 tmp = (uint64_t)pll->reference_freq * feedback_div; 983 vco = radeon_div(tmp, ref_div); 984 985 if (vco < pll_out_min) { 986 min_feed_div = feedback_div + 1; 987 continue; 988 } else if (vco > pll_out_max) { 989 max_feed_div = feedback_div; 990 continue; 991 } 992 993 while (min_frac_feed_div < max_frac_feed_div) { 994 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; 995 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; 996 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 997 current_freq = radeon_div(tmp, ref_div * post_div); 998 999 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 1000 if (freq < current_freq) 1001 error = 0xffffffff; 1002 else 1003 error = freq - current_freq; 1004 } else 1005 error = abs(current_freq - freq); 1006 vco_diff = abs(vco - best_vco); 1007 1008 if ((best_vco == 0 && error < best_error) || 1009 (best_vco != 0 && 1010 ((best_error > 100 && error < best_error - 100) || 1011 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { 1012 best_post_div = post_div; 1013 best_ref_div = ref_div; 1014 best_feedback_div = feedback_div; 1015 best_frac_feedback_div = frac_feedback_div; 1016 best_freq = current_freq; 1017 best_error = error; 1018 best_vco_diff = vco_diff; 1019 } else if (current_freq == freq) { 1020 if (best_freq == -1) { 1021 best_post_div = post_div; 1022 best_ref_div = ref_div; 1023 best_feedback_div = feedback_div; 1024 best_frac_feedback_div = frac_feedback_div; 1025 best_freq = current_freq; 1026 best_error = error; 1027 best_vco_diff = vco_diff; 1028 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 1029 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 1030 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 1031 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 1032 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 1033 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 1034 best_post_div = post_div; 1035 best_ref_div = ref_div; 1036 best_feedback_div = feedback_div; 1037 best_frac_feedback_div = frac_feedback_div; 1038 best_freq = current_freq; 1039 best_error = error; 1040 best_vco_diff = vco_diff; 1041 } 1042 } 1043 if (current_freq < freq) 1044 min_frac_feed_div = frac_feedback_div + 1; 1045 else 1046 max_frac_feed_div = frac_feedback_div; 1047 } 1048 if (current_freq < freq) 1049 min_feed_div = feedback_div + 1; 1050 else 1051 max_feed_div = feedback_div; 1052 } 1053 } 1054 } 1055 1056 *dot_clock_p = best_freq / 10000; 1057 *fb_div_p = best_feedback_div; 1058 *frac_fb_div_p = best_frac_feedback_div; 1059 *ref_div_p = best_ref_div; 1060 *post_div_p = best_post_div; 1061 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1062 (long long)freq, 1063 best_freq / 1000, best_feedback_div, best_frac_feedback_div, 1064 best_ref_div, best_post_div); 1065 1066} 1067 1068static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) 1069{ 1070 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1071 1072 if (radeon_fb->obj) { 1073 drm_gem_object_unreference_unlocked(radeon_fb->obj); 1074 } 1075 drm_framebuffer_cleanup(fb); 1076 kfree(radeon_fb); 1077} 1078 1079static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, 1080 struct drm_file *file_priv, 1081 unsigned int *handle) 1082{ 1083 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1084 1085 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); 1086} 1087 1088static const struct drm_framebuffer_funcs radeon_fb_funcs = { 1089 .destroy = radeon_user_framebuffer_destroy, 1090 .create_handle = radeon_user_framebuffer_create_handle, 1091}; 1092 1093int 1094radeon_framebuffer_init(struct drm_device *dev, 1095 struct radeon_framebuffer *rfb, 1096 struct drm_mode_fb_cmd2 *mode_cmd, 1097 struct drm_gem_object *obj) 1098{ 1099 int ret; 1100 rfb->obj = obj; 1101 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); 1102 if (ret) { 1103 rfb->obj = NULL; 1104 return ret; 1105 } 1106 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); 1107 return 0; 1108} 1109 1110static struct drm_framebuffer * 1111radeon_user_framebuffer_create(struct drm_device *dev, 1112 struct drm_file *file_priv, 1113 struct drm_mode_fb_cmd2 *mode_cmd) 1114{ 1115 struct drm_gem_object *obj; 1116 struct radeon_framebuffer *radeon_fb; 1117 int ret; 1118 1119 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]); 1120 if (obj == NULL) { 1121 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 1122 "can't create framebuffer\n", mode_cmd->handles[0]); 1123 return ERR_PTR(-ENOENT); 1124 } 1125 1126 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); 1127 if (radeon_fb == NULL) 1128 return ERR_PTR(-ENOMEM); 1129 1130 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); 1131 if (ret) { 1132 kfree(radeon_fb); 1133 drm_gem_object_unreference_unlocked(obj); 1134 return NULL; 1135 } 1136 1137 return &radeon_fb->base; 1138} 1139 1140static void radeon_output_poll_changed(struct drm_device *dev) 1141{ 1142 struct radeon_device *rdev = dev->dev_private; 1143 radeon_fb_output_poll_changed(rdev); 1144} 1145 1146static const struct drm_mode_config_funcs radeon_mode_funcs = { 1147 .fb_create = radeon_user_framebuffer_create, 1148 .output_poll_changed = radeon_output_poll_changed 1149}; 1150 1151static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = 1152{ { 0, "driver" }, 1153 { 1, "bios" }, 1154}; 1155 1156static struct drm_prop_enum_list radeon_tv_std_enum_list[] = 1157{ { TV_STD_NTSC, "ntsc" }, 1158 { TV_STD_PAL, "pal" }, 1159 { TV_STD_PAL_M, "pal-m" }, 1160 { TV_STD_PAL_60, "pal-60" }, 1161 { TV_STD_NTSC_J, "ntsc-j" }, 1162 { TV_STD_SCART_PAL, "scart-pal" }, 1163 { TV_STD_PAL_CN, "pal-cn" }, 1164 { TV_STD_SECAM, "secam" }, 1165}; 1166 1167static struct drm_prop_enum_list radeon_underscan_enum_list[] = 1168{ { UNDERSCAN_OFF, "off" }, 1169 { UNDERSCAN_ON, "on" }, 1170 { UNDERSCAN_AUTO, "auto" }, 1171}; 1172 1173static int radeon_modeset_create_props(struct radeon_device *rdev) 1174{ 1175 int sz; 1176 1177 if (rdev->is_atom_bios) { 1178 rdev->mode_info.coherent_mode_property = 1179 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); 1180 if (!rdev->mode_info.coherent_mode_property) 1181 return -ENOMEM; 1182 } 1183 1184 if (!ASIC_IS_AVIVO(rdev)) { 1185 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); 1186 rdev->mode_info.tmds_pll_property = 1187 drm_property_create_enum(rdev->ddev, 0, 1188 "tmds_pll", 1189 radeon_tmds_pll_enum_list, sz); 1190 } 1191 1192 rdev->mode_info.load_detect_property = 1193 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); 1194 if (!rdev->mode_info.load_detect_property) 1195 return -ENOMEM; 1196 1197 drm_mode_create_scaling_mode_property(rdev->ddev); 1198 1199 sz = ARRAY_SIZE(radeon_tv_std_enum_list); 1200 rdev->mode_info.tv_std_property = 1201 drm_property_create_enum(rdev->ddev, 0, 1202 "tv standard", 1203 radeon_tv_std_enum_list, sz); 1204 1205 sz = ARRAY_SIZE(radeon_underscan_enum_list); 1206 rdev->mode_info.underscan_property = 1207 drm_property_create_enum(rdev->ddev, 0, 1208 "underscan", 1209 radeon_underscan_enum_list, sz); 1210 1211 rdev->mode_info.underscan_hborder_property = 1212 drm_property_create_range(rdev->ddev, 0, 1213 "underscan hborder", 0, 128); 1214 if (!rdev->mode_info.underscan_hborder_property) 1215 return -ENOMEM; 1216 1217 rdev->mode_info.underscan_vborder_property = 1218 drm_property_create_range(rdev->ddev, 0, 1219 "underscan vborder", 0, 128); 1220 if (!rdev->mode_info.underscan_vborder_property) 1221 return -ENOMEM; 1222 1223 return 0; 1224} 1225 1226void radeon_update_display_priority(struct radeon_device *rdev) 1227{ 1228 /* adjustment options for the display watermarks */ 1229 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { 1230 /* set display priority to high for r3xx, rv515 chips 1231 * this avoids flickering due to underflow to the 1232 * display controllers during heavy acceleration. 1233 * Don't force high on rs4xx igp chips as it seems to 1234 * affect the sound card. See kernel bug 15982. 1235 */ 1236 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && 1237 !(rdev->flags & RADEON_IS_IGP)) 1238 rdev->disp_priority = 2; 1239 else 1240 rdev->disp_priority = 0; 1241 } else 1242 rdev->disp_priority = radeon_disp_priority; 1243 1244} 1245 1246int radeon_modeset_init(struct radeon_device *rdev) 1247{ 1248 int i; 1249 int ret; 1250 1251 drm_mode_config_init(rdev->ddev); 1252 rdev->mode_info.mode_config_initialized = true; 1253 1254 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs; 1255 1256 if (ASIC_IS_DCE5(rdev)) { 1257 rdev->ddev->mode_config.max_width = 16384; 1258 rdev->ddev->mode_config.max_height = 16384; 1259 } else if (ASIC_IS_AVIVO(rdev)) { 1260 rdev->ddev->mode_config.max_width = 8192; 1261 rdev->ddev->mode_config.max_height = 8192; 1262 } else { 1263 rdev->ddev->mode_config.max_width = 4096; 1264 rdev->ddev->mode_config.max_height = 4096; 1265 } 1266 1267 rdev->ddev->mode_config.preferred_depth = 24; 1268 rdev->ddev->mode_config.prefer_shadow = 1; 1269 1270 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; 1271 1272 ret = radeon_modeset_create_props(rdev); 1273 if (ret) { 1274 return ret; 1275 } 1276 1277 /* init i2c buses */ 1278 radeon_i2c_init(rdev); 1279 1280 /* check combios for a valid hardcoded EDID - Sun servers */ 1281 if (!rdev->is_atom_bios) { 1282 /* check for hardcoded EDID in BIOS */ 1283 radeon_combios_check_hardcoded_edid(rdev); 1284 } 1285 1286 /* allocate crtcs */ 1287 for (i = 0; i < rdev->num_crtc; i++) { 1288 radeon_crtc_init(rdev->ddev, i); 1289 } 1290 1291 /* okay we should have all the bios connectors */ 1292 ret = radeon_setup_enc_conn(rdev->ddev); 1293 if (!ret) { 1294 return ret; 1295 } 1296 1297 /* init dig PHYs, disp eng pll */ 1298 if (rdev->is_atom_bios) { 1299 radeon_atom_encoder_init(rdev); 1300 radeon_atom_disp_eng_pll_init(rdev); 1301 } 1302 1303 /* initialize hpd */ 1304 radeon_hpd_init(rdev); 1305 1306 /* Initialize power management */ 1307 radeon_pm_init(rdev); 1308 1309 radeon_fbdev_init(rdev); 1310 drm_kms_helper_poll_init(rdev->ddev); 1311 1312 return 0; 1313} 1314 1315void radeon_modeset_fini(struct radeon_device *rdev) 1316{ 1317 radeon_fbdev_fini(rdev); 1318 kfree(rdev->mode_info.bios_hardcoded_edid); 1319 radeon_pm_fini(rdev); 1320 1321 if (rdev->mode_info.mode_config_initialized) { 1322 drm_kms_helper_poll_fini(rdev->ddev); 1323 radeon_hpd_fini(rdev); 1324 drm_mode_config_cleanup(rdev->ddev); 1325 rdev->mode_info.mode_config_initialized = false; 1326 } 1327 /* free i2c buses */ 1328 radeon_i2c_fini(rdev); 1329} 1330 1331static bool is_hdtv_mode(struct drm_display_mode *mode) 1332{ 1333 /* try and guess if this is a tv or a monitor */ 1334 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 1335 (mode->vdisplay == 576) || /* 576p */ 1336 (mode->vdisplay == 720) || /* 720p */ 1337 (mode->vdisplay == 1080)) /* 1080p */ 1338 return true; 1339 else 1340 return false; 1341} 1342 1343bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1344 struct drm_display_mode *mode, 1345 struct drm_display_mode *adjusted_mode) 1346{ 1347 struct drm_device *dev = crtc->dev; 1348 struct radeon_device *rdev = dev->dev_private; 1349 struct drm_encoder *encoder; 1350 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1351 struct radeon_encoder *radeon_encoder; 1352 struct drm_connector *connector; 1353 struct radeon_connector *radeon_connector; 1354 bool first = true; 1355 u32 src_v = 1, dst_v = 1; 1356 u32 src_h = 1, dst_h = 1; 1357 1358 radeon_crtc->h_border = 0; 1359 radeon_crtc->v_border = 0; 1360 1361 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1362 if (encoder->crtc != crtc) 1363 continue; 1364 radeon_encoder = to_radeon_encoder(encoder); 1365 connector = radeon_get_connector_for_encoder(encoder); 1366 radeon_connector = to_radeon_connector(connector); 1367 1368 if (first) { 1369 /* set scaling */ 1370 if (radeon_encoder->rmx_type == RMX_OFF) 1371 radeon_crtc->rmx_type = RMX_OFF; 1372 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || 1373 mode->vdisplay < radeon_encoder->native_mode.vdisplay) 1374 radeon_crtc->rmx_type = radeon_encoder->rmx_type; 1375 else 1376 radeon_crtc->rmx_type = RMX_OFF; 1377 /* copy native mode */ 1378 memcpy(&radeon_crtc->native_mode, 1379 &radeon_encoder->native_mode, 1380 sizeof(struct drm_display_mode)); 1381 src_v = crtc->mode.vdisplay; 1382 dst_v = radeon_crtc->native_mode.vdisplay; 1383 src_h = crtc->mode.hdisplay; 1384 dst_h = radeon_crtc->native_mode.hdisplay; 1385 1386 /* fix up for overscan on hdmi */ 1387 if (ASIC_IS_AVIVO(rdev) && 1388 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 1389 ((radeon_encoder->underscan_type == UNDERSCAN_ON) || 1390 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && 1391 drm_detect_hdmi_monitor(radeon_connector->edid) && 1392 is_hdtv_mode(mode)))) { 1393 if (radeon_encoder->underscan_hborder != 0) 1394 radeon_crtc->h_border = radeon_encoder->underscan_hborder; 1395 else 1396 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; 1397 if (radeon_encoder->underscan_vborder != 0) 1398 radeon_crtc->v_border = radeon_encoder->underscan_vborder; 1399 else 1400 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; 1401 radeon_crtc->rmx_type = RMX_FULL; 1402 src_v = crtc->mode.vdisplay; 1403 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); 1404 src_h = crtc->mode.hdisplay; 1405 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); 1406 } 1407 first = false; 1408 } else { 1409 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 1410 /* WARNING: Right now this can't happen but 1411 * in the future we need to check that scaling 1412 * are consistent across different encoder 1413 * (ie all encoder can work with the same 1414 * scaling). 1415 */ 1416 DRM_ERROR("Scaling not consistent across encoder.\n"); 1417 return false; 1418 } 1419 } 1420 } 1421 if (radeon_crtc->rmx_type != RMX_OFF) { 1422 fixed20_12 a, b; 1423 a.full = dfixed_const(src_v); 1424 b.full = dfixed_const(dst_v); 1425 radeon_crtc->vsc.full = dfixed_div(a, b); 1426 a.full = dfixed_const(src_h); 1427 b.full = dfixed_const(dst_h); 1428 radeon_crtc->hsc.full = dfixed_div(a, b); 1429 } else { 1430 radeon_crtc->vsc.full = dfixed_const(1); 1431 radeon_crtc->hsc.full = dfixed_const(1); 1432 } 1433 return true; 1434} 1435 1436/* 1437 * Retrieve current video scanout position of crtc on a given gpu. 1438 * 1439 * \param dev Device to query. 1440 * \param crtc Crtc to query. 1441 * \param *vpos Location where vertical scanout position should be stored. 1442 * \param *hpos Location where horizontal scanout position should go. 1443 * 1444 * Returns vpos as a positive number while in active scanout area. 1445 * Returns vpos as a negative number inside vblank, counting the number 1446 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 1447 * until start of active scanout / end of vblank." 1448 * 1449 * \return Flags, or'ed together as follows: 1450 * 1451 * DRM_SCANOUTPOS_VALID = Query successful. 1452 * DRM_SCANOUTPOS_INVBL = Inside vblank. 1453 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1454 * this flag means that returned position may be offset by a constant but 1455 * unknown small number of scanlines wrt. real scanout position. 1456 * 1457 */ 1458int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos) 1459{ 1460 u32 stat_crtc = 0, vbl = 0, position = 0; 1461 int vbl_start, vbl_end, vtotal, ret = 0; 1462 bool in_vbl = true; 1463 1464 struct radeon_device *rdev = dev->dev_private; 1465 1466 if (ASIC_IS_DCE4(rdev)) { 1467 if (crtc == 0) { 1468 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1469 EVERGREEN_CRTC0_REGISTER_OFFSET); 1470 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1471 EVERGREEN_CRTC0_REGISTER_OFFSET); 1472 ret |= DRM_SCANOUTPOS_VALID; 1473 } 1474 if (crtc == 1) { 1475 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1476 EVERGREEN_CRTC1_REGISTER_OFFSET); 1477 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1478 EVERGREEN_CRTC1_REGISTER_OFFSET); 1479 ret |= DRM_SCANOUTPOS_VALID; 1480 } 1481 if (crtc == 2) { 1482 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1483 EVERGREEN_CRTC2_REGISTER_OFFSET); 1484 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1485 EVERGREEN_CRTC2_REGISTER_OFFSET); 1486 ret |= DRM_SCANOUTPOS_VALID; 1487 } 1488 if (crtc == 3) { 1489 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1490 EVERGREEN_CRTC3_REGISTER_OFFSET); 1491 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1492 EVERGREEN_CRTC3_REGISTER_OFFSET); 1493 ret |= DRM_SCANOUTPOS_VALID; 1494 } 1495 if (crtc == 4) { 1496 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1497 EVERGREEN_CRTC4_REGISTER_OFFSET); 1498 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1499 EVERGREEN_CRTC4_REGISTER_OFFSET); 1500 ret |= DRM_SCANOUTPOS_VALID; 1501 } 1502 if (crtc == 5) { 1503 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1504 EVERGREEN_CRTC5_REGISTER_OFFSET); 1505 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1506 EVERGREEN_CRTC5_REGISTER_OFFSET); 1507 ret |= DRM_SCANOUTPOS_VALID; 1508 } 1509 } else if (ASIC_IS_AVIVO(rdev)) { 1510 if (crtc == 0) { 1511 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); 1512 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); 1513 ret |= DRM_SCANOUTPOS_VALID; 1514 } 1515 if (crtc == 1) { 1516 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); 1517 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); 1518 ret |= DRM_SCANOUTPOS_VALID; 1519 } 1520 } else { 1521 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ 1522 if (crtc == 0) { 1523 /* Assume vbl_end == 0, get vbl_start from 1524 * upper 16 bits. 1525 */ 1526 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & 1527 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1528 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ 1529 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1530 stat_crtc = RREG32(RADEON_CRTC_STATUS); 1531 if (!(stat_crtc & 1)) 1532 in_vbl = false; 1533 1534 ret |= DRM_SCANOUTPOS_VALID; 1535 } 1536 if (crtc == 1) { 1537 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & 1538 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1539 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1540 stat_crtc = RREG32(RADEON_CRTC2_STATUS); 1541 if (!(stat_crtc & 1)) 1542 in_vbl = false; 1543 1544 ret |= DRM_SCANOUTPOS_VALID; 1545 } 1546 } 1547 1548 /* Decode into vertical and horizontal scanout position. */ 1549 *vpos = position & 0x1fff; 1550 *hpos = (position >> 16) & 0x1fff; 1551 1552 /* Valid vblank area boundaries from gpu retrieved? */ 1553 if (vbl > 0) { 1554 /* Yes: Decode. */ 1555 ret |= DRM_SCANOUTPOS_ACCURATE; 1556 vbl_start = vbl & 0x1fff; 1557 vbl_end = (vbl >> 16) & 0x1fff; 1558 } 1559 else { 1560 /* No: Fake something reasonable which gives at least ok results. */ 1561 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay; 1562 vbl_end = 0; 1563 } 1564 1565 /* Test scanout position against vblank region. */ 1566 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 1567 in_vbl = false; 1568 1569 /* Check if inside vblank area and apply corrective offsets: 1570 * vpos will then be >=0 in video scanout area, but negative 1571 * within vblank area, counting down the number of lines until 1572 * start of scanout. 1573 */ 1574 1575 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 1576 if (in_vbl && (*vpos >= vbl_start)) { 1577 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal; 1578 *vpos = *vpos - vtotal; 1579 } 1580 1581 /* Correct for shifted end of vbl at vbl_end. */ 1582 *vpos = *vpos - vbl_end; 1583 1584 /* In vblank? */ 1585 if (in_vbl) 1586 ret |= DRM_SCANOUTPOS_INVBL; 1587 1588 return ret; 1589} 1590