1/* 2 * Driver for the i2c controller on the Marvell line of host bridges 3 * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family). 4 * 5 * Author: Mark A. Greer <mgreer@mvista.com> 6 * 7 * 2005 (c) MontaVista, Software, Inc. This file is licensed under 8 * the terms of the GNU General Public License version 2. This program 9 * is licensed "as is" without any warranty of any kind, whether express 10 * or implied. 11 */ 12#include <linux/kernel.h> 13#include <linux/slab.h> 14#include <linux/module.h> 15#include <linux/spinlock.h> 16#include <linux/i2c.h> 17#include <linux/interrupt.h> 18#include <linux/mv643xx_i2c.h> 19#include <linux/platform_device.h> 20#include <linux/io.h> 21 22/* Register defines */ 23#define MV64XXX_I2C_REG_SLAVE_ADDR 0x00 24#define MV64XXX_I2C_REG_DATA 0x04 25#define MV64XXX_I2C_REG_CONTROL 0x08 26#define MV64XXX_I2C_REG_STATUS 0x0c 27#define MV64XXX_I2C_REG_BAUD 0x0c 28#define MV64XXX_I2C_REG_EXT_SLAVE_ADDR 0x10 29#define MV64XXX_I2C_REG_SOFT_RESET 0x1c 30 31#define MV64XXX_I2C_REG_CONTROL_ACK 0x00000004 32#define MV64XXX_I2C_REG_CONTROL_IFLG 0x00000008 33#define MV64XXX_I2C_REG_CONTROL_STOP 0x00000010 34#define MV64XXX_I2C_REG_CONTROL_START 0x00000020 35#define MV64XXX_I2C_REG_CONTROL_TWSIEN 0x00000040 36#define MV64XXX_I2C_REG_CONTROL_INTEN 0x00000080 37 38/* Ctlr status values */ 39#define MV64XXX_I2C_STATUS_BUS_ERR 0x00 40#define MV64XXX_I2C_STATUS_MAST_START 0x08 41#define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10 42#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18 43#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20 44#define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28 45#define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30 46#define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38 47#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40 48#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48 49#define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50 50#define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58 51#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0 52#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8 53#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0 54#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8 55#define MV64XXX_I2C_STATUS_NO_STATUS 0xf8 56 57/* Driver states */ 58enum { 59 MV64XXX_I2C_STATE_INVALID, 60 MV64XXX_I2C_STATE_IDLE, 61 MV64XXX_I2C_STATE_WAITING_FOR_START_COND, 62 MV64XXX_I2C_STATE_WAITING_FOR_RESTART, 63 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK, 64 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK, 65 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK, 66 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA, 67}; 68 69/* Driver actions */ 70enum { 71 MV64XXX_I2C_ACTION_INVALID, 72 MV64XXX_I2C_ACTION_CONTINUE, 73 MV64XXX_I2C_ACTION_SEND_START, 74 MV64XXX_I2C_ACTION_SEND_RESTART, 75 MV64XXX_I2C_ACTION_SEND_ADDR_1, 76 MV64XXX_I2C_ACTION_SEND_ADDR_2, 77 MV64XXX_I2C_ACTION_SEND_DATA, 78 MV64XXX_I2C_ACTION_RCV_DATA, 79 MV64XXX_I2C_ACTION_RCV_DATA_STOP, 80 MV64XXX_I2C_ACTION_SEND_STOP, 81}; 82 83struct mv64xxx_i2c_data { 84 int irq; 85 u32 state; 86 u32 action; 87 u32 aborting; 88 u32 cntl_bits; 89 void __iomem *reg_base; 90 u32 reg_base_p; 91 u32 reg_size; 92 u32 addr1; 93 u32 addr2; 94 u32 bytes_left; 95 u32 byte_posn; 96 u32 send_stop; 97 u32 block; 98 int rc; 99 u32 freq_m; 100 u32 freq_n; 101 wait_queue_head_t waitq; 102 spinlock_t lock; 103 struct i2c_msg *msg; 104 struct i2c_adapter adapter; 105}; 106 107/* 108 ***************************************************************************** 109 * 110 * Finite State Machine & Interrupt Routines 111 * 112 ***************************************************************************** 113 */ 114 115/* Reset hardware and initialize FSM */ 116static void 117mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data) 118{ 119 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SOFT_RESET); 120 writel((((drv_data->freq_m & 0xf) << 3) | (drv_data->freq_n & 0x7)), 121 drv_data->reg_base + MV64XXX_I2C_REG_BAUD); 122 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SLAVE_ADDR); 123 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_EXT_SLAVE_ADDR); 124 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP, 125 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 126 drv_data->state = MV64XXX_I2C_STATE_IDLE; 127} 128 129static void 130mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status) 131{ 132 /* 133 * If state is idle, then this is likely the remnants of an old 134 * operation that driver has given up on or the user has killed. 135 * If so, issue the stop condition and go to idle. 136 */ 137 if (drv_data->state == MV64XXX_I2C_STATE_IDLE) { 138 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 139 return; 140 } 141 142 /* The status from the ctlr [mostly] tells us what to do next */ 143 switch (status) { 144 /* Start condition interrupt */ 145 case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */ 146 case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */ 147 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1; 148 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK; 149 break; 150 151 /* Performing a write */ 152 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */ 153 if (drv_data->msg->flags & I2C_M_TEN) { 154 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2; 155 drv_data->state = 156 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK; 157 break; 158 } 159 /* FALLTHRU */ 160 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */ 161 case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */ 162 if ((drv_data->bytes_left == 0) 163 || (drv_data->aborting 164 && (drv_data->byte_posn != 0))) { 165 if (drv_data->send_stop) { 166 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 167 drv_data->state = MV64XXX_I2C_STATE_IDLE; 168 } else { 169 drv_data->action = 170 MV64XXX_I2C_ACTION_SEND_RESTART; 171 drv_data->state = 172 MV64XXX_I2C_STATE_WAITING_FOR_RESTART; 173 } 174 } else { 175 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA; 176 drv_data->state = 177 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK; 178 drv_data->bytes_left--; 179 } 180 break; 181 182 /* Performing a read */ 183 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */ 184 if (drv_data->msg->flags & I2C_M_TEN) { 185 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2; 186 drv_data->state = 187 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK; 188 break; 189 } 190 /* FALLTHRU */ 191 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */ 192 if (drv_data->bytes_left == 0) { 193 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 194 drv_data->state = MV64XXX_I2C_STATE_IDLE; 195 break; 196 } 197 /* FALLTHRU */ 198 case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */ 199 if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK) 200 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE; 201 else { 202 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA; 203 drv_data->bytes_left--; 204 } 205 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA; 206 207 if ((drv_data->bytes_left == 1) || drv_data->aborting) 208 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK; 209 break; 210 211 case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */ 212 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP; 213 drv_data->state = MV64XXX_I2C_STATE_IDLE; 214 break; 215 216 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */ 217 case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */ 218 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */ 219 /* Doesn't seem to be a device at other end */ 220 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 221 drv_data->state = MV64XXX_I2C_STATE_IDLE; 222 drv_data->rc = -ENODEV; 223 break; 224 225 default: 226 dev_err(&drv_data->adapter.dev, 227 "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, " 228 "status: 0x%x, addr: 0x%x, flags: 0x%x\n", 229 drv_data->state, status, drv_data->msg->addr, 230 drv_data->msg->flags); 231 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 232 mv64xxx_i2c_hw_init(drv_data); 233 drv_data->rc = -EIO; 234 } 235} 236 237static void 238mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data) 239{ 240 switch(drv_data->action) { 241 case MV64XXX_I2C_ACTION_SEND_RESTART: 242 drv_data->cntl_bits |= MV64XXX_I2C_REG_CONTROL_START; 243 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN; 244 writel(drv_data->cntl_bits, 245 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 246 drv_data->block = 0; 247 wake_up_interruptible(&drv_data->waitq); 248 break; 249 250 case MV64XXX_I2C_ACTION_CONTINUE: 251 writel(drv_data->cntl_bits, 252 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 253 break; 254 255 case MV64XXX_I2C_ACTION_SEND_START: 256 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START, 257 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 258 break; 259 260 case MV64XXX_I2C_ACTION_SEND_ADDR_1: 261 writel(drv_data->addr1, 262 drv_data->reg_base + MV64XXX_I2C_REG_DATA); 263 writel(drv_data->cntl_bits, 264 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 265 break; 266 267 case MV64XXX_I2C_ACTION_SEND_ADDR_2: 268 writel(drv_data->addr2, 269 drv_data->reg_base + MV64XXX_I2C_REG_DATA); 270 writel(drv_data->cntl_bits, 271 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 272 break; 273 274 case MV64XXX_I2C_ACTION_SEND_DATA: 275 writel(drv_data->msg->buf[drv_data->byte_posn++], 276 drv_data->reg_base + MV64XXX_I2C_REG_DATA); 277 writel(drv_data->cntl_bits, 278 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 279 break; 280 281 case MV64XXX_I2C_ACTION_RCV_DATA: 282 drv_data->msg->buf[drv_data->byte_posn++] = 283 readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA); 284 writel(drv_data->cntl_bits, 285 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 286 break; 287 288 case MV64XXX_I2C_ACTION_RCV_DATA_STOP: 289 drv_data->msg->buf[drv_data->byte_posn++] = 290 readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA); 291 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN; 292 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, 293 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 294 drv_data->block = 0; 295 wake_up_interruptible(&drv_data->waitq); 296 break; 297 298 case MV64XXX_I2C_ACTION_INVALID: 299 default: 300 dev_err(&drv_data->adapter.dev, 301 "mv64xxx_i2c_do_action: Invalid action: %d\n", 302 drv_data->action); 303 drv_data->rc = -EIO; 304 /* FALLTHRU */ 305 case MV64XXX_I2C_ACTION_SEND_STOP: 306 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN; 307 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, 308 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 309 drv_data->block = 0; 310 wake_up_interruptible(&drv_data->waitq); 311 break; 312 } 313} 314 315static irqreturn_t 316mv64xxx_i2c_intr(int irq, void *dev_id) 317{ 318 struct mv64xxx_i2c_data *drv_data = dev_id; 319 unsigned long flags; 320 u32 status; 321 irqreturn_t rc = IRQ_NONE; 322 323 spin_lock_irqsave(&drv_data->lock, flags); 324 while (readl(drv_data->reg_base + MV64XXX_I2C_REG_CONTROL) & 325 MV64XXX_I2C_REG_CONTROL_IFLG) { 326 status = readl(drv_data->reg_base + MV64XXX_I2C_REG_STATUS); 327 mv64xxx_i2c_fsm(drv_data, status); 328 mv64xxx_i2c_do_action(drv_data); 329 rc = IRQ_HANDLED; 330 } 331 spin_unlock_irqrestore(&drv_data->lock, flags); 332 333 return rc; 334} 335 336/* 337 ***************************************************************************** 338 * 339 * I2C Msg Execution Routines 340 * 341 ***************************************************************************** 342 */ 343static void 344mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data, 345 struct i2c_msg *msg) 346{ 347 u32 dir = 0; 348 349 drv_data->msg = msg; 350 drv_data->byte_posn = 0; 351 drv_data->bytes_left = msg->len; 352 drv_data->aborting = 0; 353 drv_data->rc = 0; 354 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK | 355 MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN; 356 357 if (msg->flags & I2C_M_RD) 358 dir = 1; 359 360 if (msg->flags & I2C_M_TEN) { 361 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir; 362 drv_data->addr2 = (u32)msg->addr & 0xff; 363 } else { 364 drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir; 365 drv_data->addr2 = 0; 366 } 367} 368 369static void 370mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data) 371{ 372 long time_left; 373 unsigned long flags; 374 char abort = 0; 375 376 time_left = wait_event_interruptible_timeout(drv_data->waitq, 377 !drv_data->block, drv_data->adapter.timeout); 378 379 spin_lock_irqsave(&drv_data->lock, flags); 380 if (!time_left) { /* Timed out */ 381 drv_data->rc = -ETIMEDOUT; 382 abort = 1; 383 } else if (time_left < 0) { /* Interrupted/Error */ 384 drv_data->rc = time_left; /* errno value */ 385 abort = 1; 386 } 387 388 if (abort && drv_data->block) { 389 drv_data->aborting = 1; 390 spin_unlock_irqrestore(&drv_data->lock, flags); 391 392 time_left = wait_event_timeout(drv_data->waitq, 393 !drv_data->block, drv_data->adapter.timeout); 394 395 if ((time_left <= 0) && drv_data->block) { 396 drv_data->state = MV64XXX_I2C_STATE_IDLE; 397 dev_err(&drv_data->adapter.dev, 398 "mv64xxx: I2C bus locked, block: %d, " 399 "time_left: %d\n", drv_data->block, 400 (int)time_left); 401 mv64xxx_i2c_hw_init(drv_data); 402 } 403 } else 404 spin_unlock_irqrestore(&drv_data->lock, flags); 405} 406 407static int 408mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg, 409 int is_first, int is_last) 410{ 411 unsigned long flags; 412 413 spin_lock_irqsave(&drv_data->lock, flags); 414 mv64xxx_i2c_prepare_for_io(drv_data, msg); 415 416 if (unlikely(msg->flags & I2C_M_NOSTART)) { /* Skip start/addr phases */ 417 if (drv_data->msg->flags & I2C_M_RD) { 418 /* No action to do, wait for slave to send a byte */ 419 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE; 420 drv_data->state = 421 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA; 422 } else { 423 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA; 424 drv_data->state = 425 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK; 426 drv_data->bytes_left--; 427 } 428 } else { 429 if (is_first) { 430 drv_data->action = MV64XXX_I2C_ACTION_SEND_START; 431 drv_data->state = 432 MV64XXX_I2C_STATE_WAITING_FOR_START_COND; 433 } else { 434 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1; 435 drv_data->state = 436 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK; 437 } 438 } 439 440 drv_data->send_stop = is_last; 441 drv_data->block = 1; 442 mv64xxx_i2c_do_action(drv_data); 443 spin_unlock_irqrestore(&drv_data->lock, flags); 444 445 mv64xxx_i2c_wait_for_completion(drv_data); 446 return drv_data->rc; 447} 448 449/* 450 ***************************************************************************** 451 * 452 * I2C Core Support Routines (Interface to higher level I2C code) 453 * 454 ***************************************************************************** 455 */ 456static u32 457mv64xxx_i2c_functionality(struct i2c_adapter *adap) 458{ 459 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL; 460} 461 462static int 463mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 464{ 465 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap); 466 int i, rc; 467 468 for (i = 0; i < num; i++) { 469 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[i], 470 i == 0, i + 1 == num); 471 if (rc < 0) 472 return rc; 473 } 474 475 return num; 476} 477 478static const struct i2c_algorithm mv64xxx_i2c_algo = { 479 .master_xfer = mv64xxx_i2c_xfer, 480 .functionality = mv64xxx_i2c_functionality, 481}; 482 483/* 484 ***************************************************************************** 485 * 486 * Driver Interface & Early Init Routines 487 * 488 ***************************************************************************** 489 */ 490static int __devinit 491mv64xxx_i2c_map_regs(struct platform_device *pd, 492 struct mv64xxx_i2c_data *drv_data) 493{ 494 int size; 495 struct resource *r = platform_get_resource(pd, IORESOURCE_MEM, 0); 496 497 if (!r) 498 return -ENODEV; 499 500 size = resource_size(r); 501 502 if (!request_mem_region(r->start, size, drv_data->adapter.name)) 503 return -EBUSY; 504 505 drv_data->reg_base = ioremap(r->start, size); 506 drv_data->reg_base_p = r->start; 507 drv_data->reg_size = size; 508 509 return 0; 510} 511 512static void 513mv64xxx_i2c_unmap_regs(struct mv64xxx_i2c_data *drv_data) 514{ 515 if (drv_data->reg_base) { 516 iounmap(drv_data->reg_base); 517 release_mem_region(drv_data->reg_base_p, drv_data->reg_size); 518 } 519 520 drv_data->reg_base = NULL; 521 drv_data->reg_base_p = 0; 522} 523 524static int __devinit 525mv64xxx_i2c_probe(struct platform_device *pd) 526{ 527 struct mv64xxx_i2c_data *drv_data; 528 struct mv64xxx_i2c_pdata *pdata = pd->dev.platform_data; 529 int rc; 530 531 if ((pd->id != 0) || !pdata) 532 return -ENODEV; 533 534 drv_data = kzalloc(sizeof(struct mv64xxx_i2c_data), GFP_KERNEL); 535 if (!drv_data) 536 return -ENOMEM; 537 538 if (mv64xxx_i2c_map_regs(pd, drv_data)) { 539 rc = -ENODEV; 540 goto exit_kfree; 541 } 542 543 strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter", 544 sizeof(drv_data->adapter.name)); 545 546 init_waitqueue_head(&drv_data->waitq); 547 spin_lock_init(&drv_data->lock); 548 549 drv_data->freq_m = pdata->freq_m; 550 drv_data->freq_n = pdata->freq_n; 551 drv_data->irq = platform_get_irq(pd, 0); 552 if (drv_data->irq < 0) { 553 rc = -ENXIO; 554 goto exit_unmap_regs; 555 } 556 drv_data->adapter.dev.parent = &pd->dev; 557 drv_data->adapter.algo = &mv64xxx_i2c_algo; 558 drv_data->adapter.owner = THIS_MODULE; 559 drv_data->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 560 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout); 561 drv_data->adapter.nr = pd->id; 562 platform_set_drvdata(pd, drv_data); 563 i2c_set_adapdata(&drv_data->adapter, drv_data); 564 565 mv64xxx_i2c_hw_init(drv_data); 566 567 if (request_irq(drv_data->irq, mv64xxx_i2c_intr, 0, 568 MV64XXX_I2C_CTLR_NAME, drv_data)) { 569 dev_err(&drv_data->adapter.dev, 570 "mv64xxx: Can't register intr handler irq: %d\n", 571 drv_data->irq); 572 rc = -EINVAL; 573 goto exit_unmap_regs; 574 } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) { 575 dev_err(&drv_data->adapter.dev, 576 "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc); 577 goto exit_free_irq; 578 } 579 580 return 0; 581 582 exit_free_irq: 583 free_irq(drv_data->irq, drv_data); 584 exit_unmap_regs: 585 mv64xxx_i2c_unmap_regs(drv_data); 586 exit_kfree: 587 kfree(drv_data); 588 return rc; 589} 590 591static int __devexit 592mv64xxx_i2c_remove(struct platform_device *dev) 593{ 594 struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(dev); 595 int rc; 596 597 rc = i2c_del_adapter(&drv_data->adapter); 598 free_irq(drv_data->irq, drv_data); 599 mv64xxx_i2c_unmap_regs(drv_data); 600 kfree(drv_data); 601 602 return rc; 603} 604 605static struct platform_driver mv64xxx_i2c_driver = { 606 .probe = mv64xxx_i2c_probe, 607 .remove = __devexit_p(mv64xxx_i2c_remove), 608 .driver = { 609 .owner = THIS_MODULE, 610 .name = MV64XXX_I2C_CTLR_NAME, 611 }, 612}; 613 614module_platform_driver(mv64xxx_i2c_driver); 615 616MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>"); 617MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver"); 618MODULE_LICENSE("GPL"); 619