1/* 2 * Copyright (c) 2008, 2009 QLogic Corporation. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33#include <linux/pci.h> 34#include <linux/io.h> 35#include <linux/delay.h> 36#include <linux/vmalloc.h> 37#include <linux/aer.h> 38#include <linux/module.h> 39 40#include "qib.h" 41 42/* 43 * This file contains PCIe utility routines that are common to the 44 * various QLogic InfiniPath adapters 45 */ 46 47/* 48 * Code to adjust PCIe capabilities. 49 * To minimize the change footprint, we call it 50 * from qib_pcie_params, which every chip-specific 51 * file calls, even though this violates some 52 * expectations of harmlessness. 53 */ 54static int qib_tune_pcie_caps(struct qib_devdata *); 55static int qib_tune_pcie_coalesce(struct qib_devdata *); 56 57/* 58 * Do all the common PCIe setup and initialization. 59 * devdata is not yet allocated, and is not allocated until after this 60 * routine returns success. Therefore qib_dev_err() can't be used for error 61 * printing. 62 */ 63int qib_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent) 64{ 65 int ret; 66 67 ret = pci_enable_device(pdev); 68 if (ret) { 69 /* 70 * This can happen (in theory) iff: 71 * We did a chip reset, and then failed to reprogram the 72 * BAR, or the chip reset due to an internal error. We then 73 * unloaded the driver and reloaded it. 74 * 75 * Both reset cases set the BAR back to initial state. For 76 * the latter case, the AER sticky error bit at offset 0x718 77 * should be set, but the Linux kernel doesn't yet know 78 * about that, it appears. If the original BAR was retained 79 * in the kernel data structures, this may be OK. 80 */ 81 qib_early_err(&pdev->dev, "pci enable failed: error %d\n", 82 -ret); 83 goto done; 84 } 85 86 ret = pci_request_regions(pdev, QIB_DRV_NAME); 87 if (ret) { 88 qib_devinfo(pdev, "pci_request_regions fails: err %d\n", -ret); 89 goto bail; 90 } 91 92 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 93 if (ret) { 94 /* 95 * If the 64 bit setup fails, try 32 bit. Some systems 96 * do not setup 64 bit maps on systems with 2GB or less 97 * memory installed. 98 */ 99 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 100 if (ret) { 101 qib_devinfo(pdev, "Unable to set DMA mask: %d\n", ret); 102 goto bail; 103 } 104 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 105 } else 106 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 107 if (ret) { 108 qib_early_err(&pdev->dev, 109 "Unable to set DMA consistent mask: %d\n", ret); 110 goto bail; 111 } 112 113 pci_set_master(pdev); 114 ret = pci_enable_pcie_error_reporting(pdev); 115 if (ret) { 116 qib_early_err(&pdev->dev, 117 "Unable to enable pcie error reporting: %d\n", 118 ret); 119 ret = 0; 120 } 121 goto done; 122 123bail: 124 pci_disable_device(pdev); 125 pci_release_regions(pdev); 126done: 127 return ret; 128} 129 130/* 131 * Do remaining PCIe setup, once dd is allocated, and save away 132 * fields required to re-initialize after a chip reset, or for 133 * various other purposes 134 */ 135int qib_pcie_ddinit(struct qib_devdata *dd, struct pci_dev *pdev, 136 const struct pci_device_id *ent) 137{ 138 unsigned long len; 139 resource_size_t addr; 140 141 dd->pcidev = pdev; 142 pci_set_drvdata(pdev, dd); 143 144 addr = pci_resource_start(pdev, 0); 145 len = pci_resource_len(pdev, 0); 146 147#if defined(__powerpc__) 148 /* There isn't a generic way to specify writethrough mappings */ 149 dd->kregbase = __ioremap(addr, len, _PAGE_NO_CACHE | _PAGE_WRITETHRU); 150#else 151 dd->kregbase = ioremap_nocache(addr, len); 152#endif 153 154 if (!dd->kregbase) 155 return -ENOMEM; 156 157 dd->kregend = (u64 __iomem *)((void __iomem *) dd->kregbase + len); 158 dd->physaddr = addr; /* used for io_remap, etc. */ 159 160 /* 161 * Save BARs to rewrite after device reset. Save all 64 bits of 162 * BAR, just in case. 163 */ 164 dd->pcibar0 = addr; 165 dd->pcibar1 = addr >> 32; 166 dd->deviceid = ent->device; /* save for later use */ 167 dd->vendorid = ent->vendor; 168 169 return 0; 170} 171 172/* 173 * Do PCIe cleanup, after chip-specific cleanup, etc. Just prior 174 * to releasing the dd memory. 175 * void because none of the core pcie cleanup returns are void 176 */ 177void qib_pcie_ddcleanup(struct qib_devdata *dd) 178{ 179 u64 __iomem *base = (void __iomem *) dd->kregbase; 180 181 dd->kregbase = NULL; 182 iounmap(base); 183 if (dd->piobase) 184 iounmap(dd->piobase); 185 if (dd->userbase) 186 iounmap(dd->userbase); 187 if (dd->piovl15base) 188 iounmap(dd->piovl15base); 189 190 pci_disable_device(dd->pcidev); 191 pci_release_regions(dd->pcidev); 192 193 pci_set_drvdata(dd->pcidev, NULL); 194} 195 196static void qib_msix_setup(struct qib_devdata *dd, int pos, u32 *msixcnt, 197 struct qib_msix_entry *qib_msix_entry) 198{ 199 int ret; 200 u32 tabsize = 0; 201 u16 msix_flags; 202 struct msix_entry *msix_entry; 203 int i; 204 205 /* We can't pass qib_msix_entry array to qib_msix_setup 206 * so use a dummy msix_entry array and copy the allocated 207 * irq back to the qib_msix_entry array. */ 208 msix_entry = kmalloc(*msixcnt * sizeof(*msix_entry), GFP_KERNEL); 209 if (!msix_entry) { 210 ret = -ENOMEM; 211 goto do_intx; 212 } 213 for (i = 0; i < *msixcnt; i++) 214 msix_entry[i] = qib_msix_entry[i].msix; 215 216 pci_read_config_word(dd->pcidev, pos + PCI_MSIX_FLAGS, &msix_flags); 217 tabsize = 1 + (msix_flags & PCI_MSIX_FLAGS_QSIZE); 218 if (tabsize > *msixcnt) 219 tabsize = *msixcnt; 220 ret = pci_enable_msix(dd->pcidev, msix_entry, tabsize); 221 if (ret > 0) { 222 tabsize = ret; 223 ret = pci_enable_msix(dd->pcidev, msix_entry, tabsize); 224 } 225do_intx: 226 if (ret) { 227 qib_dev_err(dd, "pci_enable_msix %d vectors failed: %d, " 228 "falling back to INTx\n", tabsize, ret); 229 tabsize = 0; 230 } 231 for (i = 0; i < tabsize; i++) 232 qib_msix_entry[i].msix = msix_entry[i]; 233 kfree(msix_entry); 234 *msixcnt = tabsize; 235 236 if (ret) 237 qib_enable_intx(dd->pcidev); 238 239} 240 241/** 242 * We save the msi lo and hi values, so we can restore them after 243 * chip reset (the kernel PCI infrastructure doesn't yet handle that 244 * correctly. 245 */ 246static int qib_msi_setup(struct qib_devdata *dd, int pos) 247{ 248 struct pci_dev *pdev = dd->pcidev; 249 u16 control; 250 int ret; 251 252 ret = pci_enable_msi(pdev); 253 if (ret) 254 qib_dev_err(dd, "pci_enable_msi failed: %d, " 255 "interrupts may not work\n", ret); 256 /* continue even if it fails, we may still be OK... */ 257 258 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_LO, 259 &dd->msi_lo); 260 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_HI, 261 &dd->msi_hi); 262 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); 263 /* now save the data (vector) info */ 264 pci_read_config_word(pdev, pos + ((control & PCI_MSI_FLAGS_64BIT) 265 ? 12 : 8), 266 &dd->msi_data); 267 return ret; 268} 269 270int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent, 271 struct qib_msix_entry *entry) 272{ 273 u16 linkstat, speed; 274 int pos = 0, pose, ret = 1; 275 276 pose = pci_pcie_cap(dd->pcidev); 277 if (!pose) { 278 qib_dev_err(dd, "Can't find PCI Express capability!\n"); 279 /* set up something... */ 280 dd->lbus_width = 1; 281 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */ 282 goto bail; 283 } 284 285 pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSIX); 286 if (nent && *nent && pos) { 287 qib_msix_setup(dd, pos, nent, entry); 288 ret = 0; /* did it, either MSIx or INTx */ 289 } else { 290 pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI); 291 if (pos) 292 ret = qib_msi_setup(dd, pos); 293 else 294 qib_dev_err(dd, "No PCI MSI or MSIx capability!\n"); 295 } 296 if (!pos) 297 qib_enable_intx(dd->pcidev); 298 299 pci_read_config_word(dd->pcidev, pose + PCI_EXP_LNKSTA, &linkstat); 300 /* 301 * speed is bits 0-3, linkwidth is bits 4-8 302 * no defines for them in headers 303 */ 304 speed = linkstat & 0xf; 305 linkstat >>= 4; 306 linkstat &= 0x1f; 307 dd->lbus_width = linkstat; 308 309 switch (speed) { 310 case 1: 311 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */ 312 break; 313 case 2: 314 dd->lbus_speed = 5000; /* Gen1, 5GHz */ 315 break; 316 default: /* not defined, assume gen1 */ 317 dd->lbus_speed = 2500; 318 break; 319 } 320 321 /* 322 * Check against expected pcie width and complain if "wrong" 323 * on first initialization, not afterwards (i.e., reset). 324 */ 325 if (minw && linkstat < minw) 326 qib_dev_err(dd, 327 "PCIe width %u (x%u HCA), performance reduced\n", 328 linkstat, minw); 329 330 qib_tune_pcie_caps(dd); 331 332 qib_tune_pcie_coalesce(dd); 333 334bail: 335 /* fill in string, even on errors */ 336 snprintf(dd->lbus_info, sizeof(dd->lbus_info), 337 "PCIe,%uMHz,x%u\n", dd->lbus_speed, dd->lbus_width); 338 return ret; 339} 340 341/* 342 * Setup pcie interrupt stuff again after a reset. I'd like to just call 343 * pci_enable_msi() again for msi, but when I do that, 344 * the MSI enable bit doesn't get set in the command word, and 345 * we switch to to a different interrupt vector, which is confusing, 346 * so I instead just do it all inline. Perhaps somehow can tie this 347 * into the PCIe hotplug support at some point 348 */ 349int qib_reinit_intr(struct qib_devdata *dd) 350{ 351 int pos; 352 u16 control; 353 int ret = 0; 354 355 /* If we aren't using MSI, don't restore it */ 356 if (!dd->msi_lo) 357 goto bail; 358 359 pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI); 360 if (!pos) { 361 qib_dev_err(dd, "Can't find MSI capability, " 362 "can't restore MSI settings\n"); 363 ret = 0; 364 /* nothing special for MSIx, just MSI */ 365 goto bail; 366 } 367 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO, 368 dd->msi_lo); 369 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI, 370 dd->msi_hi); 371 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control); 372 if (!(control & PCI_MSI_FLAGS_ENABLE)) { 373 control |= PCI_MSI_FLAGS_ENABLE; 374 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, 375 control); 376 } 377 /* now rewrite the data (vector) info */ 378 pci_write_config_word(dd->pcidev, pos + 379 ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8), 380 dd->msi_data); 381 ret = 1; 382bail: 383 if (!ret && (dd->flags & QIB_HAS_INTX)) { 384 qib_enable_intx(dd->pcidev); 385 ret = 1; 386 } 387 388 /* and now set the pci master bit again */ 389 pci_set_master(dd->pcidev); 390 391 return ret; 392} 393 394/* 395 * Disable msi interrupt if enabled, and clear msi_lo. 396 * This is used primarily for the fallback to INTx, but 397 * is also used in reinit after reset, and during cleanup. 398 */ 399void qib_nomsi(struct qib_devdata *dd) 400{ 401 dd->msi_lo = 0; 402 pci_disable_msi(dd->pcidev); 403} 404 405/* 406 * Same as qib_nosmi, but for MSIx. 407 */ 408void qib_nomsix(struct qib_devdata *dd) 409{ 410 pci_disable_msix(dd->pcidev); 411} 412 413/* 414 * Similar to pci_intx(pdev, 1), except that we make sure 415 * msi(x) is off. 416 */ 417void qib_enable_intx(struct pci_dev *pdev) 418{ 419 u16 cw, new; 420 int pos; 421 422 /* first, turn on INTx */ 423 pci_read_config_word(pdev, PCI_COMMAND, &cw); 424 new = cw & ~PCI_COMMAND_INTX_DISABLE; 425 if (new != cw) 426 pci_write_config_word(pdev, PCI_COMMAND, new); 427 428 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); 429 if (pos) { 430 /* then turn off MSI */ 431 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &cw); 432 new = cw & ~PCI_MSI_FLAGS_ENABLE; 433 if (new != cw) 434 pci_write_config_word(pdev, pos + PCI_MSI_FLAGS, new); 435 } 436 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 437 if (pos) { 438 /* then turn off MSIx */ 439 pci_read_config_word(pdev, pos + PCI_MSIX_FLAGS, &cw); 440 new = cw & ~PCI_MSIX_FLAGS_ENABLE; 441 if (new != cw) 442 pci_write_config_word(pdev, pos + PCI_MSIX_FLAGS, new); 443 } 444} 445 446/* 447 * These two routines are helper routines for the device reset code 448 * to move all the pcie code out of the chip-specific driver code. 449 */ 450void qib_pcie_getcmd(struct qib_devdata *dd, u16 *cmd, u8 *iline, u8 *cline) 451{ 452 pci_read_config_word(dd->pcidev, PCI_COMMAND, cmd); 453 pci_read_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline); 454 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline); 455} 456 457void qib_pcie_reenable(struct qib_devdata *dd, u16 cmd, u8 iline, u8 cline) 458{ 459 int r; 460 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, 461 dd->pcibar0); 462 if (r) 463 qib_dev_err(dd, "rewrite of BAR0 failed: %d\n", r); 464 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, 465 dd->pcibar1); 466 if (r) 467 qib_dev_err(dd, "rewrite of BAR1 failed: %d\n", r); 468 /* now re-enable memory access, and restore cosmetic settings */ 469 pci_write_config_word(dd->pcidev, PCI_COMMAND, cmd); 470 pci_write_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline); 471 pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline); 472 r = pci_enable_device(dd->pcidev); 473 if (r) 474 qib_dev_err(dd, "pci_enable_device failed after " 475 "reset: %d\n", r); 476} 477 478/* code to adjust PCIe capabilities. */ 479 480static int fld2val(int wd, int mask) 481{ 482 int lsbmask; 483 484 if (!mask) 485 return 0; 486 wd &= mask; 487 lsbmask = mask ^ (mask & (mask - 1)); 488 wd /= lsbmask; 489 return wd; 490} 491 492static int val2fld(int wd, int mask) 493{ 494 int lsbmask; 495 496 if (!mask) 497 return 0; 498 lsbmask = mask ^ (mask & (mask - 1)); 499 wd *= lsbmask; 500 return wd; 501} 502 503static int qib_pcie_coalesce; 504module_param_named(pcie_coalesce, qib_pcie_coalesce, int, S_IRUGO); 505MODULE_PARM_DESC(pcie_coalesce, "tune PCIe colescing on some Intel chipsets"); 506 507/* 508 * Enable PCIe completion and data coalescing, on Intel 5x00 and 7300 509 * chipsets. This is known to be unsafe for some revisions of some 510 * of these chipsets, with some BIOS settings, and enabling it on those 511 * systems may result in the system crashing, and/or data corruption. 512 */ 513static int qib_tune_pcie_coalesce(struct qib_devdata *dd) 514{ 515 int r; 516 struct pci_dev *parent; 517 int ppos; 518 u16 devid; 519 u32 mask, bits, val; 520 521 if (!qib_pcie_coalesce) 522 return 0; 523 524 /* Find out supported and configured values for parent (root) */ 525 parent = dd->pcidev->bus->self; 526 if (parent->bus->parent) { 527 qib_devinfo(dd->pcidev, "Parent not root\n"); 528 return 1; 529 } 530 ppos = pci_pcie_cap(parent); 531 if (!ppos) 532 return 1; 533 if (parent->vendor != 0x8086) 534 return 1; 535 536 /* 537 * - bit 12: Max_rdcmp_Imt_EN: need to set to 1 538 * - bit 11: COALESCE_FORCE: need to set to 0 539 * - bit 10: COALESCE_EN: need to set to 1 540 * (but limitations on some on some chipsets) 541 * 542 * On the Intel 5000, 5100, and 7300 chipsets, there is 543 * also: - bit 25:24: COALESCE_MODE, need to set to 0 544 */ 545 devid = parent->device; 546 if (devid >= 0x25e2 && devid <= 0x25fa) { 547 /* 5000 P/V/X/Z */ 548 if (parent->revision <= 0xb2) 549 bits = 1U << 10; 550 else 551 bits = 7U << 10; 552 mask = (3U << 24) | (7U << 10); 553 } else if (devid >= 0x65e2 && devid <= 0x65fa) { 554 /* 5100 */ 555 bits = 1U << 10; 556 mask = (3U << 24) | (7U << 10); 557 } else if (devid >= 0x4021 && devid <= 0x402e) { 558 /* 5400 */ 559 bits = 7U << 10; 560 mask = 7U << 10; 561 } else if (devid >= 0x3604 && devid <= 0x360a) { 562 /* 7300 */ 563 bits = 7U << 10; 564 mask = (3U << 24) | (7U << 10); 565 } else { 566 /* not one of the chipsets that we know about */ 567 return 1; 568 } 569 pci_read_config_dword(parent, 0x48, &val); 570 val &= ~mask; 571 val |= bits; 572 r = pci_write_config_dword(parent, 0x48, val); 573 return 0; 574} 575 576/* 577 * BIOS may not set PCIe bus-utilization parameters for best performance. 578 * Check and optionally adjust them to maximize our throughput. 579 */ 580static int qib_pcie_caps; 581module_param_named(pcie_caps, qib_pcie_caps, int, S_IRUGO); 582MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)"); 583 584static int qib_tune_pcie_caps(struct qib_devdata *dd) 585{ 586 int ret = 1; /* Assume the worst */ 587 struct pci_dev *parent; 588 int ppos, epos; 589 u16 pcaps, pctl, ecaps, ectl; 590 int rc_sup, ep_sup; 591 int rc_cur, ep_cur; 592 593 /* Find out supported and configured values for parent (root) */ 594 parent = dd->pcidev->bus->self; 595 if (parent->bus->parent) { 596 qib_devinfo(dd->pcidev, "Parent not root\n"); 597 goto bail; 598 } 599 ppos = pci_pcie_cap(parent); 600 if (ppos) { 601 pci_read_config_word(parent, ppos + PCI_EXP_DEVCAP, &pcaps); 602 pci_read_config_word(parent, ppos + PCI_EXP_DEVCTL, &pctl); 603 } else 604 goto bail; 605 /* Find out supported and configured values for endpoint (us) */ 606 epos = pci_pcie_cap(dd->pcidev); 607 if (epos) { 608 pci_read_config_word(dd->pcidev, epos + PCI_EXP_DEVCAP, &ecaps); 609 pci_read_config_word(dd->pcidev, epos + PCI_EXP_DEVCTL, &ectl); 610 } else 611 goto bail; 612 ret = 0; 613 /* Find max payload supported by root, endpoint */ 614 rc_sup = fld2val(pcaps, PCI_EXP_DEVCAP_PAYLOAD); 615 ep_sup = fld2val(ecaps, PCI_EXP_DEVCAP_PAYLOAD); 616 if (rc_sup > ep_sup) 617 rc_sup = ep_sup; 618 619 rc_cur = fld2val(pctl, PCI_EXP_DEVCTL_PAYLOAD); 620 ep_cur = fld2val(ectl, PCI_EXP_DEVCTL_PAYLOAD); 621 622 /* If Supported greater than limit in module param, limit it */ 623 if (rc_sup > (qib_pcie_caps & 7)) 624 rc_sup = qib_pcie_caps & 7; 625 /* If less than (allowed, supported), bump root payload */ 626 if (rc_sup > rc_cur) { 627 rc_cur = rc_sup; 628 pctl = (pctl & ~PCI_EXP_DEVCTL_PAYLOAD) | 629 val2fld(rc_cur, PCI_EXP_DEVCTL_PAYLOAD); 630 pci_write_config_word(parent, ppos + PCI_EXP_DEVCTL, pctl); 631 } 632 /* If less than (allowed, supported), bump endpoint payload */ 633 if (rc_sup > ep_cur) { 634 ep_cur = rc_sup; 635 ectl = (ectl & ~PCI_EXP_DEVCTL_PAYLOAD) | 636 val2fld(ep_cur, PCI_EXP_DEVCTL_PAYLOAD); 637 pci_write_config_word(dd->pcidev, epos + PCI_EXP_DEVCTL, ectl); 638 } 639 640 /* 641 * Now the Read Request size. 642 * No field for max supported, but PCIe spec limits it to 4096, 643 * which is code '5' (log2(4096) - 7) 644 */ 645 rc_sup = 5; 646 if (rc_sup > ((qib_pcie_caps >> 4) & 7)) 647 rc_sup = (qib_pcie_caps >> 4) & 7; 648 rc_cur = fld2val(pctl, PCI_EXP_DEVCTL_READRQ); 649 ep_cur = fld2val(ectl, PCI_EXP_DEVCTL_READRQ); 650 651 if (rc_sup > rc_cur) { 652 rc_cur = rc_sup; 653 pctl = (pctl & ~PCI_EXP_DEVCTL_READRQ) | 654 val2fld(rc_cur, PCI_EXP_DEVCTL_READRQ); 655 pci_write_config_word(parent, ppos + PCI_EXP_DEVCTL, pctl); 656 } 657 if (rc_sup > ep_cur) { 658 ep_cur = rc_sup; 659 ectl = (ectl & ~PCI_EXP_DEVCTL_READRQ) | 660 val2fld(ep_cur, PCI_EXP_DEVCTL_READRQ); 661 pci_write_config_word(dd->pcidev, epos + PCI_EXP_DEVCTL, ectl); 662 } 663bail: 664 return ret; 665} 666/* End of PCIe capability tuning */ 667 668/* 669 * From here through qib_pci_err_handler definition is invoked via 670 * PCI error infrastructure, registered via pci 671 */ 672static pci_ers_result_t 673qib_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 674{ 675 struct qib_devdata *dd = pci_get_drvdata(pdev); 676 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; 677 678 switch (state) { 679 case pci_channel_io_normal: 680 qib_devinfo(pdev, "State Normal, ignoring\n"); 681 break; 682 683 case pci_channel_io_frozen: 684 qib_devinfo(pdev, "State Frozen, requesting reset\n"); 685 pci_disable_device(pdev); 686 ret = PCI_ERS_RESULT_NEED_RESET; 687 break; 688 689 case pci_channel_io_perm_failure: 690 qib_devinfo(pdev, "State Permanent Failure, disabling\n"); 691 if (dd) { 692 /* no more register accesses! */ 693 dd->flags &= ~QIB_PRESENT; 694 qib_disable_after_error(dd); 695 } 696 /* else early, or other problem */ 697 ret = PCI_ERS_RESULT_DISCONNECT; 698 break; 699 700 default: /* shouldn't happen */ 701 qib_devinfo(pdev, "QIB PCI errors detected (state %d)\n", 702 state); 703 break; 704 } 705 return ret; 706} 707 708static pci_ers_result_t 709qib_pci_mmio_enabled(struct pci_dev *pdev) 710{ 711 u64 words = 0U; 712 struct qib_devdata *dd = pci_get_drvdata(pdev); 713 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; 714 715 if (dd && dd->pport) { 716 words = dd->f_portcntr(dd->pport, QIBPORTCNTR_WORDRCV); 717 if (words == ~0ULL) 718 ret = PCI_ERS_RESULT_NEED_RESET; 719 } 720 qib_devinfo(pdev, "QIB mmio_enabled function called, " 721 "read wordscntr %Lx, returning %d\n", words, ret); 722 return ret; 723} 724 725static pci_ers_result_t 726qib_pci_slot_reset(struct pci_dev *pdev) 727{ 728 qib_devinfo(pdev, "QIB link_reset function called, ignored\n"); 729 return PCI_ERS_RESULT_CAN_RECOVER; 730} 731 732static pci_ers_result_t 733qib_pci_link_reset(struct pci_dev *pdev) 734{ 735 qib_devinfo(pdev, "QIB link_reset function called, ignored\n"); 736 return PCI_ERS_RESULT_CAN_RECOVER; 737} 738 739static void 740qib_pci_resume(struct pci_dev *pdev) 741{ 742 struct qib_devdata *dd = pci_get_drvdata(pdev); 743 qib_devinfo(pdev, "QIB resume function called\n"); 744 pci_cleanup_aer_uncorrect_error_status(pdev); 745 /* 746 * Running jobs will fail, since it's asynchronous 747 * unlike sysfs-requested reset. Better than 748 * doing nothing. 749 */ 750 qib_init(dd, 1); /* same as re-init after reset */ 751} 752 753struct pci_error_handlers qib_pci_err_handler = { 754 .error_detected = qib_pci_error_detected, 755 .mmio_enabled = qib_pci_mmio_enabled, 756 .link_reset = qib_pci_link_reset, 757 .slot_reset = qib_pci_slot_reset, 758 .resume = qib_pci_resume, 759}; 760