1/* 2 * ddbridge.c: Digital Devices PCIe bridge driver 3 * 4 * Copyright (C) 2010-2011 Digital Devices GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 only, as published by the Free Software Foundation. 9 * 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 20 * 02110-1301, USA 21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html 22 */ 23 24#include <linux/module.h> 25#include <linux/init.h> 26#include <linux/interrupt.h> 27#include <linux/delay.h> 28#include <linux/slab.h> 29#include <linux/poll.h> 30#include <linux/io.h> 31#include <linux/pci.h> 32#include <linux/pci_ids.h> 33#include <linux/timer.h> 34#include <linux/version.h> 35#include <linux/i2c.h> 36#include <linux/swab.h> 37#include <linux/vmalloc.h> 38#include "ddbridge.h" 39 40#include "ddbridge-regs.h" 41 42#include "tda18271c2dd.h" 43#include "stv6110x.h" 44#include "stv090x.h" 45#include "lnbh24.h" 46#include "drxk.h" 47 48DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); 49 50/* MSI had problems with lost interrupts, fixed but needs testing */ 51#undef CONFIG_PCI_MSI 52 53/******************************************************************************/ 54 55static int i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val) 56{ 57 struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, 58 .buf = val, .len = 1 } }; 59 return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; 60} 61 62static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, u8 reg, u8 *val) 63{ 64 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, 65 .buf = ®, .len = 1 }, 66 {.addr = adr, .flags = I2C_M_RD, 67 .buf = val, .len = 1 } }; 68 return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; 69} 70 71static int i2c_read_reg16(struct i2c_adapter *adapter, u8 adr, 72 u16 reg, u8 *val) 73{ 74 u8 msg[2] = {reg>>8, reg&0xff}; 75 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, 76 .buf = msg, .len = 2}, 77 {.addr = adr, .flags = I2C_M_RD, 78 .buf = val, .len = 1} }; 79 return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; 80} 81 82static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd) 83{ 84 struct ddb *dev = i2c->dev; 85 int stat; 86 u32 val; 87 88 i2c->done = 0; 89 ddbwritel((adr << 9) | cmd, i2c->regs + I2C_COMMAND); 90 stat = wait_event_timeout(i2c->wq, i2c->done == 1, HZ); 91 if (stat <= 0) { 92 printk(KERN_ERR "I2C timeout\n"); 93 { /* MSI debugging*/ 94 u32 istat = ddbreadl(INTERRUPT_STATUS); 95 printk(KERN_ERR "IRS %08x\n", istat); 96 ddbwritel(istat, INTERRUPT_ACK); 97 } 98 return -EIO; 99 } 100 val = ddbreadl(i2c->regs+I2C_COMMAND); 101 if (val & 0x70000) 102 return -EIO; 103 return 0; 104} 105 106static int ddb_i2c_master_xfer(struct i2c_adapter *adapter, 107 struct i2c_msg msg[], int num) 108{ 109 struct ddb_i2c *i2c = (struct ddb_i2c *)i2c_get_adapdata(adapter); 110 struct ddb *dev = i2c->dev; 111 u8 addr = 0; 112 113 if (num) 114 addr = msg[0].addr; 115 116 if (num == 2 && msg[1].flags & I2C_M_RD && 117 !(msg[0].flags & I2C_M_RD)) { 118 memcpy_toio(dev->regs + I2C_TASKMEM_BASE + i2c->wbuf, 119 msg[0].buf, msg[0].len); 120 ddbwritel(msg[0].len|(msg[1].len << 16), 121 i2c->regs+I2C_TASKLENGTH); 122 if (!ddb_i2c_cmd(i2c, addr, 1)) { 123 memcpy_fromio(msg[1].buf, 124 dev->regs + I2C_TASKMEM_BASE + i2c->rbuf, 125 msg[1].len); 126 return num; 127 } 128 } 129 130 if (num == 1 && !(msg[0].flags & I2C_M_RD)) { 131 ddbcpyto(I2C_TASKMEM_BASE + i2c->wbuf, msg[0].buf, msg[0].len); 132 ddbwritel(msg[0].len, i2c->regs + I2C_TASKLENGTH); 133 if (!ddb_i2c_cmd(i2c, addr, 2)) 134 return num; 135 } 136 if (num == 1 && (msg[0].flags & I2C_M_RD)) { 137 ddbwritel(msg[0].len << 16, i2c->regs + I2C_TASKLENGTH); 138 if (!ddb_i2c_cmd(i2c, addr, 3)) { 139 ddbcpyfrom(msg[0].buf, 140 I2C_TASKMEM_BASE + i2c->rbuf, msg[0].len); 141 return num; 142 } 143 } 144 return -EIO; 145} 146 147 148static u32 ddb_i2c_functionality(struct i2c_adapter *adap) 149{ 150 return I2C_FUNC_SMBUS_EMUL; 151} 152 153struct i2c_algorithm ddb_i2c_algo = { 154 .master_xfer = ddb_i2c_master_xfer, 155 .functionality = ddb_i2c_functionality, 156}; 157 158static void ddb_i2c_release(struct ddb *dev) 159{ 160 int i; 161 struct ddb_i2c *i2c; 162 struct i2c_adapter *adap; 163 164 for (i = 0; i < dev->info->port_num; i++) { 165 i2c = &dev->i2c[i]; 166 adap = &i2c->adap; 167 i2c_del_adapter(adap); 168 } 169} 170 171static int ddb_i2c_init(struct ddb *dev) 172{ 173 int i, j, stat = 0; 174 struct ddb_i2c *i2c; 175 struct i2c_adapter *adap; 176 177 for (i = 0; i < dev->info->port_num; i++) { 178 i2c = &dev->i2c[i]; 179 i2c->dev = dev; 180 i2c->nr = i; 181 i2c->wbuf = i * (I2C_TASKMEM_SIZE / 4); 182 i2c->rbuf = i2c->wbuf + (I2C_TASKMEM_SIZE / 8); 183 i2c->regs = 0x80 + i * 0x20; 184 ddbwritel(I2C_SPEED_100, i2c->regs + I2C_TIMING); 185 ddbwritel((i2c->rbuf << 16) | i2c->wbuf, 186 i2c->regs + I2C_TASKADDRESS); 187 init_waitqueue_head(&i2c->wq); 188 189 adap = &i2c->adap; 190 i2c_set_adapdata(adap, i2c); 191#ifdef I2C_ADAP_CLASS_TV_DIGITAL 192 adap->class = I2C_ADAP_CLASS_TV_DIGITAL|I2C_CLASS_TV_ANALOG; 193#else 194#ifdef I2C_CLASS_TV_ANALOG 195 adap->class = I2C_CLASS_TV_ANALOG; 196#endif 197#endif 198 strcpy(adap->name, "ddbridge"); 199 adap->algo = &ddb_i2c_algo; 200 adap->algo_data = (void *)i2c; 201 adap->dev.parent = &dev->pdev->dev; 202 stat = i2c_add_adapter(adap); 203 if (stat) 204 break; 205 } 206 if (stat) 207 for (j = 0; j < i; j++) { 208 i2c = &dev->i2c[j]; 209 adap = &i2c->adap; 210 i2c_del_adapter(adap); 211 } 212 return stat; 213} 214 215 216/******************************************************************************/ 217/******************************************************************************/ 218/******************************************************************************/ 219 220#if 0 221static void set_table(struct ddb *dev, u32 off, 222 dma_addr_t *pbuf, u32 num) 223{ 224 u32 i, base; 225 u64 mem; 226 227 base = DMA_BASE_ADDRESS_TABLE + off; 228 for (i = 0; i < num; i++) { 229 mem = pbuf[i]; 230 ddbwritel(mem & 0xffffffff, base + i * 8); 231 ddbwritel(mem >> 32, base + i * 8 + 4); 232 } 233} 234#endif 235 236static void ddb_address_table(struct ddb *dev) 237{ 238 u32 i, j, base; 239 u64 mem; 240 dma_addr_t *pbuf; 241 242 for (i = 0; i < dev->info->port_num * 2; i++) { 243 base = DMA_BASE_ADDRESS_TABLE + i * 0x100; 244 pbuf = dev->input[i].pbuf; 245 for (j = 0; j < dev->input[i].dma_buf_num; j++) { 246 mem = pbuf[j]; 247 ddbwritel(mem & 0xffffffff, base + j * 8); 248 ddbwritel(mem >> 32, base + j * 8 + 4); 249 } 250 } 251 for (i = 0; i < dev->info->port_num; i++) { 252 base = DMA_BASE_ADDRESS_TABLE + 0x800 + i * 0x100; 253 pbuf = dev->output[i].pbuf; 254 for (j = 0; j < dev->output[i].dma_buf_num; j++) { 255 mem = pbuf[j]; 256 ddbwritel(mem & 0xffffffff, base + j * 8); 257 ddbwritel(mem >> 32, base + j * 8 + 4); 258 } 259 } 260} 261 262static void io_free(struct pci_dev *pdev, u8 **vbuf, 263 dma_addr_t *pbuf, u32 size, int num) 264{ 265 int i; 266 267 for (i = 0; i < num; i++) { 268 if (vbuf[i]) { 269 pci_free_consistent(pdev, size, vbuf[i], pbuf[i]); 270 vbuf[i] = 0; 271 } 272 } 273} 274 275static int io_alloc(struct pci_dev *pdev, u8 **vbuf, 276 dma_addr_t *pbuf, u32 size, int num) 277{ 278 int i; 279 280 for (i = 0; i < num; i++) { 281 vbuf[i] = pci_alloc_consistent(pdev, size, &pbuf[i]); 282 if (!vbuf[i]) 283 return -ENOMEM; 284 } 285 return 0; 286} 287 288static int ddb_buffers_alloc(struct ddb *dev) 289{ 290 int i; 291 struct ddb_port *port; 292 293 for (i = 0; i < dev->info->port_num; i++) { 294 port = &dev->port[i]; 295 switch (port->class) { 296 case DDB_PORT_TUNER: 297 if (io_alloc(dev->pdev, port->input[0]->vbuf, 298 port->input[0]->pbuf, 299 port->input[0]->dma_buf_size, 300 port->input[0]->dma_buf_num) < 0) 301 return -1; 302 if (io_alloc(dev->pdev, port->input[1]->vbuf, 303 port->input[1]->pbuf, 304 port->input[1]->dma_buf_size, 305 port->input[1]->dma_buf_num) < 0) 306 return -1; 307 break; 308 case DDB_PORT_CI: 309 if (io_alloc(dev->pdev, port->input[0]->vbuf, 310 port->input[0]->pbuf, 311 port->input[0]->dma_buf_size, 312 port->input[0]->dma_buf_num) < 0) 313 return -1; 314 if (io_alloc(dev->pdev, port->output->vbuf, 315 port->output->pbuf, 316 port->output->dma_buf_size, 317 port->output->dma_buf_num) < 0) 318 return -1; 319 break; 320 default: 321 break; 322 } 323 } 324 ddb_address_table(dev); 325 return 0; 326} 327 328static void ddb_buffers_free(struct ddb *dev) 329{ 330 int i; 331 struct ddb_port *port; 332 333 for (i = 0; i < dev->info->port_num; i++) { 334 port = &dev->port[i]; 335 io_free(dev->pdev, port->input[0]->vbuf, 336 port->input[0]->pbuf, 337 port->input[0]->dma_buf_size, 338 port->input[0]->dma_buf_num); 339 io_free(dev->pdev, port->input[1]->vbuf, 340 port->input[1]->pbuf, 341 port->input[1]->dma_buf_size, 342 port->input[1]->dma_buf_num); 343 io_free(dev->pdev, port->output->vbuf, 344 port->output->pbuf, 345 port->output->dma_buf_size, 346 port->output->dma_buf_num); 347 } 348} 349 350static void ddb_input_start(struct ddb_input *input) 351{ 352 struct ddb *dev = input->port->dev; 353 354 spin_lock_irq(&input->lock); 355 input->cbuf = 0; 356 input->coff = 0; 357 358 /* reset */ 359 ddbwritel(0, TS_INPUT_CONTROL(input->nr)); 360 ddbwritel(2, TS_INPUT_CONTROL(input->nr)); 361 ddbwritel(0, TS_INPUT_CONTROL(input->nr)); 362 363 ddbwritel((1 << 16) | 364 (input->dma_buf_num << 11) | 365 (input->dma_buf_size >> 7), 366 DMA_BUFFER_SIZE(input->nr)); 367 ddbwritel(0, DMA_BUFFER_ACK(input->nr)); 368 369 ddbwritel(1, DMA_BASE_WRITE); 370 ddbwritel(3, DMA_BUFFER_CONTROL(input->nr)); 371 ddbwritel(9, TS_INPUT_CONTROL(input->nr)); 372 input->running = 1; 373 spin_unlock_irq(&input->lock); 374} 375 376static void ddb_input_stop(struct ddb_input *input) 377{ 378 struct ddb *dev = input->port->dev; 379 380 spin_lock_irq(&input->lock); 381 ddbwritel(0, TS_INPUT_CONTROL(input->nr)); 382 ddbwritel(0, DMA_BUFFER_CONTROL(input->nr)); 383 input->running = 0; 384 spin_unlock_irq(&input->lock); 385} 386 387static void ddb_output_start(struct ddb_output *output) 388{ 389 struct ddb *dev = output->port->dev; 390 391 spin_lock_irq(&output->lock); 392 output->cbuf = 0; 393 output->coff = 0; 394 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr)); 395 ddbwritel(2, TS_OUTPUT_CONTROL(output->nr)); 396 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr)); 397 ddbwritel(0x3c, TS_OUTPUT_CONTROL(output->nr)); 398 ddbwritel((1 << 16) | 399 (output->dma_buf_num << 11) | 400 (output->dma_buf_size >> 7), 401 DMA_BUFFER_SIZE(output->nr + 8)); 402 ddbwritel(0, DMA_BUFFER_ACK(output->nr + 8)); 403 404 ddbwritel(1, DMA_BASE_READ); 405 ddbwritel(3, DMA_BUFFER_CONTROL(output->nr + 8)); 406 /* ddbwritel(0xbd, TS_OUTPUT_CONTROL(output->nr)); */ 407 ddbwritel(0x1d, TS_OUTPUT_CONTROL(output->nr)); 408 output->running = 1; 409 spin_unlock_irq(&output->lock); 410} 411 412static void ddb_output_stop(struct ddb_output *output) 413{ 414 struct ddb *dev = output->port->dev; 415 416 spin_lock_irq(&output->lock); 417 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr)); 418 ddbwritel(0, DMA_BUFFER_CONTROL(output->nr + 8)); 419 output->running = 0; 420 spin_unlock_irq(&output->lock); 421} 422 423static u32 ddb_output_free(struct ddb_output *output) 424{ 425 u32 idx, off, stat = output->stat; 426 s32 diff; 427 428 idx = (stat >> 11) & 0x1f; 429 off = (stat & 0x7ff) << 7; 430 431 if (output->cbuf != idx) { 432 if ((((output->cbuf + 1) % output->dma_buf_num) == idx) && 433 (output->dma_buf_size - output->coff <= 188)) 434 return 0; 435 return 188; 436 } 437 diff = off - output->coff; 438 if (diff <= 0 || diff > 188) 439 return 188; 440 return 0; 441} 442 443static ssize_t ddb_output_write(struct ddb_output *output, 444 const u8 *buf, size_t count) 445{ 446 struct ddb *dev = output->port->dev; 447 u32 idx, off, stat = output->stat; 448 u32 left = count, len; 449 450 idx = (stat >> 11) & 0x1f; 451 off = (stat & 0x7ff) << 7; 452 453 while (left) { 454 len = output->dma_buf_size - output->coff; 455 if ((((output->cbuf + 1) % output->dma_buf_num) == idx) && 456 (off == 0)) { 457 if (len <= 188) 458 break; 459 len -= 188; 460 } 461 if (output->cbuf == idx) { 462 if (off > output->coff) { 463#if 1 464 len = off - output->coff; 465 len -= (len % 188); 466 if (len <= 188) 467 468#endif 469 break; 470 len -= 188; 471 } 472 } 473 if (len > left) 474 len = left; 475 if (copy_from_user(output->vbuf[output->cbuf] + output->coff, 476 buf, len)) 477 return -EIO; 478 left -= len; 479 buf += len; 480 output->coff += len; 481 if (output->coff == output->dma_buf_size) { 482 output->coff = 0; 483 output->cbuf = ((output->cbuf + 1) % output->dma_buf_num); 484 } 485 ddbwritel((output->cbuf << 11) | (output->coff >> 7), 486 DMA_BUFFER_ACK(output->nr + 8)); 487 } 488 return count - left; 489} 490 491static u32 ddb_input_avail(struct ddb_input *input) 492{ 493 struct ddb *dev = input->port->dev; 494 u32 idx, off, stat = input->stat; 495 u32 ctrl = ddbreadl(DMA_BUFFER_CONTROL(input->nr)); 496 497 idx = (stat >> 11) & 0x1f; 498 off = (stat & 0x7ff) << 7; 499 500 if (ctrl & 4) { 501 printk(KERN_ERR "IA %d %d %08x\n", idx, off, ctrl); 502 ddbwritel(input->stat, DMA_BUFFER_ACK(input->nr)); 503 return 0; 504 } 505 if (input->cbuf != idx) 506 return 188; 507 return 0; 508} 509 510static ssize_t ddb_input_read(struct ddb_input *input, u8 *buf, size_t count) 511{ 512 struct ddb *dev = input->port->dev; 513 u32 left = count; 514 u32 idx, free, stat = input->stat; 515 int ret; 516 517 idx = (stat >> 11) & 0x1f; 518 519 while (left) { 520 if (input->cbuf == idx) 521 return count - left; 522 free = input->dma_buf_size - input->coff; 523 if (free > left) 524 free = left; 525 ret = copy_to_user(buf, input->vbuf[input->cbuf] + 526 input->coff, free); 527 if (ret) 528 return -EFAULT; 529 input->coff += free; 530 if (input->coff == input->dma_buf_size) { 531 input->coff = 0; 532 input->cbuf = (input->cbuf+1) % input->dma_buf_num; 533 } 534 left -= free; 535 ddbwritel((input->cbuf << 11) | (input->coff >> 7), 536 DMA_BUFFER_ACK(input->nr)); 537 } 538 return count; 539} 540 541/******************************************************************************/ 542/******************************************************************************/ 543/******************************************************************************/ 544 545#if 0 546static struct ddb_input *fe2input(struct ddb *dev, struct dvb_frontend *fe) 547{ 548 int i; 549 550 for (i = 0; i < dev->info->port_num * 2; i++) { 551 if (dev->input[i].fe == fe) 552 return &dev->input[i]; 553 } 554 return NULL; 555} 556#endif 557 558static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable) 559{ 560 struct ddb_input *input = fe->sec_priv; 561 struct ddb_port *port = input->port; 562 int status; 563 564 if (enable) { 565 mutex_lock(&port->i2c_gate_lock); 566 status = input->gate_ctrl(fe, 1); 567 } else { 568 status = input->gate_ctrl(fe, 0); 569 mutex_unlock(&port->i2c_gate_lock); 570 } 571 return status; 572} 573 574static int demod_attach_drxk(struct ddb_input *input) 575{ 576 struct i2c_adapter *i2c = &input->port->i2c->adap; 577 struct dvb_frontend *fe; 578 struct drxk_config config; 579 580 memset(&config, 0, sizeof(config)); 581 config.microcode_name = "drxk_a3.mc"; 582 config.adr = 0x29 + (input->nr & 1); 583 584 fe = input->fe = dvb_attach(drxk_attach, &config, i2c); 585 if (!input->fe) { 586 printk(KERN_ERR "No DRXK found!\n"); 587 return -ENODEV; 588 } 589 fe->sec_priv = input; 590 input->gate_ctrl = fe->ops.i2c_gate_ctrl; 591 fe->ops.i2c_gate_ctrl = drxk_gate_ctrl; 592 return 0; 593} 594 595static int tuner_attach_tda18271(struct ddb_input *input) 596{ 597 struct i2c_adapter *i2c = &input->port->i2c->adap; 598 struct dvb_frontend *fe; 599 600 if (input->fe->ops.i2c_gate_ctrl) 601 input->fe->ops.i2c_gate_ctrl(input->fe, 1); 602 fe = dvb_attach(tda18271c2dd_attach, input->fe, i2c, 0x60); 603 if (!fe) { 604 printk(KERN_ERR "No TDA18271 found!\n"); 605 return -ENODEV; 606 } 607 if (input->fe->ops.i2c_gate_ctrl) 608 input->fe->ops.i2c_gate_ctrl(input->fe, 0); 609 return 0; 610} 611 612/******************************************************************************/ 613/******************************************************************************/ 614/******************************************************************************/ 615 616static struct stv090x_config stv0900 = { 617 .device = STV0900, 618 .demod_mode = STV090x_DUAL, 619 .clk_mode = STV090x_CLK_EXT, 620 621 .xtal = 27000000, 622 .address = 0x69, 623 624 .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED, 625 .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED, 626 627 .repeater_level = STV090x_RPTLEVEL_16, 628 629 .adc1_range = STV090x_ADC_1Vpp, 630 .adc2_range = STV090x_ADC_1Vpp, 631 632 .diseqc_envelope_mode = true, 633}; 634 635static struct stv090x_config stv0900_aa = { 636 .device = STV0900, 637 .demod_mode = STV090x_DUAL, 638 .clk_mode = STV090x_CLK_EXT, 639 640 .xtal = 27000000, 641 .address = 0x68, 642 643 .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED, 644 .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED, 645 646 .repeater_level = STV090x_RPTLEVEL_16, 647 648 .adc1_range = STV090x_ADC_1Vpp, 649 .adc2_range = STV090x_ADC_1Vpp, 650 651 .diseqc_envelope_mode = true, 652}; 653 654static struct stv6110x_config stv6110a = { 655 .addr = 0x60, 656 .refclk = 27000000, 657 .clk_div = 1, 658}; 659 660static struct stv6110x_config stv6110b = { 661 .addr = 0x63, 662 .refclk = 27000000, 663 .clk_div = 1, 664}; 665 666static int demod_attach_stv0900(struct ddb_input *input, int type) 667{ 668 struct i2c_adapter *i2c = &input->port->i2c->adap; 669 struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900; 670 671 input->fe = dvb_attach(stv090x_attach, feconf, i2c, 672 (input->nr & 1) ? STV090x_DEMODULATOR_1 673 : STV090x_DEMODULATOR_0); 674 if (!input->fe) { 675 printk(KERN_ERR "No STV0900 found!\n"); 676 return -ENODEV; 677 } 678 if (!dvb_attach(lnbh24_attach, input->fe, i2c, 0, 679 0, (input->nr & 1) ? 680 (0x09 - type) : (0x0b - type))) { 681 printk(KERN_ERR "No LNBH24 found!\n"); 682 return -ENODEV; 683 } 684 return 0; 685} 686 687static int tuner_attach_stv6110(struct ddb_input *input, int type) 688{ 689 struct i2c_adapter *i2c = &input->port->i2c->adap; 690 struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900; 691 struct stv6110x_config *tunerconf = (input->nr & 1) ? 692 &stv6110b : &stv6110a; 693 struct stv6110x_devctl *ctl; 694 695 ctl = dvb_attach(stv6110x_attach, input->fe, tunerconf, i2c); 696 if (!ctl) { 697 printk(KERN_ERR "No STV6110X found!\n"); 698 return -ENODEV; 699 } 700 printk(KERN_INFO "attach tuner input %d adr %02x\n", 701 input->nr, tunerconf->addr); 702 703 feconf->tuner_init = ctl->tuner_init; 704 feconf->tuner_sleep = ctl->tuner_sleep; 705 feconf->tuner_set_mode = ctl->tuner_set_mode; 706 feconf->tuner_set_frequency = ctl->tuner_set_frequency; 707 feconf->tuner_get_frequency = ctl->tuner_get_frequency; 708 feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth; 709 feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth; 710 feconf->tuner_set_bbgain = ctl->tuner_set_bbgain; 711 feconf->tuner_get_bbgain = ctl->tuner_get_bbgain; 712 feconf->tuner_set_refclk = ctl->tuner_set_refclk; 713 feconf->tuner_get_status = ctl->tuner_get_status; 714 715 return 0; 716} 717 718static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id, 719 int (*start_feed)(struct dvb_demux_feed *), 720 int (*stop_feed)(struct dvb_demux_feed *), 721 void *priv) 722{ 723 dvbdemux->priv = priv; 724 725 dvbdemux->filternum = 256; 726 dvbdemux->feednum = 256; 727 dvbdemux->start_feed = start_feed; 728 dvbdemux->stop_feed = stop_feed; 729 dvbdemux->write_to_decoder = NULL; 730 dvbdemux->dmx.capabilities = (DMX_TS_FILTERING | 731 DMX_SECTION_FILTERING | 732 DMX_MEMORY_BASED_FILTERING); 733 return dvb_dmx_init(dvbdemux); 734} 735 736static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev, 737 struct dvb_demux *dvbdemux, 738 struct dmx_frontend *hw_frontend, 739 struct dmx_frontend *mem_frontend, 740 struct dvb_adapter *dvb_adapter) 741{ 742 int ret; 743 744 dmxdev->filternum = 256; 745 dmxdev->demux = &dvbdemux->dmx; 746 dmxdev->capabilities = 0; 747 ret = dvb_dmxdev_init(dmxdev, dvb_adapter); 748 if (ret < 0) 749 return ret; 750 751 hw_frontend->source = DMX_FRONTEND_0; 752 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend); 753 mem_frontend->source = DMX_MEMORY_FE; 754 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend); 755 return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend); 756} 757 758static int start_feed(struct dvb_demux_feed *dvbdmxfeed) 759{ 760 struct dvb_demux *dvbdmx = dvbdmxfeed->demux; 761 struct ddb_input *input = dvbdmx->priv; 762 763 if (!input->users) 764 ddb_input_start(input); 765 766 return ++input->users; 767} 768 769static int stop_feed(struct dvb_demux_feed *dvbdmxfeed) 770{ 771 struct dvb_demux *dvbdmx = dvbdmxfeed->demux; 772 struct ddb_input *input = dvbdmx->priv; 773 774 if (--input->users) 775 return input->users; 776 777 ddb_input_stop(input); 778 return 0; 779} 780 781 782static void dvb_input_detach(struct ddb_input *input) 783{ 784 struct dvb_adapter *adap = &input->adap; 785 struct dvb_demux *dvbdemux = &input->demux; 786 787 switch (input->attached) { 788 case 5: 789 if (input->fe2) 790 dvb_unregister_frontend(input->fe2); 791 if (input->fe) { 792 dvb_unregister_frontend(input->fe); 793 dvb_frontend_detach(input->fe); 794 input->fe = NULL; 795 } 796 case 4: 797 dvb_net_release(&input->dvbnet); 798 799 case 3: 800 dvbdemux->dmx.close(&dvbdemux->dmx); 801 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, 802 &input->hw_frontend); 803 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, 804 &input->mem_frontend); 805 dvb_dmxdev_release(&input->dmxdev); 806 807 case 2: 808 dvb_dmx_release(&input->demux); 809 810 case 1: 811 dvb_unregister_adapter(adap); 812 } 813 input->attached = 0; 814} 815 816static int dvb_input_attach(struct ddb_input *input) 817{ 818 int ret; 819 struct ddb_port *port = input->port; 820 struct dvb_adapter *adap = &input->adap; 821 struct dvb_demux *dvbdemux = &input->demux; 822 823 ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE, 824 &input->port->dev->pdev->dev, 825 adapter_nr); 826 if (ret < 0) { 827 printk(KERN_ERR "ddbridge: Could not register adapter." 828 "Check if you enabled enough adapters in dvb-core!\n"); 829 return ret; 830 } 831 input->attached = 1; 832 833 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux", 834 start_feed, 835 stop_feed, input); 836 if (ret < 0) 837 return ret; 838 input->attached = 2; 839 840 ret = my_dvb_dmxdev_ts_card_init(&input->dmxdev, &input->demux, 841 &input->hw_frontend, 842 &input->mem_frontend, adap); 843 if (ret < 0) 844 return ret; 845 input->attached = 3; 846 847 ret = dvb_net_init(adap, &input->dvbnet, input->dmxdev.demux); 848 if (ret < 0) 849 return ret; 850 input->attached = 4; 851 852 input->fe = 0; 853 switch (port->type) { 854 case DDB_TUNER_DVBS_ST: 855 if (demod_attach_stv0900(input, 0) < 0) 856 return -ENODEV; 857 if (tuner_attach_stv6110(input, 0) < 0) 858 return -ENODEV; 859 if (input->fe) { 860 if (dvb_register_frontend(adap, input->fe) < 0) 861 return -ENODEV; 862 } 863 break; 864 case DDB_TUNER_DVBS_ST_AA: 865 if (demod_attach_stv0900(input, 1) < 0) 866 return -ENODEV; 867 if (tuner_attach_stv6110(input, 1) < 0) 868 return -ENODEV; 869 if (input->fe) { 870 if (dvb_register_frontend(adap, input->fe) < 0) 871 return -ENODEV; 872 } 873 break; 874 case DDB_TUNER_DVBCT_TR: 875 if (demod_attach_drxk(input) < 0) 876 return -ENODEV; 877 if (tuner_attach_tda18271(input) < 0) 878 return -ENODEV; 879 if (input->fe) { 880 if (dvb_register_frontend(adap, input->fe) < 0) 881 return -ENODEV; 882 } 883 if (input->fe2) { 884 if (dvb_register_frontend(adap, input->fe2) < 0) 885 return -ENODEV; 886 input->fe2->tuner_priv = input->fe->tuner_priv; 887 memcpy(&input->fe2->ops.tuner_ops, 888 &input->fe->ops.tuner_ops, 889 sizeof(struct dvb_tuner_ops)); 890 } 891 break; 892 } 893 input->attached = 5; 894 return 0; 895} 896 897/****************************************************************************/ 898/****************************************************************************/ 899 900static ssize_t ts_write(struct file *file, const char *buf, 901 size_t count, loff_t *ppos) 902{ 903 struct dvb_device *dvbdev = file->private_data; 904 struct ddb_output *output = dvbdev->priv; 905 size_t left = count; 906 int stat; 907 908 while (left) { 909 if (ddb_output_free(output) < 188) { 910 if (file->f_flags & O_NONBLOCK) 911 break; 912 if (wait_event_interruptible( 913 output->wq, ddb_output_free(output) >= 188) < 0) 914 break; 915 } 916 stat = ddb_output_write(output, buf, left); 917 if (stat < 0) 918 break; 919 buf += stat; 920 left -= stat; 921 } 922 return (left == count) ? -EAGAIN : (count - left); 923} 924 925static ssize_t ts_read(struct file *file, char *buf, 926 size_t count, loff_t *ppos) 927{ 928 struct dvb_device *dvbdev = file->private_data; 929 struct ddb_output *output = dvbdev->priv; 930 struct ddb_input *input = output->port->input[0]; 931 int left, read; 932 933 count -= count % 188; 934 left = count; 935 while (left) { 936 if (ddb_input_avail(input) < 188) { 937 if (file->f_flags & O_NONBLOCK) 938 break; 939 if (wait_event_interruptible( 940 input->wq, ddb_input_avail(input) >= 188) < 0) 941 break; 942 } 943 read = ddb_input_read(input, buf, left); 944 if (read < 0) 945 return read; 946 left -= read; 947 buf += read; 948 } 949 return (left == count) ? -EAGAIN : (count - left); 950} 951 952static unsigned int ts_poll(struct file *file, poll_table *wait) 953{ 954 /* 955 struct dvb_device *dvbdev = file->private_data; 956 struct ddb_output *output = dvbdev->priv; 957 struct ddb_input *input = output->port->input[0]; 958 */ 959 unsigned int mask = 0; 960 961#if 0 962 if (data_avail_to_read) 963 mask |= POLLIN | POLLRDNORM; 964 if (data_avail_to_write) 965 mask |= POLLOUT | POLLWRNORM; 966 967 poll_wait(file, &read_queue, wait); 968 poll_wait(file, &write_queue, wait); 969#endif 970 return mask; 971} 972 973static const struct file_operations ci_fops = { 974 .owner = THIS_MODULE, 975 .read = ts_read, 976 .write = ts_write, 977 .open = dvb_generic_open, 978 .release = dvb_generic_release, 979 .poll = ts_poll, 980 .mmap = 0, 981}; 982 983static struct dvb_device dvbdev_ci = { 984 .priv = 0, 985 .readers = -1, 986 .writers = -1, 987 .users = -1, 988 .fops = &ci_fops, 989}; 990 991/****************************************************************************/ 992/****************************************************************************/ 993/****************************************************************************/ 994 995static void input_tasklet(unsigned long data) 996{ 997 struct ddb_input *input = (struct ddb_input *) data; 998 struct ddb *dev = input->port->dev; 999 1000 spin_lock(&input->lock); 1001 if (!input->running) { 1002 spin_unlock(&input->lock); 1003 return; 1004 } 1005 input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr)); 1006 1007 if (input->port->class == DDB_PORT_TUNER) { 1008 if (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr))) 1009 printk(KERN_ERR "Overflow input %d\n", input->nr); 1010 while (input->cbuf != ((input->stat >> 11) & 0x1f) 1011 || (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))) { 1012 dvb_dmx_swfilter_packets(&input->demux, 1013 input->vbuf[input->cbuf], 1014 input->dma_buf_size / 188); 1015 1016 input->cbuf = (input->cbuf + 1) % input->dma_buf_num; 1017 ddbwritel((input->cbuf << 11), 1018 DMA_BUFFER_ACK(input->nr)); 1019 input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr)); 1020 } 1021 } 1022 if (input->port->class == DDB_PORT_CI) 1023 wake_up(&input->wq); 1024 spin_unlock(&input->lock); 1025} 1026 1027static void output_tasklet(unsigned long data) 1028{ 1029 struct ddb_output *output = (struct ddb_output *) data; 1030 struct ddb *dev = output->port->dev; 1031 1032 spin_lock(&output->lock); 1033 if (!output->running) { 1034 spin_unlock(&output->lock); 1035 return; 1036 } 1037 output->stat = ddbreadl(DMA_BUFFER_CURRENT(output->nr + 8)); 1038 wake_up(&output->wq); 1039 spin_unlock(&output->lock); 1040} 1041 1042 1043struct cxd2099_cfg cxd_cfg = { 1044 .bitrate = 62000, 1045 .adr = 0x40, 1046 .polarity = 1, 1047 .clock_mode = 1, 1048}; 1049 1050static int ddb_ci_attach(struct ddb_port *port) 1051{ 1052 int ret; 1053 1054 ret = dvb_register_adapter(&port->output->adap, 1055 "DDBridge", 1056 THIS_MODULE, 1057 &port->dev->pdev->dev, 1058 adapter_nr); 1059 if (ret < 0) 1060 return ret; 1061 port->en = cxd2099_attach(&cxd_cfg, port, &port->i2c->adap); 1062 if (!port->en) { 1063 dvb_unregister_adapter(&port->output->adap); 1064 return -ENODEV; 1065 } 1066 ddb_input_start(port->input[0]); 1067 ddb_output_start(port->output); 1068 dvb_ca_en50221_init(&port->output->adap, 1069 port->en, 0, 1); 1070 ret = dvb_register_device(&port->output->adap, &port->output->dev, 1071 &dvbdev_ci, (void *) port->output, 1072 DVB_DEVICE_SEC); 1073 return ret; 1074} 1075 1076static int ddb_port_attach(struct ddb_port *port) 1077{ 1078 int ret = 0; 1079 1080 switch (port->class) { 1081 case DDB_PORT_TUNER: 1082 ret = dvb_input_attach(port->input[0]); 1083 if (ret < 0) 1084 break; 1085 ret = dvb_input_attach(port->input[1]); 1086 break; 1087 case DDB_PORT_CI: 1088 ret = ddb_ci_attach(port); 1089 break; 1090 default: 1091 break; 1092 } 1093 if (ret < 0) 1094 printk(KERN_ERR "port_attach on port %d failed\n", port->nr); 1095 return ret; 1096} 1097 1098static int ddb_ports_attach(struct ddb *dev) 1099{ 1100 int i, ret = 0; 1101 struct ddb_port *port; 1102 1103 for (i = 0; i < dev->info->port_num; i++) { 1104 port = &dev->port[i]; 1105 ret = ddb_port_attach(port); 1106 if (ret < 0) 1107 break; 1108 } 1109 return ret; 1110} 1111 1112static void ddb_ports_detach(struct ddb *dev) 1113{ 1114 int i; 1115 struct ddb_port *port; 1116 1117 for (i = 0; i < dev->info->port_num; i++) { 1118 port = &dev->port[i]; 1119 switch (port->class) { 1120 case DDB_PORT_TUNER: 1121 dvb_input_detach(port->input[0]); 1122 dvb_input_detach(port->input[1]); 1123 break; 1124 case DDB_PORT_CI: 1125 if (port->output->dev) 1126 dvb_unregister_device(port->output->dev); 1127 if (port->en) { 1128 ddb_input_stop(port->input[0]); 1129 ddb_output_stop(port->output); 1130 dvb_ca_en50221_release(port->en); 1131 kfree(port->en); 1132 port->en = 0; 1133 dvb_unregister_adapter(&port->output->adap); 1134 } 1135 break; 1136 } 1137 } 1138} 1139 1140/****************************************************************************/ 1141/****************************************************************************/ 1142 1143static int port_has_ci(struct ddb_port *port) 1144{ 1145 u8 val; 1146 return i2c_read_reg(&port->i2c->adap, 0x40, 0, &val) ? 0 : 1; 1147} 1148 1149static int port_has_stv0900(struct ddb_port *port) 1150{ 1151 u8 val; 1152 if (i2c_read_reg16(&port->i2c->adap, 0x69, 0xf100, &val) < 0) 1153 return 0; 1154 return 1; 1155} 1156 1157static int port_has_stv0900_aa(struct ddb_port *port) 1158{ 1159 u8 val; 1160 if (i2c_read_reg16(&port->i2c->adap, 0x68, 0xf100, &val) < 0) 1161 return 0; 1162 return 1; 1163} 1164 1165static int port_has_drxks(struct ddb_port *port) 1166{ 1167 u8 val; 1168 if (i2c_read(&port->i2c->adap, 0x29, &val) < 0) 1169 return 0; 1170 if (i2c_read(&port->i2c->adap, 0x2a, &val) < 0) 1171 return 0; 1172 return 1; 1173} 1174 1175static void ddb_port_probe(struct ddb_port *port) 1176{ 1177 struct ddb *dev = port->dev; 1178 char *modname = "NO MODULE"; 1179 1180 port->class = DDB_PORT_NONE; 1181 1182 if (port_has_ci(port)) { 1183 modname = "CI"; 1184 port->class = DDB_PORT_CI; 1185 ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING); 1186 } else if (port_has_stv0900(port)) { 1187 modname = "DUAL DVB-S2"; 1188 port->class = DDB_PORT_TUNER; 1189 port->type = DDB_TUNER_DVBS_ST; 1190 ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING); 1191 } else if (port_has_stv0900_aa(port)) { 1192 modname = "DUAL DVB-S2"; 1193 port->class = DDB_PORT_TUNER; 1194 port->type = DDB_TUNER_DVBS_ST_AA; 1195 ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING); 1196 } else if (port_has_drxks(port)) { 1197 modname = "DUAL DVB-C/T"; 1198 port->class = DDB_PORT_TUNER; 1199 port->type = DDB_TUNER_DVBCT_TR; 1200 ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING); 1201 } 1202 printk(KERN_INFO "Port %d (TAB %d): %s\n", 1203 port->nr, port->nr+1, modname); 1204} 1205 1206static void ddb_input_init(struct ddb_port *port, int nr) 1207{ 1208 struct ddb *dev = port->dev; 1209 struct ddb_input *input = &dev->input[nr]; 1210 1211 input->nr = nr; 1212 input->port = port; 1213 input->dma_buf_num = INPUT_DMA_BUFS; 1214 input->dma_buf_size = INPUT_DMA_SIZE; 1215 ddbwritel(0, TS_INPUT_CONTROL(nr)); 1216 ddbwritel(2, TS_INPUT_CONTROL(nr)); 1217 ddbwritel(0, TS_INPUT_CONTROL(nr)); 1218 ddbwritel(0, DMA_BUFFER_ACK(nr)); 1219 tasklet_init(&input->tasklet, input_tasklet, (unsigned long) input); 1220 spin_lock_init(&input->lock); 1221 init_waitqueue_head(&input->wq); 1222} 1223 1224static void ddb_output_init(struct ddb_port *port, int nr) 1225{ 1226 struct ddb *dev = port->dev; 1227 struct ddb_output *output = &dev->output[nr]; 1228 output->nr = nr; 1229 output->port = port; 1230 output->dma_buf_num = OUTPUT_DMA_BUFS; 1231 output->dma_buf_size = OUTPUT_DMA_SIZE; 1232 1233 ddbwritel(0, TS_OUTPUT_CONTROL(nr)); 1234 ddbwritel(2, TS_OUTPUT_CONTROL(nr)); 1235 ddbwritel(0, TS_OUTPUT_CONTROL(nr)); 1236 tasklet_init(&output->tasklet, output_tasklet, (unsigned long) output); 1237 init_waitqueue_head(&output->wq); 1238} 1239 1240static void ddb_ports_init(struct ddb *dev) 1241{ 1242 int i; 1243 struct ddb_port *port; 1244 1245 for (i = 0; i < dev->info->port_num; i++) { 1246 port = &dev->port[i]; 1247 port->dev = dev; 1248 port->nr = i; 1249 port->i2c = &dev->i2c[i]; 1250 port->input[0] = &dev->input[2 * i]; 1251 port->input[1] = &dev->input[2 * i + 1]; 1252 port->output = &dev->output[i]; 1253 1254 mutex_init(&port->i2c_gate_lock); 1255 ddb_port_probe(port); 1256 ddb_input_init(port, 2 * i); 1257 ddb_input_init(port, 2 * i + 1); 1258 ddb_output_init(port, i); 1259 } 1260} 1261 1262static void ddb_ports_release(struct ddb *dev) 1263{ 1264 int i; 1265 struct ddb_port *port; 1266 1267 for (i = 0; i < dev->info->port_num; i++) { 1268 port = &dev->port[i]; 1269 port->dev = dev; 1270 tasklet_kill(&port->input[0]->tasklet); 1271 tasklet_kill(&port->input[1]->tasklet); 1272 tasklet_kill(&port->output->tasklet); 1273 } 1274} 1275 1276/****************************************************************************/ 1277/****************************************************************************/ 1278/****************************************************************************/ 1279 1280static void irq_handle_i2c(struct ddb *dev, int n) 1281{ 1282 struct ddb_i2c *i2c = &dev->i2c[n]; 1283 1284 i2c->done = 1; 1285 wake_up(&i2c->wq); 1286} 1287 1288static irqreturn_t irq_handler(int irq, void *dev_id) 1289{ 1290 struct ddb *dev = (struct ddb *) dev_id; 1291 u32 s = ddbreadl(INTERRUPT_STATUS); 1292 1293 if (!s) 1294 return IRQ_NONE; 1295 1296 do { 1297 ddbwritel(s, INTERRUPT_ACK); 1298 1299 if (s & 0x00000001) 1300 irq_handle_i2c(dev, 0); 1301 if (s & 0x00000002) 1302 irq_handle_i2c(dev, 1); 1303 if (s & 0x00000004) 1304 irq_handle_i2c(dev, 2); 1305 if (s & 0x00000008) 1306 irq_handle_i2c(dev, 3); 1307 1308 if (s & 0x00000100) 1309 tasklet_schedule(&dev->input[0].tasklet); 1310 if (s & 0x00000200) 1311 tasklet_schedule(&dev->input[1].tasklet); 1312 if (s & 0x00000400) 1313 tasklet_schedule(&dev->input[2].tasklet); 1314 if (s & 0x00000800) 1315 tasklet_schedule(&dev->input[3].tasklet); 1316 if (s & 0x00001000) 1317 tasklet_schedule(&dev->input[4].tasklet); 1318 if (s & 0x00002000) 1319 tasklet_schedule(&dev->input[5].tasklet); 1320 if (s & 0x00004000) 1321 tasklet_schedule(&dev->input[6].tasklet); 1322 if (s & 0x00008000) 1323 tasklet_schedule(&dev->input[7].tasklet); 1324 1325 if (s & 0x00010000) 1326 tasklet_schedule(&dev->output[0].tasklet); 1327 if (s & 0x00020000) 1328 tasklet_schedule(&dev->output[1].tasklet); 1329 if (s & 0x00040000) 1330 tasklet_schedule(&dev->output[2].tasklet); 1331 if (s & 0x00080000) 1332 tasklet_schedule(&dev->output[3].tasklet); 1333 1334 /* if (s & 0x000f0000) printk(KERN_DEBUG "%08x\n", istat); */ 1335 } while ((s = ddbreadl(INTERRUPT_STATUS))); 1336 1337 return IRQ_HANDLED; 1338} 1339 1340/******************************************************************************/ 1341/******************************************************************************/ 1342/******************************************************************************/ 1343 1344static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) 1345{ 1346 u32 data, shift; 1347 1348 if (wlen > 4) 1349 ddbwritel(1, SPI_CONTROL); 1350 while (wlen > 4) { 1351 /* FIXME: check for big-endian */ 1352 data = swab32(*(u32 *)wbuf); 1353 wbuf += 4; 1354 wlen -= 4; 1355 ddbwritel(data, SPI_DATA); 1356 while (ddbreadl(SPI_CONTROL) & 0x0004) 1357 ; 1358 } 1359 1360 if (rlen) 1361 ddbwritel(0x0001 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL); 1362 else 1363 ddbwritel(0x0003 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL); 1364 1365 data = 0; 1366 shift = ((4 - wlen) * 8); 1367 while (wlen) { 1368 data <<= 8; 1369 data |= *wbuf; 1370 wlen--; 1371 wbuf++; 1372 } 1373 if (shift) 1374 data <<= shift; 1375 ddbwritel(data, SPI_DATA); 1376 while (ddbreadl(SPI_CONTROL) & 0x0004) 1377 ; 1378 1379 if (!rlen) { 1380 ddbwritel(0, SPI_CONTROL); 1381 return 0; 1382 } 1383 if (rlen > 4) 1384 ddbwritel(1, SPI_CONTROL); 1385 1386 while (rlen > 4) { 1387 ddbwritel(0xffffffff, SPI_DATA); 1388 while (ddbreadl(SPI_CONTROL) & 0x0004) 1389 ; 1390 data = ddbreadl(SPI_DATA); 1391 *(u32 *) rbuf = swab32(data); 1392 rbuf += 4; 1393 rlen -= 4; 1394 } 1395 ddbwritel(0x0003 | ((rlen << (8 + 3)) & 0x1F00), SPI_CONTROL); 1396 ddbwritel(0xffffffff, SPI_DATA); 1397 while (ddbreadl(SPI_CONTROL) & 0x0004) 1398 ; 1399 1400 data = ddbreadl(SPI_DATA); 1401 ddbwritel(0, SPI_CONTROL); 1402 1403 if (rlen < 4) 1404 data <<= ((4 - rlen) * 8); 1405 1406 while (rlen > 0) { 1407 *rbuf = ((data >> 24) & 0xff); 1408 data <<= 8; 1409 rbuf++; 1410 rlen--; 1411 } 1412 return 0; 1413} 1414 1415#define DDB_MAGIC 'd' 1416 1417struct ddb_flashio { 1418 __u8 *write_buf; 1419 __u32 write_len; 1420 __u8 *read_buf; 1421 __u32 read_len; 1422}; 1423 1424#define IOCTL_DDB_FLASHIO _IOWR(DDB_MAGIC, 0x00, struct ddb_flashio) 1425 1426#define DDB_NAME "ddbridge" 1427 1428static u32 ddb_num; 1429static struct ddb *ddbs[32]; 1430static struct class *ddb_class; 1431static int ddb_major; 1432 1433static int ddb_open(struct inode *inode, struct file *file) 1434{ 1435 struct ddb *dev = ddbs[iminor(inode)]; 1436 1437 file->private_data = dev; 1438 return 0; 1439} 1440 1441static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) 1442{ 1443 struct ddb *dev = file->private_data; 1444 void *parg = (void *)arg; 1445 int res; 1446 1447 switch (cmd) { 1448 case IOCTL_DDB_FLASHIO: 1449 { 1450 struct ddb_flashio fio; 1451 u8 *rbuf, *wbuf; 1452 1453 if (copy_from_user(&fio, parg, sizeof(fio))) 1454 return -EFAULT; 1455 1456 if (fio.write_len > 1028 || fio.read_len > 1028) 1457 return -EINVAL; 1458 if (fio.write_len + fio.read_len > 1028) 1459 return -EINVAL; 1460 1461 wbuf = &dev->iobuf[0]; 1462 rbuf = wbuf + fio.write_len; 1463 1464 if (copy_from_user(wbuf, fio.write_buf, fio.write_len)) 1465 return -EFAULT; 1466 res = flashio(dev, wbuf, fio.write_len, rbuf, fio.read_len); 1467 if (res) 1468 return res; 1469 if (copy_to_user(fio.read_buf, rbuf, fio.read_len)) 1470 return -EFAULT; 1471 break; 1472 } 1473 default: 1474 return -ENOTTY; 1475 } 1476 return 0; 1477} 1478 1479static const struct file_operations ddb_fops = { 1480 .unlocked_ioctl = ddb_ioctl, 1481 .open = ddb_open, 1482}; 1483 1484static char *ddb_devnode(struct device *device, umode_t *mode) 1485{ 1486 struct ddb *dev = dev_get_drvdata(device); 1487 1488 return kasprintf(GFP_KERNEL, "ddbridge/card%d", dev->nr); 1489} 1490 1491static int ddb_class_create(void) 1492{ 1493 ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops); 1494 if (ddb_major < 0) 1495 return ddb_major; 1496 1497 ddb_class = class_create(THIS_MODULE, DDB_NAME); 1498 if (IS_ERR(ddb_class)) { 1499 unregister_chrdev(ddb_major, DDB_NAME); 1500 return -1; 1501 } 1502 ddb_class->devnode = ddb_devnode; 1503 return 0; 1504} 1505 1506static void ddb_class_destroy(void) 1507{ 1508 class_destroy(ddb_class); 1509 unregister_chrdev(ddb_major, DDB_NAME); 1510} 1511 1512static int ddb_device_create(struct ddb *dev) 1513{ 1514 dev->nr = ddb_num++; 1515 dev->ddb_dev = device_create(ddb_class, NULL, 1516 MKDEV(ddb_major, dev->nr), 1517 dev, "ddbridge%d", dev->nr); 1518 ddbs[dev->nr] = dev; 1519 if (IS_ERR(dev->ddb_dev)) 1520 return -1; 1521 return 0; 1522} 1523 1524static void ddb_device_destroy(struct ddb *dev) 1525{ 1526 ddb_num--; 1527 if (IS_ERR(dev->ddb_dev)) 1528 return; 1529 device_destroy(ddb_class, MKDEV(ddb_major, 0)); 1530} 1531 1532 1533/****************************************************************************/ 1534/****************************************************************************/ 1535/****************************************************************************/ 1536 1537static void ddb_unmap(struct ddb *dev) 1538{ 1539 if (dev->regs) 1540 iounmap(dev->regs); 1541 vfree(dev); 1542} 1543 1544 1545static void __devexit ddb_remove(struct pci_dev *pdev) 1546{ 1547 struct ddb *dev = (struct ddb *) pci_get_drvdata(pdev); 1548 1549 ddb_ports_detach(dev); 1550 ddb_i2c_release(dev); 1551 1552 ddbwritel(0, INTERRUPT_ENABLE); 1553 free_irq(dev->pdev->irq, dev); 1554#ifdef CONFIG_PCI_MSI 1555 if (dev->msi) 1556 pci_disable_msi(dev->pdev); 1557#endif 1558 ddb_ports_release(dev); 1559 ddb_buffers_free(dev); 1560 ddb_device_destroy(dev); 1561 1562 ddb_unmap(dev); 1563 pci_set_drvdata(pdev, 0); 1564 pci_disable_device(pdev); 1565} 1566 1567 1568static int __devinit ddb_probe(struct pci_dev *pdev, 1569 const struct pci_device_id *id) 1570{ 1571 struct ddb *dev; 1572 int stat = 0; 1573 int irq_flag = IRQF_SHARED; 1574 1575 if (pci_enable_device(pdev) < 0) 1576 return -ENODEV; 1577 1578 dev = vmalloc(sizeof(struct ddb)); 1579 if (dev == NULL) 1580 return -ENOMEM; 1581 memset(dev, 0, sizeof(struct ddb)); 1582 1583 dev->pdev = pdev; 1584 pci_set_drvdata(pdev, dev); 1585 dev->info = (struct ddb_info *) id->driver_data; 1586 printk(KERN_INFO "DDBridge driver detected: %s\n", dev->info->name); 1587 1588 dev->regs = ioremap(pci_resource_start(dev->pdev, 0), 1589 pci_resource_len(dev->pdev, 0)); 1590 if (!dev->regs) { 1591 stat = -ENOMEM; 1592 goto fail; 1593 } 1594 printk(KERN_INFO "HW %08x FW %08x\n", ddbreadl(0), ddbreadl(4)); 1595 1596#ifdef CONFIG_PCI_MSI 1597 if (pci_msi_enabled()) 1598 stat = pci_enable_msi(dev->pdev); 1599 if (stat) { 1600 printk(KERN_INFO ": MSI not available.\n"); 1601 } else { 1602 irq_flag = 0; 1603 dev->msi = 1; 1604 } 1605#endif 1606 stat = request_irq(dev->pdev->irq, irq_handler, 1607 irq_flag, "DDBridge", (void *) dev); 1608 if (stat < 0) 1609 goto fail1; 1610 ddbwritel(0, DMA_BASE_WRITE); 1611 ddbwritel(0, DMA_BASE_READ); 1612 ddbwritel(0xffffffff, INTERRUPT_ACK); 1613 ddbwritel(0xfff0f, INTERRUPT_ENABLE); 1614 ddbwritel(0, MSI1_ENABLE); 1615 1616 if (ddb_i2c_init(dev) < 0) 1617 goto fail1; 1618 ddb_ports_init(dev); 1619 if (ddb_buffers_alloc(dev) < 0) { 1620 printk(KERN_INFO ": Could not allocate buffer memory\n"); 1621 goto fail2; 1622 } 1623 if (ddb_ports_attach(dev) < 0) 1624 goto fail3; 1625 ddb_device_create(dev); 1626 return 0; 1627 1628fail3: 1629 ddb_ports_detach(dev); 1630 printk(KERN_ERR "fail3\n"); 1631 ddb_ports_release(dev); 1632fail2: 1633 printk(KERN_ERR "fail2\n"); 1634 ddb_buffers_free(dev); 1635fail1: 1636 printk(KERN_ERR "fail1\n"); 1637 if (dev->msi) 1638 pci_disable_msi(dev->pdev); 1639 free_irq(dev->pdev->irq, dev); 1640fail: 1641 printk(KERN_ERR "fail\n"); 1642 ddb_unmap(dev); 1643 pci_set_drvdata(pdev, 0); 1644 pci_disable_device(pdev); 1645 return -1; 1646} 1647 1648/******************************************************************************/ 1649/******************************************************************************/ 1650/******************************************************************************/ 1651 1652static struct ddb_info ddb_none = { 1653 .type = DDB_NONE, 1654 .name = "Digital Devices PCIe bridge", 1655}; 1656 1657static struct ddb_info ddb_octopus = { 1658 .type = DDB_OCTOPUS, 1659 .name = "Digital Devices Octopus DVB adapter", 1660 .port_num = 4, 1661}; 1662 1663static struct ddb_info ddb_octopus_le = { 1664 .type = DDB_OCTOPUS, 1665 .name = "Digital Devices Octopus LE DVB adapter", 1666 .port_num = 2, 1667}; 1668 1669static struct ddb_info ddb_v6 = { 1670 .type = DDB_OCTOPUS, 1671 .name = "Digital Devices Cine S2 V6 DVB adapter", 1672 .port_num = 3, 1673}; 1674 1675#define DDVID 0xdd01 /* Digital Devices Vendor ID */ 1676 1677#define DDB_ID(_vend, _dev, _subvend, _subdev, _driverdata) { \ 1678 .vendor = _vend, .device = _dev, \ 1679 .subvendor = _subvend, .subdevice = _subdev, \ 1680 .driver_data = (unsigned long)&_driverdata } 1681 1682static const struct pci_device_id ddb_id_tbl[] __devinitdata = { 1683 DDB_ID(DDVID, 0x0002, DDVID, 0x0001, ddb_octopus), 1684 DDB_ID(DDVID, 0x0003, DDVID, 0x0001, ddb_octopus), 1685 DDB_ID(DDVID, 0x0003, DDVID, 0x0002, ddb_octopus_le), 1686 DDB_ID(DDVID, 0x0003, DDVID, 0x0010, ddb_octopus), 1687 DDB_ID(DDVID, 0x0003, DDVID, 0x0020, ddb_v6), 1688 /* in case sub-ids got deleted in flash */ 1689 DDB_ID(DDVID, 0x0003, PCI_ANY_ID, PCI_ANY_ID, ddb_none), 1690 {0} 1691}; 1692MODULE_DEVICE_TABLE(pci, ddb_id_tbl); 1693 1694 1695static struct pci_driver ddb_pci_driver = { 1696 .name = "DDBridge", 1697 .id_table = ddb_id_tbl, 1698 .probe = ddb_probe, 1699 .remove = ddb_remove, 1700}; 1701 1702static __init int module_init_ddbridge(void) 1703{ 1704 printk(KERN_INFO "Digital Devices PCIE bridge driver, " 1705 "Copyright (C) 2010-11 Digital Devices GmbH\n"); 1706 if (ddb_class_create()) 1707 return -1; 1708 return pci_register_driver(&ddb_pci_driver); 1709} 1710 1711static __exit void module_exit_ddbridge(void) 1712{ 1713 pci_unregister_driver(&ddb_pci_driver); 1714 ddb_class_destroy(); 1715} 1716 1717module_init(module_init_ddbridge); 1718module_exit(module_exit_ddbridge); 1719 1720MODULE_DESCRIPTION("Digital Devices PCIe Bridge"); 1721MODULE_AUTHOR("Ralph Metzler"); 1722MODULE_LICENSE("GPL"); 1723MODULE_VERSION("0.5"); 1724